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A fast-lock and low-power DLL-based clock generator applied for DDR4

January 2018
Microsystem Technologies 24(1)

January 2018
24(1)

DOI:10.1007/s00542-016-3206-7

Authors:

Yu-Lung Lo

National Kaohsiung Normal University

Wei-Bin Yang

Tamkang University

Show all 5 authorsHide

This paper presents a fast-lock and low-power delay-locked loop (DLL) circuit applied for DDR4. The proposed modified phase detector and modified charge pump can reduce locking time as well as static phase error. The glitch elimination circuit reduces glitches in the PD for reducing the glitch power. The phase interpolator and phase combiner circuit are used to generate four output frequencies: 0.2, 0.4, 0.8, and 1.6 GHz. The design is fabricated through a 0.18-μm standard CMOS process with a supply voltage of 1.8 V. The simulation results indicate that the lock time is less than 20 cycles and the power consumption of the DLL is 15.14 mW at 1.6 GHz. The active die area of the proposed DLL-based clock generator is 0.51 mm².

Architecture of the proposed DLL-based clock generator

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a Frequency of 2 × Fin (200 MHz) and b frequency of 4 × Fin (400 MHz)

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a Frequency spectra of 8 × Fin (800 MHz) and 16 × Fin (1.6 GHz) and b jitter performance at 1.6 GHz

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Behavior of Vctrl according to tracking time

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a Architecture of the PD and b timing diagram of the PD

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1 3

Microsyst Technol (2018) 24:137–146

https://doi.org/10.1007/s00542-016-3206-7

TECHNICAL PAPER

A fast‑lock and low‑power DLL‑based clock generator applied

for DDR4

Yu‑Lung Lo1 · Wei‑Bin Yang2 · Han‑Hsien Wang2 · Cing‑Huan Chen2 ·

Zi‑Ang Huang2

Received: 31 August 2016 / Accepted: 12 November 2016 / Published online: 22 November 2016

1 Introduction

Because of advances in process technology, digital inte-

grated circuit system synchronization has become crucial.

Speciﬁcally, in high-speed computing systems, clock offset

(clock skew) is a key factor for determining system per-

formance. DDR4 requires a high-speed, wide-range out-

put frequency, multi-output frequency, and low-jitter clock

generator (Tu et al. 2013; Yang et al. 2015). A phase-locked

loop (PLL) and delay-locked loop (DLL) can reduce clock

offset and increase circuit stability. In addition, a DLL has

less noise accumulation as well as being more stable than a

PLL. Therefore, DLLs has been widely used in the opera-

tion of clock circuits, such as synchronous dynamic RAM,

analog-to-digital converters, and digital signal processors.

In this work, a modiﬁed phase detector (MPD) and

modiﬁed charge pump (MCP) are proposed for improving

locking speed. Moreover, a glitch elimination (GE) circuit

is used to reduce glitches in the PD.

2 System architecture

The architecture of the proposed DLL-based clock genera-

tor is shown in Fig. 1. It can be divided into a core DLL

and an output pulse generator. The proposed core DLL

consists of an MPD, a GE circuit, an MCP, and a voltage-

controlled delay line (VCDL). The output pulse generator

consists of a phase interpolator and a phase combiner. The

proposed topology is based on two tuning loops: a ﬁne-tun-

ing loop and a coarse-tuning loop. The coarse-tuning loop

is composed of a coarse MPD and the large charging/dis-

charging current path of the MCP. The ﬁne-tuning loop is

composed of a PD and the minimize charging/discharging

current path of the MCP. The coarse-tuning loop is used to

Abstract This paper presents a fast-lock and low-power

delay-locked loop (DLL) circuit applied for DDR4. The

proposed modiﬁed phase detector and modiﬁed charge

pump can reduce locking time as well as static phase error.

The glitch elimination circuit reduces glitches in the PD for

reducing the glitch power. The phase interpolator and phase

combiner circuit are used to generate four output frequen-

cies: 0.2, 0.4, 0.8, and 1.6 GHz. The design is fabricated

through a 0.18-μm standard CMOS process with a supply

voltage of 1.8 V. The simulation results indicate that the

lock time is less than 20 cycles and the power consumption

of the DLL is 15.14 mW at 1.6 GHz. The active die area of

the proposed DLL-based clock generator is 0.51 mm2.

* Wei-Bin Yang

robin@mail.tku.edu.tw

Yu-Lung Lo

yllo@nknu.edu.tw

Han-Hsien Wang

tkus80212000@gmail.com

Cing-Huan Chen

w1993020743@gmail.com

Zi-Ang Huang

vincent811211@gmail.com

1 Department of Electrical Engineering, National Kaohsiung

Normal University, No. 62, Shenzhong Rd., Yanchao Dist.,

Kaohsiung City 82444, Taiwan (ROC)

2 Department of Electrical and Computer Engineering,

Tamkang University, No. 151, Yingzhuan Rd., Tamsui Dist.,

New Taipei City 23517, Taiwan (ROC)

Content courtesy of Springer Nature, terms of use apply. Rights reserved.

ResearchGate has not been able to resolve any citations for this publication.

A multiple frequency clock generator using wide operation frequency range phase interpolator

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This paper presents a multiple frequency clock generator that is composed of the wide operation frequency range phase interpolator and the phase combiner. The wide operation frequency range phase interpolator is developed using a delay-time-adjustment phase interpolator (DTAPI) circuit with various oscillation frequencies for different clock domain applications. The phase combiner generates multiple clock frequencies through various phase combination inputs generated by the preceding proposed phase interpolators. The varying output transition delay time of the proposed DTAPI is the result of the various oscillation frequencies of the voltage-controlled oscillator. The test chip was fabricated in a 0.18@mm CMOS process with a 1.8V supply voltage. The measured phase noise and power dissipation are -87.28dBc/Hz at 1MHz offset frequency from 88.8MHz and 1.32mW, -77.47dBc/Hz and 2.06mW from 797.8MHz, respectively. The duty cycle error rate of the output clock frequency is less than 1.5%.

A low jitter delay-locked-loop applied for DDR4

Conference Paper

Apr 2013

This work is the demand for a stable and low-jitter synchronous circuit on intra-chip. The operation frequencies of electronic products constantly increase along with the de-velopment and breakthrough of the CMOS process technology. The complexity of design and frequency of clock in memory has also been rapidly increasing. Thus, the reliability of synchronous circuits becomes more and more essential. Dynamic Random Access Memory (DRAM) has progressed to DDR4, reaches data rate 1.6 Gbps - 3.2 Gbps. The stability of clock becomes an essential part of design. This work presents a technique that includes a current-matching charge pump and an on-chip supply regulator in the delay-locked loop (DLL). The design is implemented by TSMC CMOS 1P/9M 90 nm technology with a nominal supply voltage 1.2 V and I/O supply voltage 2.5 V. The input frequency is at 1.6 GHz. Peak to peak jitter is 12.33 ps and RMS jitter is 1.66 ps. The power dissipation of DLL is 15.6 mW and chip area is 0.047 mm2.

A low jitter 110MHz 16-phase delay locked loop based on a simple and sensitive phase detector

Conference Paper

May 2013

A 16-phases low jitter delay locked loop, DLL, based on a simple phase detector is proposed in 0.35μm CMOS process. Moreover, a sensitive phase detector is introduced which detects small phase differences of input and generated clock signals. High sensitivity, besides the simplicity reduces the dead zone of the phase detector and yields a better clock jitter, consequently. A new strategy of common mode level setting is proposed for differential delay elements which no longer introduce extra parasitics on output nodes. Also, the input differential clock is carefully transferred inside the chip to considerably reduce the noise effect of power supply. Post-Layout simulation results confirm the RMS jitter of about 6.7ps at 20MHz and 2ps at 100MHz input clock frequency when the 3.3v power supply is subject to 75mv peak-to-peak noise. Total power consumption reaches from 7.5mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz.

A low jitter 110MHz 16-phase delay locked loop based on a simple and sensitive phase detector

Conference Paper

May 2013

A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator

Article

Sep 2012

A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems. The proposed DLL has a faster lock speed with the same loop dynamics compared to the conventional DLL based on a single-edge triggered phase detector (SET-PD). The proposed DET-PD solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. In addition, the proposed duty cycle difference compensation circuit (DDC) prevents the increase in the phase offset when the two inputs to the DET-PD have different duty cycle. It also controls the DLL bandwidth to maintain the DLL jitter by controlling the negative edge delay difference tracking. Finally, the proposed duty cycle keeper (DCK) enlarges the duty cycle keeping range of the DLL output. The proposed DLL is fabricated using 0.18-μm process technology. It has an area of 0.035 mm2 and a power consumption of 19 mW at 800 MHz operation. Its lock speed is over 1.9 times faster than that of the DLL based on the SET-PD without degrading the jitter.

A Multi-Band Fast-Locking Delay-Locked Loop With Jitter-Bounded Feature

Article

Feb 2011
IEEE T ULTRASON FERR

In this paper, a fast-locking delay-locked loop (DLL) with jitter-bounded feature is presented. In the proposed fast-locking mechanism, a frequency estimator and a programmable voltage circuit are developed to rapidly switch the control node of voltage-controlled delay line to a voltage level near the final required value. After that, the DLL output will be quickly locked by the following charge pumping on the loop filter. In the jitter-bounded approach, two phase-frequency detectors and a tunable delay are employed to hold the output clock jitter between two reference inputs after the DLL is locked. Furthermore, to enhance the flexibility of the presented DLL, a frequency multiplier with fewer active devices is also developed to provide high-frequency clock output for wideband applications. The presented DLL is implemented in a 0.18-μm 1P6M CMOS technology. The active area without contact pads is 0.34 × 0.41 mm<sup>2</sup>. A minimum lock time of six clock cycles is measured from no reference input to locked state. The output frequency ranges of the DLL and the frequency multiplier can be measured from 200 to 400 MHz and from 1 to 2 GHz, respectively. The power dissipation of the presented DLL is 31.5 mW at a 1.8 V supply voltage.

A high-speed and wide detectable frequency range Phase Detector for DLLs

Conference Paper

Dec 2009

A very simple, low power, wide range and high accuracy Phase Detector (PD) is presented solving many problems of the conventional circuits. SPICE simulation results show that the immune frequency range of operation is 1MHz to 2GHz. The dead zone of the presented open loop PD is zero, makes it the best choice to be used in high speed DLLs. This circuit is tested in 0.35um CMOS technology.

A new multiple frequency out of DLL with Glitch Elimination and Phase Interpolator for DDR4

Wb Yang
Ch Wang
Kh Hsu
Hh Wang
Yy Lin

A fast-lock and low-power DLL-based clock generator applied for DDR4

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