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A Monolithic 16-Channel Analog Array Normalizer
Abstract and Figures
A monolithic circuit has been developed which accepts 16 parallel voltage inputs having values which may be as small as 15 mV or as large as 15 V, and generates 16 concurrent output voltages which are in the same ratios as the inputs with a peak amplitude controllable by the user. Response time is in the region of 1 /spl mu/s at full scale. The chip includes provisions for expansion to any number of channels. Operation is from supplies of /spl plusmn/3 to 15 V at a quiescent current of 125 /spl mu/A. Details of the design principles and peripheral circuitry are provided. Measurements of static accuracy and dynamic performance demonstrate that this approach may often simplify preprocessing of signal arrays in pattern-recognition applications.
... This issue is generally resolved by scaling up the terms of the discrete probability distributions from time to time to values acceptable in the data representation. [131]. works, the fading problem of the probability values is even more pronounced. ...
... So the probability mass functions represented by current vectors have to be scaled up electronically. In [131] Gilbert has presented an array-normalizer circuit that implements exactly the needed scaling function. The circuit of Fig. 4.14 can easily be explained by using the translinear principle [107]. ...
... Comparable attempts to force circuits, originally designed for Exchanging MOS devices for BJTs can be found in other circuits bipolar technology, to operate in the quadratic (strong inversion) region of plain CMOS technology have been made. For example, Gilbert's array-normalizing circuit [131] has been used in a fuzzy logic controller to scale current vectors [153]. Although the circuit does not anymore scale the quantities correctly, the order of precedence is preserved in the monotonically increasing transfer function, which is sufficient for building fuzzy logic circuits. ...
Thesis (doctoral)--Swiss Federal Institute of Technology Zurich, 2000.
... Still at the device level, standard MOS processes provide excellent photosensors, which can be arranged in large arrays for on-chip image acquisition [11]. Translinear circuits are most important to implement very dense local or collective operators [12,13,14,15,16,17]. Their realization with MOS transistors in weak inversion faces some limitations, but it also offers additional advantages with respect to bipolar circuits. ...
... The same is true for diffusion (pseudo-)resistive networks [2,31,32,33]. Some tasks of collective processing like normalization [15], search for a maximum value (winner-take-all) [34] or collective evaluation of the motion of a texture surface [35] require communication between all the cells via just one or two common wires. When arbitrary links are needed, data can be multiplexed on a bus, thereby taking advantage of the wide bandwidth available in electronics in comparison to biology. ...
Contrary to the generally accepted idea that all future processing should be carried out digitally, analog solutions are expected to be more efficient, with respect to power consumption and chip area, for perceptive processing by collective computation in massively parallel architectures. The full potential of analog VLSI for collective computation is still under exploration, but its advantage for low-power applications, particularly in vision, is already demonstrated by several working chips. Some of them are parts of successful industrial products.
... Boussaid approximated this set by a rectangle and labeled as skin any chromaticity whose spatial coordinates were inside this rectangle. The work assumes a color imager with passive pixel sensors (PPS) directly delivering the photo-generated current to be processed through a Gilbert normalizer [33]. The skin classification is implemented with four current comparators tuned on the coordinates of the skin locus rectangle. ...
Human skin classification is an essential task for several machine vision applications such as human-machine interfaces, people/object tracking, and classification. In this paper, we describe a hybrid CMOS/memristor vision sensor architecture embedding skin detection over a wide dynamic range. In-sensor RGB to $rg$ r g -chromaticity color-space conversion is executed on-the-fly through a pixel-level automatic exposure time control. Each pixel of the array delivers two pre-filtered analog signals, the $r$ r and $g$ g values, suitable for being efficiently classified as skin or non-skin through an analog memristive neural network (NN), without the need for any further signal processing. Moreover, we study the NN performance and theorize how it should be added in the hardware. The skin classifier is organized in an array of column-level memristor-based NN to exploit the nano-scale device characteristics and non-volatile analog memory capabilities, making the proposed sensor architecture highly flexible, customizable for various use-case scenarios, and low-power. The output is a skin bitmap that is robust against variations of the illuminant color and intensity.
... In the last three decades, many researchers focused on the development of a hardware implementation for fuzzy logic systems and neural networks. An analogue circuit used to implement each part of fuzzy system including: Fuzzification, Fuzzy Inference and Defuzzification based on different circuit techniques, such as CMOS, BiCMOS, bipolar and PLA Catania et al. (1994;Gilbert (1984;Ishizuka et al. (1992;Tasaka (1989;Yamakawa (1992).The structure of fuzzy system is complex, so that the analogue circuit has to be very complicated to implement the analogue fuzzy system. Therefore, most of researchers proposed digital circuits to implement the fuzzy logic system using either Application Specific Hardware Modules (ASICs) or general purpose software microprocessor or microcontroller. ...
Focusing on designing a robust controller for active suspension systems is very important for
guaranteeing the riding comfort for the passengers and road handling quality for the vehicle.
In this thesis, the mathematical model of full vehicle nonlinear active suspension systems with
hydraulic actuators is derived to take into account the all motion of the vehicle and
nonlinearity behaviours of the active suspension system and hydraulic actuators.
Four robust control types are designed and comparisons among the responses of the controller
under different types of disturbances are carried out to select the best controller from them.
The MATLAB SIMULINK toolboxes are used to simulate the control system with the
controlled model and to display the results of the controlled model under different types of the
disturbances. The results show that the neurofuzzy controller is more robust and effective than
the other controller types.
The hardware implementation of the Neurofuzzy controller using FPGA board is designed.
The Xilinx ISE program are used as the environment to type the VHDL codes that describe
the operation of the neurofuzzy controller and to generate the configuration file that is used to
program the FPGA’s ICs. ModelSim program is used to simulate the operation of the VHDL
codes and obtained the output data of the FPGA board. To make sure that the FPGA board
works like the simulated neurofuzzy controller, MATLAB programme is used to compare
between the set of the data that are obtained from the ModelSim program and the set of the
data that are obtained from the MATLAB SIMULINK model. The results show that the
FPGA board is effective to be used as a neurofuzzy controller for full vehicle nonlinear active
suspension systems.
The active suspension system has great performance for vibration isolation, but the main
drawback of the active suspension is high energy consumption. Therefore, to use this
vii
suspension system in our model, this drawback should be solved. An electromagnetic actuator
is used to convert the vibration energy that arises from the rough road to useful electrical
energy to reduce the energy consumption by the active suspension systems. The results show
that the electromagnetic device does act as a power generator. i.e., the vibration energy
excited by the rough road surface has been converted to useful electrical energy supply for the
actuators. Furthermore, when the nonlinear damper models are replaced by the
electromagnetic actuators, riding comfort and the road handling quality have been improved.
As a result, two targets have been met by using hydraulic actuators with electromagnetic
suspension systems: increasing fuel economy and improving the vehicle performance
... This problem can be addressed in various complementary ways. Some collective operations can be carried out by distributed cells which communicate through a single (or just very few) wire, as exemplified by the normalizer [17] and the winner-take-all [18] circuits shown in Fig.4. Communication to the next neighbors only is another strategy used for example in cellular neural networks (CNN) [19,20]. ...
Biology can be a rich source of inspiration for engineers. In particular, designers of VLSI processing circuits and systems can draw inspiration from several aspects of the brain. Inspired from evolution, the opportunistic exploitation of all the properties of the technology provides very efficient analog circuit techniques. The collective computation carried out by the brain in its massively parallel architecture can be emulated on silicon. Strategies like learning and adaptation are very beneficial to VLSI processing. The same is true for the unusual ways used by the brain to represent signals and information. Four industrial chips developed with this bio-inspired approach are described, as well as several experimental circuits that demonstrate its potential for future products.
... In the last two decades, many researchers focused on the development of a hardware implementation for both fuzzy logic controller and neural controller. [1], [2] and [3] used an analogue circuit to implement each part of fuzzy system (including: Fuzzification, Fuzzy Inference and Defuzzification). The structure of fuzzy system is complex, so that the analogue circuit has to be very complicated to implement the logic system. ...
... The calculation of this involves a division operation. This operation can be obtained in electronics using analog divider as was made in [13]. However this technique has a limit in the bandwidth, requires of a calibration method and it is any susceptible to noise. ...
In this work, the design and analysis of a Fuzzy Logic Controller (FLC) is presented. This controller is totally based on analog electronics, allowing a substantial increase of its response speed. The design for each element is made with a future VLSI implementation in mind. The architecture of the controller is thought to be either static and/or dynamic, providing in this way a higher versatility. All the circuits exclude negative feedback, however, they show good stability in presence of temperature and polarization disturbances, among others. The work is supported by the analysis of each circuit and the results obtained during experimentation are presented.
... The full wave rectified responses from the HR detector are the inputs for the FD cell based model. The pooling of the positive and the negative parts is done separately by the Gilbert normalizer circuit (Gilbert, 1984). An n-channel normalizer is shown in Figure 3.8. ...
Acknowledgments I am greatly thankful to my parents and sisters for their love and continued support throughout my life. I am thankful to my advisor Chuck Higgins for his guidance, encouragement, and inspiration through- out this work. I am thankful to Prof. Rozenblit and Prof. Palusinski for serving on my thesis defense committee. I thank Ania Mitros (Caltech) for her help during the design and implementation of the spiking neuron chip. I would also like to thank the Doings group of neurobiology for the involving discussions that were highly interesting and informative. I am thankful to the Higgins Lab for the late-night parleys, and a pleasant and friendly atmosphere courtesy Erhan, Robert, Jad, and Anusha. And my special thanks to Mansi for being there and keeping me going. 3 Table of Contents List of Figures,................ ................ .......... 5 Abstract,................ ................ .............. 7
... This problem can be addressed in various complementary ways. Some collective operations can be carried out by distributed cells which communicate through a single (or just very few) wire, as exemplified by the normalizer [17] and the winner-take-all [18] circuits shown in Fig.4. Communication to the next neighbors only is another strategy used for example in cellular neural networks (CNN) [19,20]. ...
Biology can be a rich source of inspiration for engineers. In particular, designers of VLSI processing circuits and systems can draw inspiration from several aspects of the brain. Inspired from evolution, the opportunistic exploitation of all the properties of the technology provides very efficient analog circuit techniques. The collective computation carried out by the brain in its massively parallel architecture can be emulated on silicon. Strategies like learning and adaptation are very beneficial to VLSI processing. The same is true for the unusual ways used by the brain to represent signals and information. Four industrial chips developed with this bio-inspired approach are described, as well as several experimental circuits that demonstrate its potential for future products.
... The photogenerated current enters the pixel's share T N 1 − T N 2 − T N 3 of a chip-wide normalizer integrated using MOS transistors in weak inversion. Although a " real " translinear network should be made using bipolar or compatible lateral bipolar transistors [12,13] the MOS solution was chosen for its smaller area even with rather large transistors in the translinear loop and because exact normalization does not seem critical in this application. The normalization current is directly related to the network's total activity and can be used to tune bus occupation to the best value according to equation (2). ...
This paper reports on the main properties and some applications of a pulsed communication system specifically developed for
the service of multichip perception schemes realized in analog VLSI. The project started with the goal to obtain biological-like
connectivity among functional subsystems capable of processing sensory data in a collective fashion through several hierarchical
layers and through convergence, divergence and fusion of data from different origins. As a consequence of the thin sheet organization
of their biological counterparts, the realized subsystems consist almost invariably of several one- or two-dimensional arrays
of cells. The output of every cell, its activity, is relevant to further processing and should be available for communication to the next layer.
... : : : : : : : : : : : : : : : : : : : : : : : : : : : 58 3-15 Input structures, clocking waveforms, surface potentials, and signal charge, for (a) the standard ll-and-spill approach and (b) for the split-gate ll-and-spill technique. : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 59 3-16 Potentials and charge locations during shifting and sensing for (a) the oating di usion output structure and (b) the oating gate output structure. : : : : : : : 60 3-17 Required clock w aveforms for output using (a) the oating di usion output structure and (b) the oating gate output structure. ...
Attention has recently been given to the design of custom analog
VLSI chips for early vision-processing problems. The key features of
these tasks are simple operations performed in parallel at each pixel in
an image, typically resulting in a description of the scene useful for
higher-level vision. This type of processing is well suited to
implementation in analog VLSI, yielding compact high-speed low-power
solutions. The chip described computes the focus of expansion (FOE). The
FOE is the image point that the camera is moving toward. Image features
appear to expand outward from the FOE and knowledge of its location
provides the direction of camera motion
... Very fast analog processing of a large number of signals is made possible by circuits capable of truly parallel collective computation. A simple example is given by the normalization circuit shown in Fig.19 [27]. ...
Analog VLSI signal processing is most effective when precision is not required, and is therefore an ideal solution for the implementation of perception systems. The possibility to choose the physical variable that represents each signal allows all the features of the transistor to be exploited opportunistically to implement very dense time- and amplitude-continuous processing cells. This paper describes a simple model that captures all the essential features of the transistor. This symmetrical model also supports the concept of pseudoconductance which facilitates the implementation of linear networks of transistors. Basic combinations of transistors in the current mirror, the differential pair, and the translinear loop are revisited as support material for the description of a variety of building blocks. These examples illustrate the rich catalogue of linear and nonlinear operators that are available for local and collective analog processing. The difficult problem of analog storage is addressed briefly, as well as various means for implementing the necessary intrachip and interchip communication.
... The relatively slow analog dividers or instrumentation amplifiers 30 used will again significantly reduce the bandwidth. In our setup, we use a translinear normalizer 31 [which is created when transistors Q11 and Q12 are added as shown in the dotted box of Fig. 1(c)]. It is noteworthy that this normalization method is very fast, limited only by the bandwidth of the transistors. ...
We demonstrate a novel electronic readout for quadrant photodiode based optical beam deflection setups. In our readout, the signals used to calculate the deflections remain as currents, instead of undergoing an immediate conversion to voltages. Bipolar current mirrors are used to perform all mathematical operations at the transistor level, including the signal normalizing division. This method has numerous advantages, leading to significantly simpler designs that avoid large voltage swings and parasitic capacitances. The bandwidth of our readout is solely limited by the capacitance of the quadrant photodiode junctions, making the effective bandwidth a function of the intensity of photocurrents and thus the applied power of the beam deflection laser. Using commercially available components and laser intensities of 1-4 mW we achieved a 3 dB bandwidth of 20 MHz with deflection sensitivities of up to 0.5-1 V/nm and deflection noise levels below 4.5 fm/Hz. Atomic resolution imaging of muscovite mica using FM-AFM in water demonstrates the sensitivity of this novel readout.
... In the last two decades, many researchers focused on the development of a hardware implementation for both fuzzy logic controller and neural controller. [1], [2] and [3] used an analogue circuit to implement each part of fuzzy system (including: Fuzzification, Fuzzy Inference and Defuzzification). The structure of fuzzy system is complex, so that the analogue circuit has to be very complicated to implement the logic system. ...
A Field Programmable Gate Array (FPGA) is proposed to build an Adaptive Neuro Fuzzy Inference System(ANFIS) for controlling a full vehicle nonlinear active suspension system. A Very High speed integratedcircuit Hardware Description Language (VHDL) has been used to implement the proposed controller. Anoptimal Fraction Order PIlDμ (FOPID) controller is designed for a full vehicle nonlinear activesuspension system. Evolutionary Algorithm (EA) has been applied to modify the five parameters of theFOPID controller (i.e. proportional constant Kp, integral constant Ki, derivative constant Kd, integralorder l and derivative order μ). The data obtained from the FOPID controller are used as a reference todesign the ANFIS model as a controller for the controlled system. A hybrid approach is introduced to trainthe ANFIS. A Matlab Program has been used to design and simulate the proposed controller. The ANFIScontrol parameters obtained from the Matlab program are used to write the VHDL codes. Hardwareimplementation of the FPGA is dependent on the configuration file obtained from the VHDL program. Theexperimental results have proved the efficiency and robustness of the hardware implementation for theproposed controller. It provides a novel technique to be used to design NF controller for full vehiclenonlinear active suspension systems with hydraulic actuators.
... So, this rectification can be viewed as a routing mechanism for the current to its corresponding normalization circuit. A Gilbert normalizer circuit [12] is used to implement both positive and negative normalization. Each pixel acts as one of the n channels of the normalizer, and an external normalization circuit has the bias controls for the normalizer. ...
Tracking of a target in a cluttered environment requires extensive computational architecture. However, even a small housefly is adept at pursuing its prey. Biomimetic algorithms suggest a way of looking at this problem. In the lobula plate of a fly's brain, a neural circuit is hypothesized based on a tangential cell called the figure detection (FD) cell. The proposed small target fixation algorithm based on electrophysiological recordings does not take into account the translation of the pursuer during pursuit. We have modified the biological algorithm to include this aspect of tracking. In this paper, we present the elaborated biological algorithm for small target tracking, and an analog VLSI implementation of this algorithm.
Various centrality measures have been proposed to identify the influence of each node in a complex network. Among the most popular ranking metrics, spectral measures stand out from the crowd. They rely on the computation of the dominant eigenvector of suitable matrices related to the graph: EigenCentrality, PageRank, Hyperlink Induced Topic Search (HITS) and Stochastic Approach for Link-Structure Analysis (SALSA). The simplest algorithm used to solve this linear algebra computation is the Power Method. It consists of multiple Matrix-Vector Multiplications (MVMs) and a normalization step to avoid divergent behaviours. In this work, we present an analog circuit used to accelerate the Power Iteration algorithm including current-mode termination for the memristor crossbars and a normalization circuit. The normalization step together with the feedback loop of the complete circuit ensure stability and convergence of the dominant eigenvector. We implement a transistor level peripheral circuitry around the memristor crossbar and take non-idealities such as wire parasitics, source driver resistance and finite memristor precision into account. We compute the different spectral centralities to demonstrate the performance of the system. We compare our results to the ones coming from the conventional digital computers and observe significant energy savings while maintaining a competitive accuracy.
This brief presents a novel low-power analog Euclidian vector normalizer for analog signal processing in vector forms, such as the preprocessing of sensor array signals. Instead of using multiple stages of translinear circuits to synthesize the Euclidian norm with square root, squared sum, and division functions, this circuit performs concurrent Euclidian vector normalization on input signals with a feedback control loop to achieve a compact area and low power consumption. A simple two-step calibration is also provided to overcome device mismatches. This 6-channel normalizer is part of an analog gas sensing front end and was implemented in a 65-nm low-power CMOS technology with an area of 0.053 mm
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. It consumes a maximum current of 2.08 μA from 0.6/0.65-V supplies with a response time of 6.5 μs, thus achieving a low energy per operation of 1.39 pJ/channel.
In biological vision systems, the term attention describes the way that information is prioritized and selected [23]. Selective attention is necessary in visual processing in order to handle the overwhelming amount of sensory information that is available. Visual systems, such as those found in primates, have a hybrid architecture in which low-level processing is performed in parallel across the entire visual field, and high-level processing is only performed on a selected subregion of the visual field [2]. Low-level tasks that are computed entirely in parallel are described as preattentive. Attentive processing uses this preattentive information to select a smaller region of interest for subsequent high-level processing. The duality of parallel computation and serial selections of regions of interest exemplifies the trade-off between speed and processing sophistication that results from the utilization of a limited amount of processing circuitry. If the attentional selection were not performed, an overwhelming amount of neural circuitry would be required in order to perform the high-level processing in parallel over the entire visual field [1].
Resistive networks for computer vision can be used in object-related applications. In addition to the basic photoreceptor-resistor network, additional circuitry is required for implementing some specific functions.
The translinear principle has become quite familiar to IC designers during the past twenty years. Originally conceived within the narrow framework of bipolar, wideband, fixed- and variable-gain current-mode amplifiers employing closed loops of junctions [1,2]—now called TL cells, in which input and output signals and biases are all in pure current form—the scope of the concept has gradually broadened to include any circuit in which the essential function depends directly on a precise exponential relationship existing between the current at one terminal of a suitably-biased three-terminal active device and the voltage applied across the remaining two terminals. A trans linear cell not including any directly closed sloops has more recently [3] been called a translinear network (TN).
The potentialities of CMOS analog VLSI for the implementation of
neural systems are demonstrated. It is shown how the various modes of
operation of the transistor can be exploited to build very efficient
neurons on a very small area with very low power consumption. The
connectivity problem can be alleviated by selecting appropriate
architectures. Various methods for implementing analog synaptic memories
are discussed, and examples of working chips are given
In this paper we present analog very large-scale integrated
(VLSI) circuits that perform the selection process for attentive
visual processing. These circuits use excitatory feedback in
a winner-take-all computation to produce a hysteresis in the
selection from one location to the next. We present several alternative
forms of excitation that can be used to enhance surrounding regions
of the presently attended location. Each form of excitation is
discussed and experimental results from a one-dimensional array
are presented. We also demonstrate the performance of these circuits
within a system that receives optical inputs and outputs a single
voltage that encodes the position of attention. The system demonstrates
the potential use of these excitatory feedback circuits for electronic
tracking of a stimulus within a noisy environment.
In this paper we consider the use of static analog VLSI circuits for iteratively maximizing cost functions that admit a fixed point recursion. We show through circuit simulation that certain classes of fixed point equations can be solved iteratively via the settling to steady state equilibrium of properly designed static-feedback CMOS circuits biased in the subthreshold region of operation. To demonstrate the power of this approach, we design a family of circuits to compute the right principal singular vector of arbitrarily sized positive real matrices by casting the singular vector extraction problem into a fixed point iterative map. We also illustrate the methodology more simply with a square root solver that uses the Babylonian fixed point equation. All circuits are current-mode translinear circuits with no extrinsic capacitors. This permits fast, low-power computation since the principal delay component is the settling time of the static circuits, and the few transistors required are biased in weak inversion.
We present a new approach to the engineering of collective analog computing systems that emphasizes the role of currents as an appropriate signal representation and the need for low-power dissipation and simplicity in the basic functional circuits. The design methodology and implementation style that we describe are inspired by the functional and organizational principles of neuronal circuits in living systems. We have implemented synthetic neurons and synapses in analog CMOS VLSI that are suitable for building associative memories and self-organizing feature maps.
In this paper, a current-mode VLSI architecture enabling on read-out skin detection without the need for any on-chip memory elements is proposed. An important feature of the proposed architecture is that it removes the need for demosaicing. Color separation is achieved using the strong wavelength dependence of the absorption coefficient in silicon. This wavelength dependence causes a very shallow absorption of blue light and enables red light to penetrate deeply in silicon. A triple-well process, allowing a P-well to be placed inside an N-well, is chosen to fabricate three vertically integrated photodiodes acting as the RGB color detector for each pixel. Pixels of an input RGB image are classified as skin or non-skin pixels using a statistical skin color model, chosen to offer an acceptable trade-off between skin detection performance and implementation complexity. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch and also in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing external control of all classifier parameters to compensate for mismatch and changing lighting conditions.
This paper presents a variety of applications of an FPAA based on a regular pattern of signal-processing cells and primarily local signal interconnections. Despite the limitations introduced by local interconnections, the presented architecture accommodates a wide variety of linear and nonlinear circuits found in many signal processing systems. Thus it effectively proves that it is possible to improve the performance of an FPAA by means of constraining the interconnection pattern, without significantly limiting the class of circuits it can implement.
In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI translinear system with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.
We have implemented a hardware model of selective visual attention within the neuromorphic, analog VLSI paradigm. The system includes a highly-parallel winner-take-all selection with excitatory and inhibitory influences. The selection specifies positions of attention based on an array of intensity levels, which comprise a primitive saliency map. The excitation and inhibition control the strategy for shifts of attention from one position to the next. The combination of these fundamental building blocks demonstrates emergent properties that can be observed in real time due to the parallel hardware implementation. The system behaves as a smart-scanning sensor array. The basic characteristics of the scanning pattern are controlled by setting a number of analog parameters. In this paper we describe the system, focusing on the role that inhibition plays in the redirection of attention. We show experimental results from one-dimensional implementations of the hardware model. Analysis that explains the expected behavior for the two-element mode of operation is presented. The theoretical predictions are compared to experimental results.
The concept of a translinear circuit is now widely appreciated and applied. This paper traces the history of the concept, delineates the original meaning of the term, explains the basic principles of this class of circuit and discusses recent, more general, interpretations of the term. It is recommended that the word translinear, used without further qualification, should be reserved exclusively for those cells invoking exponential device behaviour, which applies to all bipolar transistors, including heterojunction types, and to MOS transistors operated in the subthreshold, or weak inversion, domain, but does not apply to normal MOS operation in strong inversion. It is proposed that the theory and practice related to such quadratic operation of MOS devices, where the transconductance is presumed to be linear with gate-source voltage, should be termed voltage-translinear, or VTL.
An electromechanical system that follows a bright visual stimulus
is presented. At the core of this system is an analog VLSI chip that
incorporates photosensitive elements and computational circuitry. The
circuitry converts a focused 1D visual imager into a bidirectional motor
signal that is encoded as a pair of pulse trains. These outputs are
amplified and are used to drive a mechanical motor system that `closes
the loop' around the circuitry by moving the chip to follow the
stimulus. The circuitry has been incorporated into a wheeled vehicle
that follows a light source
A current-mode VLSI architecture enabling real-time skin detection processing is presented. Based on a statistical skin color model, it achieves pixel classification on readout in the normalized RGB color space. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch associated errors and in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing for the external control of all classifier parameters to compensate for mismatch and changing lighting conditions.
An analog VLSI processor for motion computation is presented. It
is based on the Hassenstein-Reichardt-Poggio model for information
processing in the visual system of the fly. The authors show how neural
network models can be mapped on silicon integrated circuits for
performing tasks that can not be handled efficiently by digital
computing machinery. The design is based on current-mode subthreshold
MOS circuits using device-level design and exploiting the translinear
property of the MOS transistor. Experimental results from fabricated
chips are presented
The author considers the analog interface functions required in
the periphery of information systems. Circuit techniques are discussed
with are compatible with monolithic CMOS, bipolar, and BICMOS
technologies. Applications are considered in the context of the
following functions: input amplifier, filters, signal conditioning,
voltage-current convertors, and output (power) amplifier
A scanning laser acoustic microscope (SLAM) is described. The SLAM achieves a resolution of about 10 μm and is capable of imaging subsurface features at depths up to several millimeters, using appropriate reconstruction algorithms. The various components of the apparatus, both acousto‐optical and electronic, are described. A major feature of the SLAM is a digital data‐acquisition system capable of storing and processing the complex acoustic field in images with 256×256‐pixel resolution. An array processor enables most floating‐point operations to be completed in a few seconds. Examples of acoustic images obtained from a test sample are presented.
Subthreshold analog circuits for MOS implementation of artificial neural networks are presented with on-chip learning capability. Each synapse circuits consist of a storage capacitor and 3 analog multiplier, i.e. one for signal feedforward, one for outer-product synaptic weight adjustments, and one for error backpropagation. While all the 3 multipliers are used for error backpropagation learning, only the first 2 multipliers are used for Hebbian learning. Each neuron circuits are composed of a sigmoid circuit and a sigmoid derivative circuit, which show near ideal sigmoid characteristics and provide external gain-control capability. All the circuits incorporate modular architecture, and are designed to increase the numbers of neurons and layers with multiple chips. Also, the subthreshold operation provides low power consumption and large scale implementation.
The main objective of designed the controller for a vehicle suspension system is to reduce the discomfort sensed by passengers which arises from road roughness and to increase the ride handling associated with the pitching and rolling movements. This necessitates a very fast and accurate controller to meet as much control objectives, as possible. Therefore, this paper deals with an artificial intelligence Neuro-Fuzzy (NF) technique to design a robust controller to meet the control objectives. The advantage of this controller is that it can handle the nonlinearities faster than other conventional controllers. The approach of the proposed controller is to minimize the vibrations on each corner of vehicle by supplying control forces to suspension system when travelling on rough road. The other purpose for using the NF controller for vehicle model is to reduce the body inclinations that are made during intensive manoeuvres including braking and cornering. A full vehicle nonlinear active suspension system is introduced and tested. The robustness of the proposed controller is being assessed by comparing with an optimal Fractional Order PI<sup>λ</sup>D<sup>μ</sup> (FOPID) controller. The results show that the intelligent NF controller has improved the dynamic response measured by decreasing the cost function.
We consider the problem of automatic object recognition by small, light-weight, low power, hardware systems. We abstract from biological function and organization and propose hardware architectures and a design methodology to engineer such hardware. Robust, miniature, and energetically efficient VLSI systems for AOR can ultimately be achieved by following a path which optimizes the design at and between all levels of system integration, i.e., from devices and circuit techniques all the way to algorithms and architectural level considerations. By way of example, we discuss two experimental systems for image acquisition and preprocessing fabricated in standard CMOS processes. The first one is a large scale analog system, a contrast sensitive silicon retina, with over 590, 000 transistors operating in subthreshold CMOS. The second system is a mixed analog-digital system for image acquisition and tracking compensation that incorporates a contrast sensitive silicon retina in the image sensing area.
A two-dimensional object-based analog VLSI model of selective attentional processing has been implemented using a standard 1.2 μm CMOS process. This chip extends previous work modeling object-based selection and scanning by incorporating the circuity and architectural changes necessary for two-dimensional focal plane processing. To balance the need for closely spaced large photodetectors with the space requirements of complex in-pixel processing, the chip implements a multiresolution architecture. The system has he ability to group pixels into objects; this grouping is dynamic, driven solely by the segmentation criterion at the input. In the demonstration system, image intensity has been chosen for the input saliency map and the segmentation is based on spatial lowpass filtering followed by an intensity threshold. We present experimental results
We present an experimental analog VLSI focal plane processor for the phototransduction, local gain control and edge enhancement of natural images. The single chip system incorporates 590,000 transistors in 48,000 pixels, and it has been fabricated on a 9.5×9.3 mm die in a 1.2 μm n-well double metal, double poly, digital oriented CMOS technology. The organization of the system abstracts from the structure and function of the vertebrate distal retina. The adopted design style, current-mode subthreshold CMOS using circuits of minimal complexity offers the possibility of ultra low power dissipation and area efficiency, commensurate with VLSI integration
A collective computational architecture and real-time, analog VLSI implementation for localizing and tracking a stimulus in a sensory image are developed. This architecture is presented as a layered two-dimensional computationalframework which generates signals to autonomously control a mechanical system that tracks the stimulus. The framework is a schematic representation of the described computation. The input to the framework is a spatially encoded sensory image and the outputs are a set of pulse trains that are used to control a robotic motor system. The analog VLSI implementation is based upon circuits that provide a real-time, small-size, low-power implementation technology for this and other sensorimotor applications. The circuits perform the desired computation entirely in parallel on a single VLSI chip. The layer-to-layer communications occur via arrays of currents which are modified at each level in the framework and then communicated to the subsequent layer. The outputs generated by the circuit are a set of pulse-encoded signals sufficient to antagonistically control DC actuators. A system implementation and resulting data are also presented. The system combines a visual imaging array, computational circuitry, and a mechanical plant, which, through negative feedback, moves the imager to hold a stimulus (a bright spot on a darker background) stationary in the sensory field.
Cover title. "March 1995." Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995. Includes bibliographical references (p. 161-168). Sponsored in part by the National Science Foundation and the Advanced Research Projects Agency.
An analog current-mode circuit performs soft-max computation with gain-control capability; a theoretical analysis supports the design method and gives the expected error bound. Experimental results from post-layout simulations match theoretical predictions.
A skin detection technique suitable for on-chip integration into color CMOS imagers is proposed. The technique uses color information in the normalized rgb color space to discriminate between skin and non-skin color pixels. Its current-mode implementation achieves real-time skin detection. Furthermore, the pixel classification is performed on read-out, allowing high-speed processing without the need for any on-chip memory elements. Fully analog, the proposed VLSI architecture combines compactness, programmability and low power operation.
The theory and practice of log-domain filter design has reached
the point where it is possible to incorporate log-domain filter
structures into large current-mode VLSI systems. We report on interface
circuits used to implement a current-mode frontend filterbank and
feature extractor for acoustic pattern recognition. These circuits
maintain a log-domain structure, acting on the unexpanded filter output
to execute such functions as peak-to-peak voltage measurement, full-wave
rectification, smoothing, and normalization. A fabricated VLSI
sixteen-channel filterbank feature extractor exhibits 40 dB resolution
for short-term energy envelope measurements of class A log-domain
second-order bandpass filter outputs
We have implemented a CMOS focal-plane processing array that
performs a selection algorithm based on the intensity profile of the
input image. Objects within the image are segmented by normalization,
filtering, and thresholding. The selection processing circuits use
aggregate information from each object in order to select the most
important object within the visual field. All pixel processing is
implemented with analog subthreshold circuits. The system includes a
multiresolution array of pixels that comprise a 50×48 array of
photoreceptors and a 25×24 array of object-based selection
processing circuits. On-chip scanners are used to simultaneously display
the input and output arrays directly on a multisync monitor.
Position-encoding circuitry is also included on the chip in order to
output two analog values that indicate the selected position on the
array. The system was fabricated in a standard 1.2 μm digital CMOS
process. We present experimental results
Analog VLSI circuits that perform the selection process for
attentive sensory processing are presented. These circuits use
excitatory feedback in a winner-take-all computation to produce a
hysteresis in the selection from one location to the next. They also use
an inhibitory mechanism to disengage attention so that more than one
stimulus is attended, even when the inputs remain static. These circuits
have been implemented in analog VLSI chips that sense and process
optical input to select salient objects from the visual field. Data from
the fabricated chips are shown, demonstrating the operation of the
resulting system
A fully-parallel 16-channel analog array processor for concurrent signal normalization in pattern recognition applications will be described. Using a standard monolithic bipolar process the chip consumes 1mW, provides a 1MHz bandwidth and unlimited channel-expansion facilities.
An important and expanding branch of analogue circuits is the `translinear¿ group. Their primary function arises from the exploitation of the precise proportionality of transconductance to collector current in bipolar transistors so as to result in fundamentally exact, temperature-insensitive behaviour. The basic translinear principle is derived and several examples given.
Precision dc-coupled amplifiers having risetimes of less than a nanosecond have recently been fabricated using the monolithic planar process. The design is based on a simple technique that has a broad range of applications and is characterized by a stage-gain- bandwidth product essentially equal to that of the transistors, and a very linear transfer characteristic, free from temperature dependence.
An analog array processor Solid-State Circuit Conf
- B Gilbert
A new wideband amplifier principle~
- B Gilbert
B. Gilbert, "A new wideband amplifier principle~" IEEE J. Solid-State Circuits. vol. SC-3, p. 353. Dec. 1968.