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A Precise Four-Quadrant Multiplier with Subnanosecond Response
Abstract
This paper describes a technique for the design of two-signal four-quadrant multipliers, linear on both inputs and useful from dc to an upper frequency very close to the ft of the transistors comprising the circuit. The precision of the product is shown to be limited primarily by the matching of the transistors, particularly with reference to emitter-junction areas. Expressions are derived for the nonlineafities due to various causes. Copyright © 1968 by The Institute of Electrical and Electronics Engineers, Inc.
... The structure of a Gilbert cell mixer with the impe-dance matching circuit is demonstrated in Fig. 2 [11]. The Gilbert cell has the switch and transconductance stages. ...
... With the increase in the temperature level, the carriers mobility decreases, with which the tail current value comes down. Considering (11), it is expected that the IIP3 value will be reduced, as well. Nevertheless, the power consumption of the circuit increases from 6.64 mW to 11.08 mW due to the rise of the mixer current. ...
A Gilbert-cell mixer is designed for operation in cryogenic conditions (-196∘C) using UMC 180 nm CMOS technology. The operating frequency is determined as 5 GHz. The proposed mixer achieves an IIP3 of 12.8 dBm, a 1-dB compression of 2.19 dBm, and a conversion gain of around 4 dB at -196∘C. The design performance has been compared with the outcomes acquired at room temperature. It is verified that cryogenic conditions enable higher linearity and lower noise figure that elevates the mixer design performance.
... Due to the intended FMCW operation of the radar, the IF frequency can be sampled directly by an ADC and the impact of flicker noise on the systems signalto-noise ratio (SNR) is negligible. The chosen architecture shares similarities with the classic Gilbert-Cell [30] but at the RF input the differential pair is omitted due to the limited maximum available gain at the chosen operating frequency of the available HBTs. Only the switching quad that is needed for the frequency translation by applying a large LO signal at the bases is implemented and optimized here. ...
... The RMS error is 137 Hz for the 0.552 GHz/ms and 3.254 kHz for the 3.31-GHz/ms ramp. 30 μs, the frequency error is less than 0.5 kHz. The peak overshoot is 15 kHz. ...
The article presents a monostatic D-band frequency-modulated continuous-wave (FMCW) radar based on a fully integrated monostatic single-channel silicon-germanium (SiGe) transceiver (TRX) chip. The chip is fabricated in Infineon's bipolar-complementary metal-oxide-semiconductor (BiCMOS) production technology B11HFC which offers heterojunction bipolar transistors (HBTs) with an
$f_{{T}}$
/
$f_{{max}}$
of 250 GHz/370 GHz. The monolithic microwave integrated circuits (MMICs) output signal is coupled by a fully differential substrate integrated waveguide (SIW) based coupling network. The output power at the WR-6.5 antenna flange is more than -10 dBm over a bandwidth of 37.5 GHz. For a sweep within a single-loop phase-locked loop (PLL) circuit from 174.5 to 121.5 GHz, a spatial resolution of almost 3 mm with a metallic plate as the target is achieved. The radar provides a small form factor of 2 x 4 x 5 cm³ and low power consumption of 2.2 W at 5 V. Finally, the capabilities of the sensor for non-destructive testing (NDT) are demonstrated using a millimeter scanner. With radar imaging, it was possible to measure the orientation of the fiber layers up to a depth of 7.03 mm.
... Some designs also incorporate floating gate transistors in architectures following the mathematical approach of the translinear principle. Specifically, [26,69] modify the exponentiator; [26] is shown in Figure 22, [7] creates a squaring circuit using floating gate transistors and [8] enhances a Gilbert multiplier [70] with a floating gate memory cell. ...
... Some architectures follow the same principle but use folded cascode differential pairs [76], include multiple mirrors [77,78] or produce more than one Gaussian curve [79]. Furthermore, some designs [9,80] are inspired by Gilbert's Gaussian circuit, shown in Figure 25, which is not fundamentally different from the previous implementations but is based on the Gilbert multiplier [70], an example is shown in Figure 26. ...
This review paper explores existing architectures, operating principles, performance metrics and applications of analog Gaussian function circuits. Architectures based on the translinear principle, the bulk-controlled approach, the floating gate approach, the use of multiple differential pairs, compositions of different fundamental blocks and others are considered. Applications involving analog implementations of Machine Learning algorithms, neuromorphic circuits, smart sensor systems and fuzzy/neuro-fuzzy systems are discussed, focusing on the role of the Gaussian function circuit. Finally, a general discussion and concluding remarks are provided.
... The first bipolar analog multiplier known as the Gilbert cell was published in 1968 by Barrie Gilbert [10]. Since analog multipliers based on CMOS technology have been classified (i) according to the form of the input signal; current or voltage mode (ii) with regard to the operating region of the transistors; weak inversion [8], [11], [12] strong inversion [13], [14], saturation region [15] and linear region [16], [17]. ...
... Gilbert cell is one of the first studies of analog multiplication circuits proposed by Barrie Gilbert in 1968 [10]. Gilbert cell is popular in bipolar integrated circuits (IC) due to its wide dynamic range and bandwidth. ...
... Nonlinear terms and voltage-controlled gains are achieved through the use of multiplier blocks. Four-quadrant analog multipliers have traditionally been based on the Gilbert cell, which relies on the exponential relation between voltage and current in PN junctions to realize multiplication in the current domain [50]; when operating with voltage-mode signals, voltage-to-current converters are required to achieve good linearity over a reasonable range of input voltages [47]. Though the Gilbert cell may be realized with properly biased MOS devices, linearity and accuracy are often limited [51]. ...
Analog computing is based upon using physical processes to solve formal mathematical problems. In the past, it was the predominant instrument of scientific calculations. Now, as the physical limits imposed on digital devices compel research into alternate computing paradigms, a reexamination of the potentialities of analog computing is warranted. This work studies the application of analog CMOS cells toward the simulation of dynamical systems, and, more generally, solving sets of coupled time-dependent ordinary differential equations. Following a brief review of the fundamentals of systems theory and analog computing, the main set of computing elements is introduced, each comprising analog cells designed in a 130 nm process. These are subsequently applied to the realization of practical, special-purpose analog computing modules. Illustrative systems from various fields are selected for simulation. Though by no means comprehensive, these case studies highlight the capabilities of contemporary analog computing, especially in solving nonlinear problems. Circuit simulations show good agreement with solutions obtained from high-order numerical methods, at least over a limited range of system parameters. The article concludes with a brief discussion of broader analog computing applications, offering future prospects toward further exploration of its potentialities and limitations in a wide range of domains.
... The Q-band down-conversion mixer was designed using a Gilbert-cell topology for a high conversion gain and isolation performance [20,21]. A schematic of the mixer is shown in Figure 5a. ...
This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.
... The analog multiplier plays a vital role in signal processing circuits and it is widely used in varieties of applications such as adaptive filtering, convolving, curve fitting, square rooting, squaring, automatic gain control, modulation, phase locked loop, rectifications, and fuzzy integrated systems. In the literature, various approaches have been used to implement analog multipliers that include the translinear principle of BJT [1], modified Gilbert cell [2,3], switched capacitors [4], and square law property of complementary MOSFET [5]. The analog multipliers have been designed in both voltage and current modes. ...
In this manuscript, a new four-quadrant analog multiplier has been designed using a current-mode analog building block namely an extra-X second-generation current-controlled conveyor, and two MOS transistors. The passive components have not been used in the design of the proposed analog multiplier which leads to a simpler configuration. The proposed multiplier has been simulated using the PSPICE simulation tool with 0.18 µm Taiwan semiconductor manufacturing company parameters. The obtained simulation results are in close agreement with the theory. The performance of the proposed multiplier is satisfactory for the input voltage range of ± 0.6 V and a supply voltage of ± 0.9 V. The power consumption of the proposed multiplier is 0.26 mW. The multiplier is less sensitive to variations in temperature. The − 3 dB bandwidth of the proposed multiplier is 287.44 MHz whereas the output noise is 6.02 nV/√Hz for a 1 kΩ load. The non-ideal analysis of the proposed multiplier has also been done including all parasitic impedances. The performance of the proposed multiplier is found to be satisfactory in the application of amplitude modulation, squarer, and frequency doubler circuits.
... They consist of a transconductor stage, ensuring the voltage-to-current conversion, and an on/off switching core resulting in an intermediate frequency (IF) signal. Despite their low noise figure (NF), they have high linearity, high voltage conversion gain (VCG) and large frequency response [13], [14], [15], [16]. Their NF can be improved by adding some design noise reduction techniques [17]. ...
In this paper, different topologies of RF self-oscillating mixers (SOM), stacking the voltage controlled oscillator (VCO) and the mixer on top of each other, are assessed. Their design considerations to address sub-mW operation suitable to ultra-low power applications are presented. Two configurations of SOM circuits are implemented in 130nm CMOS technology. The obtained results are presented and performances in terms of gain, noise, linearity, area, power consumption and stability over process and mismatch are compared and discussed.
... In addition, both direct multiplication technology [19,20] and add-and-square technology [21,22] can be used to implement the analog correlator. Due to the need to customize the special multiplier chip, the cost and difficulty of the analog correlator, which uses direct multiplication technology, to achieve broadband is relatively high [23]. By comparison, the analog correlator using add-and-square technology is generally based on the six-port technique [24]; due to its low cost and ease in achieving large bandwidth, the six-port technique is widely used in the fields of reflectometers [25][26][27], receivers [28][29][30], correlators [31,32], and so on. ...
Human body temperature is a fundamental physiological sign that reflects the state of physical health. It is important to achieve high-accuracy detection for non-contact human body temperature measurement. In this article, a Ka band (32 to 36 GHz) analog complex correlator using the integrated six-port chip is proposed, and a millimeter-wave thermometer system based on the designed correlator is completed for human body temperature measurement. The designed correlator utilizes the six-port technique to achieve large bandwidth and high sensitivity, and miniaturization of the correlator is achieved through an integrated six-port chip. By performing the single-frequency test and the broadband noise measurement on the correlator, we can determine that the dynamic range of input power of the correlator is −70 dBm to −35 dBm, and the correlation efficiency and equivalent bandwidth are 92.5% and 3.42 GHz, respectively. Moreover, the output of the correlator varies linearly with the input noise power, which reveals that the designed correlator is suitable for the field of human body temperature measurement. Then, a handheld thermometer system, with a size of 140 mm × 47 mm × 20 mm, is proposed using the designed correlator, and the measurement results show that the temperature sensitivity of the thermometer is less than 0.2 K.
... For the implementation of the analog multiplier, different architectures ranging from a Gilbert cell [57], to double balanced architectures [58] and low-voltage designs such as a folded four-quadrant design [59,60] and multipliers based on a pseudo-differential architectures [61,62] have been studied in [63]. Due to the relatively good linearity and symmetry and particularly because of requiring the lowest voltage headroom, the latter has been chosen for implementation. ...
In dieser Arbeit wird eine Sammlung von Schaltungen auf der Grundlage von Transkonduktanzverstärker-Kondensator Architekturen (OTA-C) vorgestellt. Im Vergleich zu anderen Schaltungstechniken, wie z.B. Operationsverstärkern (OPAMPs), ist der Transkonduktanzverstärker ein grundlegender und vielseitiger Baustein, der auf eine Vielzahl von Anwendungen zugeschnitten werden kann, die hohe Bandbreiten, geringen Stromverbrauch, geringes Rauschen und einen geringen Fächenbedarf erfordern.
Die Realisierbarkeit von OTA-C-Filtern für hochfrequente und hochgradig rekonfigurierbare Schaltungen wird durch die Implementierung und Charakterisierung eines fieldprogrammable analog array (FPAA) in einer 130 nm-Technologie gezeigt, der Filter bis zu einer maximalen Eckfrequenz von 350MHz instanzieren kann und eine on-chip Filterkalibration integriert. Die Kalibration basiert auf einer neuartigen Filterentwurfsmethode für OTA-C Leapfrog-Filter, die im Gegensatz zu anderen bekannten Ansätzen nicht auf konventioneller Koeffizientenanpassung oder Transformationen von äquivalenten OPAMP-RC oder passiven Filterstrukturen beruht. Die Entwurfsmethode umfasst Techniken zur Optimierung für Implementierungen mit hoher Linearität oder niedriger Leistungsaufnahme und ist im Vergleich zu konventionellen Entwurfsverfahren bis zu einigen Größenordnungen rechnerisch effizienter.
Der günstige Trade-off zwischen Leistung und Bandbreite von OTAs wird auch ausgenutzt, um Schaltungen mit reduzierter Bandbreite und geringer Leistungsaufnahme zu entwerfen. Dies wird durch verschiedene Implementierungen gezeigt, wie z. B. ein OTA-C Schleifenfilter für eine energieeffiziente elektromechanische Sensorausleseschaltung in einem geschlossenen Regelkreis, die auf ΔΣ-Modulation basiert. Bei diesem Design sowie bei der schaltungstechnischen Implementierung einer automatischen Filterkalibration werden Stromspiegel-OTAs umfassend genutzt. Der Stromspiegelansatz ermöglicht es, OTAs mit mehreren Ausgängen zu implementieren, was zu vereinfachten und sehr kompakten Schaltungen führt. Unter Verwendung dieser Technik wurde der vorgestellte Schleifenfilter mit einer äquivalenten Fläche von nur 5,5 OTAs entworfen, anstatt 11 OTAs, wie es bei der Implementierung von einzelnen Transkonduktanzverstärkern erforderlich wäre.
Außerdem enthält der Schleifenfilter einen Resonator mit einem hohen Gütefaktor. Solche Resonatoren werden üblicherweise entweder mit OPAMP-RC Architekturen entworfen oder erfordern große und komplexe Schaltungen zur Feinabstimmung der Güte. Es wird ein Verfahren gezeigt, das einfach und dennoch robust gegenüber Prozess- und Temperaturschwankungen ist und einen Gütefaktor des Resonators von über 3640 (3σ) für eine nominale Mittenfrequenz von 25 kHz und über 1000 erreicht, wenn die Mittenfrequenz in einem Einstellbereich zwischen 13 kHz und 31 kHz variiert. Im Rahmen dieser Anwendung wird auch ein OTA-basierter Digital-Analog-Umsetzer mit Stromausgang vorgestellt, der zur Abstimmung des Bias-Stroms des Schleifenfilters verwendet wird, aber auch als allgemeiner Baustein für Anwendungen geeignet ist, die feine Stromkalibrierungen erfordern. Der Ansatz wird im Hinblick auf seine Robustheit gegenüber Prozessvariationen mit konventionellen Stromquellenarrays verglichen, wobei sich zeigt, dass die vorgestellte Architektur eine bis zu viermal kleinere Schaltungsimplementierung ermöglicht.
Schließlich wird ein Design vorgestellt, das alle Vorteile von OTA-C Schaltungen, d.h. geringer Stromverbrauch, geringes Rauschen und geringe Fläche, für den Anwendungsbereich neuronaler Ausleseschaltungen kombiniert. Das modulare Design ermöglicht diedirekte Analog-Digital-Umsetzung neuronaler Signale auf einer Fläche von 70x70 μm unter jeder Sensorelektrode auf dem Schaft einer aktiven, nadelförmigen subkortikalen CMOS Sonde. Die vollständige Integration auf dem Schaft wird durch einen energie und flächeneffizienten inkrementellen ΔΣ-Wandler erster Ordnung mit einem einstufigen OTA-C Integrator erreicht. Im Vergleich zum Stand der Technik benötigt die Sonde nur eine digitale 4-Draht Schnittstelle und ermöglicht das gleichzeitige Auslesen einer großen Anzahl von 144 Elektrode. Die Basis der Sonde ist so schlank wie der Schaft und hat eine Breite von 70 μm. Damit kann die aktive Sonde vollständig im Hirngewebe versenkt werden.
Einstufige OTA-C Schaltungen werden auch im Zusammenhang mit der analogen Signalverarbeitung unter Verwendung organischer Dünnschichttransistortechnologien (OTFT) analysiert. Es werden OTA-C Filter mit einem einzigen differentiellen Zweig vorgestellt, die nur p-Kanal Transistoren verwenden und die Einschränkungen überwinden, die sich aus den ausgeprägten Nicht-Idealitäten organischer Bauelemente ergeben, wie z. B. eine geringe Mobilität und hohe parasitäre Kapazitäten. Der Ansatz ermöglicht die Implementierung von Filtern mit Eckfrequenzen bis zur Hälfte der Transitfrequenz, was analoge OTFT-Schaltungen für z.B. Audioanwendungen ermöglicht.
... 17: Noise and linearity performances vs mixing transistors gate width. ...
With its ability to detect distant targets under harsh visibility conditions, the 77 GHz automotive radar plays a key role in driving safety. Using mm-wave frequencies allow a good range resolution, a better circuit integration and a wide modulation bandwidth. This is also a challenge for circuit designers who must fulfill stringent requirements especially on the receiver front-end. First 77 GHz radar receivers were manufactured with SiGe BiCMOS processes benefiting from the high transition frequency and high breakdown voltage of Hetero-junction Bipolar Transistors (HBT). Good results have been achieved with active-mixer-based architectures, but these technologies suffer from high power consumptions, limited integration capacity and large production cost. More recently, the scaling down of CMOS processes (coming together with the increase of the transition frequency of the transistors) makes CMOS a good candidate for 77 GHz circuit design, especially when cost target requires single chip solutions. The literature related to CMOS radar receivers highlights that receivers based on BiCMOS architectures generally show poor performances. The aim of this work is to demonstrate that using CMOS specific technics such as sampling and the use of high-speed digital gates should enhance the performance of the receivers. In this work, two innovative radar receiver architectures based on the sampling principle are proposed. The first one shows that this principle can be extended to millimeter wave frequencies to benefit from a very good noise/linearity trade-off. While the second one uses this principle to converts a 77 GHz RF signal by using a 26 GHz LO frequency thus simplifying the LO distribution chain of the receiver. The background of this study is introduced in the chapter 1 presenting the design trade-off related to the 77 GHz radar receiver and provides a review of the existing solutions. The following chapter describes the sampling mixer principle and the implementation of a 77 GHz sampling mixer in 28-nm FDSOI CMOS technology. Then, a sub- sampling mixer topology allowing to convert an RF signal around 77 GHz using a 26 GHz LO frequency is detailed in the chapter 3. The chapter 4 draws the conclusion of this study by showing the implementation of the two proposed sampling-based mixers with a low noise amplifier in 77 GHz front ends. These receiver architectures are compared with the state of the art highlighting the strengths and weaknesses of the proposed solutions. The results of this study demonstrates that using sampling for down conversion can be convenient to address millimeter-wave frequency applications.
... The analog correlator can be implemented using either direct multiplication technology [18][19][20][21] or add-and-square technology [22,23]. The direct multiplication analog correlator is normally carried out using non-linear devices such as mixers or analog multipliers [24]. Due to the limitation of multiplier chips, the correlator has the disadvantage of low bandwidth and operates in the low-frequency range. ...
Six-port technology has been widely used in microwave systems, such as interferometric passive imaging. In this paper, an integrated Ka-band (32-36 GHz) six-port chip based on the 0.15-μm GaAs technology is designed and fabricated to simplify the circuit structure and miniaturize the volume of the imaging system. The designed chip integrates two amplifiers, two phase shifters, and a six-port circuit as part of an analog complex correlator. In this integrated chip, the crosstalk between the two amplifiers cannot be ignored. This paper analyzes the influence of the isolation between two amplifiers on the correlation results to guide the six-port chip design. In addition, considering that the radiometer system receives a broadband noise signal, the phase shifter needs to ensure that the phase shift range of each frequency point is the same under the same control conditions. Therefore, the phase shifter is designed with a high-pass and low-pass structure. The measurement results show that the isolation between the two amplifiers is greater than 20 dB, and the measured phase shift range and phase shift range error of the designed chip are 220° and 10°, respectively, with the control voltage varying from 0 to 1.5 V, which meets the requirements of the system.
... Figure 7 shows the schematic of the mixer designed in this work. This mixer utilises the double-balanced Gilbert cell proposed in [45] as the mixer core composed of the RF nMOS transistors M 1 − M 9 , which provides benefits such as a wide operation band, high linearity, high conversion gain and strong immunity against common mode noise. The conversion gain A cv of the Gilbert cell mixer is approximated as the transcondutance of the g m stage multiplied by the load resistance R 8/9 : ...
This work investigates a 5.5–7.5‐GHz band‐configurable duty‐cycled wake‐up receiver (WuRX) fully implemented in a 45‐nm radio‐frequency (RF) silicon‐on‐insulator (SOI) complementary‐metal‐oxide‐semiconductor (CMOS) technology. Based on an uncertain intermediate frequency (IF) super‐heterodyne receiver (RX) topology, the WuRX analogue front‐end (AFE) incorporates a 5.5–7.5‐GHz band‐tunable low‐power low‐noise amplifier, a low‐power Gilbert mixer, a digitally controlled oscillator (DCO), a 100‐MHz IF band‐pass filter (BPF), an envelope detector, a comparator, a pulse generator and a current reference. By application of duty cycling with a low duty cycle below 1%, the power consumption of the AFE was significantly reduced. In addition, the on‐chip digital bank‐end consists of a frequency divider, a phase corrector, a 31‐bit correlator and a serial peripheral interface. A proof‐of‐concept WuRX circuit occupying an area of 1200 μm by 900 μm has been fabricated in a GlobalFoundries 45‐nm RF‐SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 μW. Tested at 8 operation bands covering 5.5–7.7 GHz, the WuRX has a measured sensitivity between −67.5 dBm and −72.4 dBm at a wake‐up error rate of 10⁻³. With the sensitivity unchanged, the data rate of the WuRX can be scaled up to 8.2 kbps. To the authors' best knowledge, this work offers the largest RF bandwidth from 5.5 to 7.5 GHz, the most operation channels (≥8) and the fastest settling time (<115 ns) among the WuRXs reported to date.
... The principle is illustrated in Figure 21. The output current of the Gilbert multiplier [26] is described by equation: ...
Analog Neuromorphic Systems.
First in the world fully analog Neural Network with analog backpropagation learning system.
Analog synthesizer of orthogonal signals.
System of self-correction for analog (imperfect: with off-sets of values) learning system: (similar to some parts of animal/human sleep).
... When each of the signals to be multiplied are differential a four-quadrant topology may be considered. The Gilbert cell, shown in Fig. 1 [1], is the base for many variations of this type of multipliers [2,3,4,5,6,7,8,9,10]. It consists of two cross-coupled differential pairs formed by transistors M1-M4 and controlled by one differential input signal V xy = V x − V y . ...
A four-quadrant analog multiplier with ultra-low supply voltage operation, rail-to-rail input swing and insensitive to different dc levels between the multiplied input signals is presented. It is based on the Floating-Bulk technique, in which the input signal is coupled to the bulk terminal of a PMOS transistor by means of an input capacitor. This allows rail-to-rail operation and eliminates the dc level of the input signals regardless of the offset between them, maintaining linearity. Moreover, it also eliminates the threshold-voltage requirement in the signal path of the input transistors, allowing very low voltage operation defined by a gate-source and a drain-source voltages. Experimental results in 0.5µm technology demonstrate rail-to-rail operation with a 1.1V supply voltage even with different dc level voltages between the multiplied input signals. It offers a distortion of THD =0.95% for an input signal of 0.2Vpp at 100kHz.
... While the results presented above were obtained from simulation on a digital computer using the Euler-Maruyama algorithm, LSC was designed with stochastic analog implementation in mind. In this section, we present one candidate hardware implementation making use of Gilbert cells, a type of fast analog voltage multiplier (Gilbert, 1968). ...
We describe a stochastic, dynamical system capable of inference and learning in a probabilistic latent variable model. The most challenging problem in such models - sampling the posterior distribution over latent variables - is proposed to be solved by harnessing natural sources of stochasticity inherent in electronic and neural systems. We demonstrate this idea for a sparse coding model by deriving a continuous-time equation for inferring its latent variables via Langevin dynamics. The model parameters are learned by simultaneously evolving according to another continuous-time equation, thus bypassing the need for digital accumulators or a global clock. Moreover we show that Langevin dynamics lead to an efficient procedure for sampling from the posterior distribution in the 'L0 sparse' regime, where latent variables are encouraged to be set to zero as opposed to having a small L1 norm. This allows the model to properly incorporate the notion of sparsity rather than having to resort to a relaxed version of sparsity to make optimization tractable. Simulations of the proposed dynamical system on both synthetic and natural image datasets demonstrate that the model is capable of probabilistically correct inference, enabling learning of the dictionary as well as parameters of the prior.
... The structure of a Gilbert-cell mixer can be seen in Fig. 2 [8]. M4, M5, M6, and M7 transistors work as a switch. ...
... From Fig. 1 we can see that each AN requires potentially very large numbers of multipliers for performing the inputweight product terms. These can become very power hungry when implemented either in analogue [5] or digital [6]. The problem is exacerbated when scaling up to large ANNs with hundreds of thousands or millions of ANs, each receiving hundreds of inputs. ...
In recent years, RRAM technology has been actively developed as a means of reducing power dissipation and area in a host of circuits, most notably artificial neuron synapses. However, further reduction in energy consumption may be possible by transitioning to capacitive synapses and combining them with adiabatic technique. In this work, we present and analyse the function and power dissipation of an artificial neuron with capacitive synapses where the synaptic tree is fed by a regenerative clock. Whilst the weights are fixed in this case, developments into memcapacitor technology offer the promise of tuneability in the future. In our example, a 4-synapse design was used as a proof-of-concept baseline at various frequencies. Our simulation at 1MHz indicates a ≈ 91% reduction of energy when using Regenerative Capacitive Synapses vs. standard, non-regenerative ones, which translates into a ≈ 35% drop in overall artificial neuron energy dissipation. The higher the ratio of synapses/soma, the higher the power savings, which is important for building larger and more complex neurons in silico.
... A Gilbert cell mixer circuit is given in figure 7-17 [24]. A corresponding netlist is given in Fig. 7-18. ...
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas:
• Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers.
• A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models.
• Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only).
• Object-oriented code design and implementation using modern coding practices.
Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
... A Gilbert cell mixer circuit is given in figure 7-17 [24]. A corresponding netlist is given in Fig. 7-18. ...
This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas:
• Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers.
• A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models.
• Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only).
• Object-oriented code design and implementation using modern coding practices.
Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.
... In [65], a wide-IF-bandwidth Gilbert-cell mixer [66], whose load stage is realized by an inductor-capacitor (LC) resonant circuit with a switchable capacitor array, in a complementary metal-oxide-semiconductor (CMOS) process is proposed. With the proposed mixer in [65], the mmWave siganls are downconverted to the IF band and can be transmitted through an IFoF system. ...
div>With higher frequencies and broader spectrum than conventional frequency bands, the millimeter-wave (mmWave) band is suitable for next-generation wireless networks featuring short-distance high-rate communications. As a newcomer, mmWaves are expected to have the backward compatibility with existing services and collaborate with other technologies in order to enhance system performances. Therefore, the coexistence issues become an essential topic for next-generation wireless communications. In this paper, we systematically review the coexistence issues of broadband mmWave communications and their corresponding solutions proposed in the literature, helping shed light on the insights of the mmWave design. Particularly, the works surveyed in this paper can be classified into four categories: coexistence with microwave communications, coexistence with fixed services, coexistence with non-orthogonal multiple access (NOMA), and other coexistence issues. Results of numerical evaluations inspired by the literature are presented for a deeper analysis. We also point out some challenges and future directions for each category as a roadmap to further investigate the coexistence issues of broadband mmWave communications.</div
... where x and y are the inputs and A is a constant. The first analog multiplier design which consists bipolar junction transistor (BJT) has been proposed by Gilbert in Low-Voltage and Low-Power Analog Multiplier/Divider Using OTA Based on DTMOS Transistor DTMOS Transistör Tabanlı OTA Kullanan Düşük-Gerilimli ve Düşük-Güçlü Analog Çarpıcı/Bölücü Melih Yıldırım 1* 1968 [1]. In analog multiplier circuits, the properties of consuming low power and having low power supply voltages take an important place. ...
... The TVGA has an n-bit control input, and the cosine or sine amplitudes of a given frequency are preloaded in a look-up-table (LUT). The second downconversion could be done employing a Direct Digital Synthesizer [22] and a classical mixer [23]. However, such a solution required a digital-to-analog converter (DAC), and classical mixers would be switched. ...
In this work, we present a new RF receiver architecture capable of addressing different RF bands and communication protocols. The frequency planning and discrete-time complex signal processing choices greatly simplify the frequency synthesis circuit. Since this is one of the most power-hungry blocks in the receiver, one can expect a reduction in power consumption. Thanks to the Bandpass Sampling (BPS) technique, the receiver addresses multiple RF bands without changing the sampling frequency. The BPS downconverts the signal to a varying Intermediate Frequencies (IF), called sliding IF. From this point on, the signal processing is in the discrete-time domain. The same clock is employed to drive a time-varying gain amplifier (TVGA), which implements a mixing process by multiplying the input with a sine or cosine centered at IF. A Double-Quadrature Low-IF frequency planning and complex signal processing avoid the problem of image signal folding in both downconversions. Behavioral modeling shows how this architecture can be utilized for LTE and IEEE802.11g standards, fulfilling the noise, linearity, and image rejection specifications. With 6 bits resolution in the TVGA gains, the quantized sine and cosine lead to a Signal-to-Distortion Ratio of 48dB. The receiver achieves an image rejection of 55dB for the LTE standard and 42dB for IEEE802.11g.
... One of the basic blocks in analog circuits is a multiplier and it is the most important part of adaptive filters, modulators, signal processing circuits and fuzzy logic controllers. An ideal multiplier produces a linear output signal which is obtained from two linear input signals with a constant designated as k [4]. The analog multiplier can be divided into two groups, voltage mode [5] and current mode [6][7][8]. ...
The endeavor to overcome problems of complementary metal oxide semiconductor technology makes the advent of Carbon nanotube field effect transistor (CNTFET). Improvement of structure transistor CNTFET makes higher mobility and electrostatics of gate electrons. Therefore, many analog circuits are now designed based on CNTFET technology. This paper presents a low power current mode four-quadrant analog multiplier based on CNTFET and CMOS technologies. All simulations were done with the synopsys Hspice simulator using 32nm CNTFET model from Stanford University and 32nm CMOS from PTM library at a supply voltage of 3.3 v. It was shown that the simulation of a multiplier based on CNTFET technology performs better than a multiplier based on CMOS technology.
Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the I-V characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors that the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in the 22-nm BSIM4 CMOS process and the Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies.
This chapter is dedicated to the theory and circuits for frequency translations. Whereas linear circuits have inputs and outputs at the same frequency, non-linear circuits can generate additional frequencies as either an intentional or unintentional result. This chapter provides comprehensive coverage of various frequency translation topics, including the widely used frequency mixing, as well as essential frequency multiplier and divider concepts that are needed for designing frequency synthesizers.
The capability to sense the dielectric properties of liquids and tissues is valuable in many applications, because accurate assessment of the material composition can be made from the complex permittivity measurements. Laboratory-on-chip systems for continuous dielectric monitoring impose low-voltage and low-power operation on the circuits to enable long-term use without battery replacement. In addition, high level of integration is necessary to facilitate the implementation of 2-D sensor arrays. This letter presents the design and characterization of a SiGe BiCMOS capacitive sensing oscillator-based complex dielectric sensor chip at
Ka
-band operating with a supply voltage of 1.2 and consuming 27 . The chip is integrated with readout circuits to provide simple dc outputs for easier processing and with reference circuits to serve as a tool to compensate for both the external and internal variations, which affect the sensor output. The experimental results show that different alcohols can be differentiated using the proposed sensor chip.
Design of microwave circuits require extensive simulations, which often take significant computational time due to design complexity. This can be addressed through neural networks (NNs) that provide predictive capability. Predictions often come with uncertainties that need to be quantified. Moreover, optimization and inverse designs are better done using probabilities. This article describes the use of Bayes theorem and machine learning (ML) for solving complex microwave design problems.
Dry cask storage is one of two storage methods approved by the U.S. Nuclear Regulatory Commission for spent fuel after removal from reactor cores. Dry casks consist of a stainless steel canister enclosed in a concrete overpack to contain the hazardous radioactive spent fuel rods and provide radiation shielding. Monitoring spent fuel storage casks is desired to ensure the safe containment of the enclosed spent fuel, but is very difficult due to the related harsh temperature and radiation environment. The sensors and associated electronics to monitor temperature, pressure, and/or radiation need to survive high temperatures and radiation doses for extended time periods. For this reason, there is a severe need for radiation-hardened electrical systems that survive well beyond the existing capabilities of commercially available radiation-rated electronic components, which have primarily been developed for space applications. Junction-gate field-effect transistor (JFET) devices are inherently radiation hardened [exceeding 100 Mrad (Si)]. When JFETs are used as building blocks for sensing and communication electronics (i.e., oscillators, amplifiers, filters, and mixers), inherently radiation-hardened circuits can be achieved. To this end, JFET-based radiation-hardened electronics interfacing with cask-embedded sensors capable of driving modulated sensor signals through a stainless steel barrier were designed and tested at a dose rate of approximately 500 krad/h (Si) to beyond a 200-Mrad (Si) total ionizing dose. After 200 Mrad (Si), the sensor and communication circuit signals were correctly decoded at the receiver despite oscillator drift. The results from this experiment demonstrate the potential for creating more complex radiation-hardened JFET-based electrical systems for nuclear environments.
Bei Gleichrichterschaltungen insbesondere höherer Leistung, aber auch bei Auftreten einer Vielzahl solcher geringerer Leistung, können die durch leistungselektronische Systeme verursachten Netzrückwirkungen, vor allem die erzeugten Oberschwingungen und die Blindleistungen, nicht mehr vernachlässigt werden. Um die Qualität der Netzspannung sicherzustellen, definieren die EVUs Vorschriften über maximal zulässige Energie oder andere Kennwerte der vom Verbraucher erzeugten Stromoberschwingungen. Auch im Hinblick auf die immer genauer und strenger werdenden Richtlinienwird es daher notwendig, Stromrichterkonzepte zu entwickeln, die möglichst geringe Netzrückwirkungen verursachen.
Analog-to-digital converters are built from operational amplifiers, current mirrors, biasing circuits, buffers, oscillators and many more elementary circuits. This chapter starts with one and two transistor circuits and expands to more complex topologies. Fundamental ideas, like Miller compensation, distortion in differential pairs and cascoding are analyzed and popular implementations are shown. Where needed small and large signal analysis is provided.
This chapter is concerned with the design of terahertz transmit and receive analog frontends on the basis of high electron mobility transistor technology. While HEMTs offer the highest cutoff frequencies and, hence, allow for the best gain-bandwidth tradeoffs at THz frequencies, the design paradigms of the implementation of HEMT-based transceiver MMICs for THz communication are very different from their counterparts in HBT and Si MOSFET technologies. This chapter highlights and discusses those design paradigms and reviews the state of the art in HEMT-based transceivers dedicated to THz communication.
Improving measurement accuracy over a wide range is very important for the measurement system based on four-quadrant detector (4QD). However, its measurement performance is easily affected by the energy distribution of the spot imaged on 4QD, which limits its wider practical application. Existing methods mainly use the collected data for curve fitting to improve the measurement accuracy. However, actual data collection may be difficult, and the spot energy distribution imaged on 4QD may change at any time. In this paper, an active method to improve the measurement accuracy of 4QD is proposed, which can adapt to the change of the spot energy distribution without additional actual data. Experimental results show that the proposed method can effectively improve the measurement accuracy over a wide range with fast detection speed.
A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between −7 and −30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of
$205\times $
and
$140\times $
, respectively.
The development of microwave mixers was fostered during World War II with the development of radar. The single‐diode mixer, although fondly remembered for its use as an AM “crystal” radio or radar detector during World War II, has become less popular due to demanding broadband and high‐dynamic‐range requirements encountered at frequencies below 20 GHz. There are other types of hybrid or balun structures that can be used in the design of single‐balanced mixers, but they are typically used in double‐balanced designs. Single‐balanced mixers have the added advantage of being able to provide some large‐signal noise rejection in the receiving chain. The most commonly used mixer in the microwave portion of the spectrum is the double‐balanced mixer. The majority of mixers are based on FET devices. FETs offer the advantage of good switching properties, provide gate and drain contacts that allow for easier isolation of the ports, and may even offer gain depending on biasing condition.
A microwave component is only useful if either the manufacturer or a third‐party modeling company like Modelithics provide a reliable model. Microwave and millimeter circuit design, especially concerning integrated circuits, requires a skilled engineer using the computer‐aided design tools. The transmission line models provided by radio frequency circuit simulators account for the dispersive effects. At least, the simulator will issue a warning when simulating outside the frequency range for which the model is valid. As the frequency moves up, the wavelength of sinusoidal signals reduces and the bandwidth in hertz of the communications systems continues to increase, including optical circuits. Analog signals travel continuously in real time, so it is very difficult to multiplex signals to increase the number of customers on the frequency band. In the analog world, the heterodyne concept provides the additional advantage of suppressing second‐order intermodulation product.
In this paper, a low-voltage and low-power current mode analog multiplier design is presented. The multiplier is based on dynamic threshold MOS (DTMOS) structure. The proposed topology consists of four current squarer circuits and one subtractor structure. Each squarer cell has two MOS transistors and the subtractor consists four MOS transistors. Therefore, the multiplier employs 12 MOS transistors excluding resistors and biasing current sources. The introduced circuit consumes low power and requires low voltage power supplies thanks to DTMOS structure. The current mode analog multiplier architecture has a power consumption of 99.76nW and involves a single supply voltage of 0.3V owing to including DTMOS transistor. The analysis results agree well with the expected results. The behavior of the suggested multiplier has been verified through the analysis results with the help of LTspice simulation software and 0.13µm IBM CMOS technology parameters have been used for simulation.
The logarithmic nature of the voltage-current characteristics of silicon junction diodes is exploited to design an analogue multiplier. Four silicon junction diodes are used in conjunction with a differential operational amplifier in the multiplier circuit. The principle of operation, design considerations and techniques to compensate for temperature effects and unequal diode parameters are discussed. Methods of performing division and generation of special types of functions are outlined. Measurements on an experimental single quadrant multiplier show that an accuracy of multiplication of the order of 1% can be achieved. Long term temperature drift at the output is measured to be 2% per 10 degC change in ambient temperature. The bandwidth of the multiplier is directly dependent on the operational amplifier employed. With a Donner (Model 3400) amplifier, the bandwidth is measured to be about 200 Hz. An attractive feature of the circuit is that it lends itself for miniaturization with the advent of differential operational amplifiers in the integrated circuit form.
A direct-coupled monolithic IF amplifier that incorporates an active gain control stage and exhibits a power gain of 50 dB and an AGC range of 60 dB at 50 MHz is described. This circuit has negligible change in either input or output admittance, and has excellent signal linearity over the full range of gain control. Experimental and theoretical analyses are made of the large signal response, stability, available gain, and noise behavior of the circuit. An application to color television is discussed in which the functions of the 45-MHz IF amplifier and the dc-AGC circuitry are fabricated on a single die.
Precision dc-coupled amplifiers having risetimes of less than a nanosecond have recently been fabricated using the monolithic planar process. The design is based on a simple technique that has a broad range of applications and is characterized by a stage-gain- bandwidth product essentially equal to that of the transistors, and a very linear transfer characteristic, free from temperature dependence.
Dual output synchronous detector utilizing transistorized differential amplifiers
- H E Jones
An integrated analog multiplier circuit
- E Traa