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A new wide-band amplifier technique
Abstract
Precision dc-coupled amplifiers having risetimes of less than a nanosecond have recently been fabricated using the monolithic planar process. The design is based on a simple technique that has a broad range of applications and is characterized by a stage-gain- bandwidth product essentially equal to that of the transistors, and a very linear transfer characteristic, free from temperature dependence.
... This was useful at a time when analog multiplication was still of broad general value. Its potential was of specific interest to the author in 1966, for use as the core of a 500 MHz variablegain amplifier [5]. BJT-LTP cells remain at the heart of many contemporary VGAs, sometimes using another circa-mid-1960's linear transconductance concept, the multi-tanh principle [6]. ...
... This was the first example of a large class of nonlinear current-mode circuits. The extension of this basic topology to four-quadrant multiplier operation was straightforward [5] and has been widely used. Scores of other such cells quickly followed [5][6][7], numerous patents, and doctoral theses, notably that of Seevinck [8], which cataloged all the then-known cells as well as examples of formal synthesis methods. ...
... The extension of this basic topology to four-quadrant multiplier operation was straightforward [5] and has been widely used. Scores of other such cells quickly followed [5][6][7], numerous patents, and doctoral theses, notably that of Seevinck [8], which cataloged all the then-known cells as well as examples of formal synthesis methods. In 1975, the author proposed a formal definition of this class of circuits, based on the strict translinear (STL) principle [9], in which all state variables are currents, and all voltages are incidental. ...
Many claims have been made about the benefits of a current-mode (CM) approach to IC design. The term is used to draw attention to some kind of special dependence on currents as signals, often without a clear orientation to the broader field, referring instead to recent CM papers. Its use suggests a significant and valuable distinction over “conventional” solutions, perhaps in the hope that this perspective, with an element of novelty at the cell level, will influence circuit design in the stringent context of IC production. This paper asks: What factors unambiguously define a current-mode circuit, and formally differentiate it from standard realizations of some function? Can one point to any compelling, and in the most favorable cases unique, advantages? Are these cells clearly of general value, capable of widespread utility? These issues are examined from the critical viewpoint that no circuits carry the entire functional burden by the exclusive use of either currents or voltages, and very few fully exploit the specific, but narrow, benefits of CM concepts. Real-world product development invariably demands the vigilant and full embrace of what might be called the Free Mode perspective, but merely as a mnemonic, not a classification.
... Current mode operation is beneficial in predominantly capacitive IC environment due to maximized speed and minimized voltage swing [4][5][6]. A major factor limiting the speed of voltage mode signals is the time needed to charge and discharge parasitic capacitances at the internal nodes as the node voltages swing [5]. ...
... Current mode operation is beneficial in predominantly capacitive IC environment due to maximized speed and minimized voltage swing [4][5][6]. A major factor limiting the speed of voltage mode signals is the time needed to charge and discharge parasitic capacitances at the internal nodes as the node voltages swing [5]. Since the voltage swings in current mode circuits are reduced, voltage changes across parasitic capacitances will be less. ...
A novel current buffer stage with very low input resistance is proposed. Low input resistance is achieved using a potentially instable positive feedback loop. Stability of the circuit under different operating conditions is examined in details. A feedback control block using a bipolar 4-bit current steering DAC as a control mechanism is added to the buffer to control the input resistance and assure stability. The proposed technology-independent design methodology always ensures precision and stability for all different parasitic capacitor and resistor values of the driving signal source as well as for process, mismatch, and environmental variations. Additionally, a novel second generation current conveyor circuit based on this novel input buffer is presented to demonstrate how this buffer makes almost ideal current mode circuits possible. Filter applications using the proposed CCII are performed for further justification. The current buffer and CCII were built in AMS 0.35 μm 2P4M CMOS technology. Measurement results are presented for the current buffer, the CCII circuit, and the filters.
... Los circuitos translineales, propuestos por Gilbert [1] en 1975, permiten implementar toda una familia de circuitos electrónicos (denominados translineales) que se utilizan en el procesado analógico de señal para realizar con precisión operaciones como amplificación (Gilbert [2]), productos (Gilbert [3]), divisiones, potencias y raíces en el dominio de la corriente. También se emplean en el filtrado de señales, donde reciben el nombre de filtros log-domain, propuestos por Adams [4] en 1979 y Seevinck [5] en 1990. ...
... El transistor bipolar (BJT) se considera el elemento translineal por excelencia y es el que se ha venido utilizando desde los inicios del diseño translineal (Gilbert [2][3]). Sigue la ecuación (3.1) durante ocho décadas de corriente de colector, tomando λ como el área relativa de la unión base emisor, η como un valor próximo a la unidad y el terminal de puerta del elemento translineal ideal como el terminal de base del BJT. ...
... The second stage of ADPreampl3 amplifier is a differential stage (DS) on Q 17 and Q 18 with a Gilbert cell (Q 11 -Q 14 ) as a collector load for providing a smooth gain control [34]. ...
... The double-balanced four-quadrant analog multiplier, invented in the 1960s by Howard Jones [1] and then improved upon by Barrie Gilbert [2,3], is ubiquitous in numerous modern electronic systems. Shown in Figure 1, this topology effectively multiplies its two input voltages V RF and V LO . ...
We present an extension of the double-balanced current-commutating analog multiplier (also known as the Gilbert cell) that enables the multiplication of an arbitrary number of signed differential input voltages. A general analysis of the circuit for an arbitrary device nonlinearity is provided, and simulations on a bulk CMOS process as well as measurement results of a discrete bipolar implementation are reported.
... Bipolar Gilbert multiplier cell mixer is the most commonly used architecture. This topology is based on the traditional bipolar cross-coupled differential modulator stage introduced by Gilbert [1]. A CMOS counterpart of the traditional bipolar Gilbert cell mixer is shown in Fig. 1. ...
A CMOS down-conversion mixer using current folded-mirror technique is demonstrated in this paper. Apart from the low voltage operation.. the current folded-mirror mixer has a similar performance in gain, linearity, and frequency performance compared with a traditional high voltage mixer. A prototype mixer was implemented in an AMS(R) 0.6-micron CMOS technology. The measured 1-dB compression point is -3 dBm, IIP3 is I dBm. and the conversion gain is -2.5 dB; at an input RF frequency of 900 MHz. The IC consumes 7.5 mW from a 1.5 V supply.
... The Gilbert-cell mixer for the modern receiver design is illustrated in Figure 1 [13]. The Gilbert cell mixer consists of a class-A transconductor stage, a current commutating stage, and a load stage. ...
A high linearity down-conversion mixer for the application of the fourth generation (4G) mobile communication systems is presented. The presented 2.3 to 5.8 GHz broadband mixer adopts current-reused and bulk-controlled techniques. The linearized transconductor stage is composed of the CMOS amplifiers and the bulk-controlled compensation (BCC) transistors. The bulk-controlled voltage is applied to adjust the threshold voltage of the BCC transistor. Thus, the equivalent third-order intermodulation (IM3) term of the CMOS amplifiers and the BCC transistors can be mitigated so as to improve the linearity. Furthermore, the current-reused architecture enhances the conversion gain of the proposed mixer and compensates the loss caused by the shunt feedback matching network. The presented mixer consumes 4.8 mA from a 1.5 V power supply. The measurement results of the mixer exhibit the maximum power conversion gain of 11.3 dB. The input third-order intercept point (IIP3) of 4.7 dBm over the entire 2.3-5.8 GHz band is observed.
The paper regards a new active resistor for ultra-low power applications. Thanks to the chosen topology, based on feedback and operational amplifier, it allows to accurately emulate the voltage versus current characteristic (V-I) of a component with respect to the process, temperature and power supply variations. Furthermore, using a transistor in a series configuration as reference, it is possible to obtain very high resistance values with up to 10 times less area with respect to the resistors available in standard complementary metal-oxide-semiconductor (CMOS) technology. The circuit has been simulated using 1.2-V transistors of a 130nm CMOS technology. Compared with a standard p+ poly-silicon resistors, it exhibits equivalent performance parameters using less area.
The importance of amplifiers that have a wide bandwidth (more than 100MHz), stable gain, and low capacitance distortion in modern electronics is greatly increased. LNA is one of the commonly used types of amplifiers as it is used in all receivers. The idea of LNA is to enhance the received signal sufficiently and make it above the noise level. It is not easy to design this type of amplifier, as two characteristics must be considered when designing: Gain and Noise Figure. To reach a more stable design, one feature must be compromised for the sake of another. Therefore, designing an LNA is not very simple.
This paper aims to design one of the types of high-frequency amplifiers to obtain high gain and a wide frequency band with specifications that enable it to work on several frequencies. That is, to cover the problems of weak signals for many local applications such as band Free, WIFI, mobile phone networks, and other applications.
Current-Reused technology was used to design a two-stage cascade amplifier. The first stage is a CS amplifier and the second stage is a sequential amplifier with an additional buffer stage at the output. The amplifier was designed and applied to the ADS simulation program to obtain the desired results, where we obtained S11 equal to -8.5dB, and the gain reached a value of 48dB with width band from 800MHz to 5GHz. The circuit was able to operate at temperatures up to 200°C without any change in gain, and the circuit was stable during stability tests in the required frequency range.
This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18-[Formula: see text]m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5[Formula: see text]GHz, while less than 0.78[Formula: see text]mW is consumed from a 1.5-V supply. A noise figure of 23.7[Formula: see text]dB is measured. Also, the VGA achieves a gain control range of 19[Formula: see text]dB with a gain error less than [Formula: see text][Formula: see text]dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications.
Bei Gleichrichterschaltungen insbesondere höherer Leistung, aber auch bei Auftreten einer Vielzahl solcher geringerer Leistung, können die durch leistungselektronische Systeme verursachten Netzrückwirkungen, vor allem die erzeugten Oberschwingungen und die Blindleistungen, nicht mehr vernachlässigt werden. Um die Qualität der Netzspannung sicherzustellen, definieren die EVUs Vorschriften über maximal zulässige Energie oder andere Kennwerte der vom Verbraucher erzeugten Stromoberschwingungen. Auch im Hinblick auf die immer genauer und strenger werdenden Richtlinienwird es daher notwendig, Stromrichterkonzepte zu entwickeln, die möglichst geringe Netzrückwirkungen verursachen.
New structured array (SA) MH2XA020 and the way of designing nuclear electronic integrated circuits (ICs) based on it are considered. The SA MH2XA020 contains eight readout channels. Each channel includes a charge-sensitive amplifier (CSA), an amplifier-shaper (AS) with gain control and “tail” cancellation, a sampling and storage device (SSD), and a multiplexer. In the SA, it is possible to change the operating current of the input transistor,
RC
value in the CSA feedback loop, and the peaking time of the AS. Experimental results of eight-channel MH2XA020-01 chip implemented on the SA are presented.
The following chapter includes all the new circuit techniques related to frequency selective stages. After reviewing the Log companding principle of operation, the generalization for the MOS transistor is presented. Based on these results, different types of CMOS basic building blocks for arbitrary Log filters are proposed in conjunction with a compact synthesis methodology. This research is extended to all-MOS implementations for their integration through digital CMOS technologies. Finally, some filter cases and design examples are presented as demonstrators.
Stochastic computation has recently been studied for soft-error-resilient hardware and approximate computing, such as image processing, machine learning, and deep neural networks. This paper reviews stochastic computation and discusses the advantages and disadvantages along with the recent developments in hardware. In addition, stochastic-computation-based brainware LSIs (BLSIs) for vision information processing are introduced and discussed in terms of energy efficiency.
Continuous electronic variability of a memoryless transfer characteristic (current gain, voltage gain, resistance, etc.) is the shared theme of variable-gain amplifiers or attenuators, electronically variable resistances and transconductances, and analog multipliers. Such functions have a long history, predating solid-state devices. The need for variable gain per se has arisen for many decades in such applications as automatic gain control (AGC) [1–5]. Analog multipliers were originally important in analog computers, and more recently in analog implementation of certain signal-processing arithmetic. Variable transconductance (Gm) and resistance (R) circuits, the heart of many variable-gain amplifiers and multipliers, have acquired further importance as elements of tunable monolithic continuous-time filters. Much overlap exists between the circuit techniques for these various functions, embodying relatively few basic circuit principles. This chapter reviews those principles together (switched gain control, a related class, is outside the scope of this survey). Some upshots are summarized from a broader study of this subject matter as of 1981, which is also available [60]. Certain uses of nonsaturated FETs in particular have been reinvented over the decades in different applications, most recently in the application of filters.
Recently, it was proposed to generalize the well-known translinear (TL) circuit principle in such a way that it also applies to MOS transistors operated in strong inversion. The ‘sum-of-square-roots’ relation which is typical for this kind of TL circuits is much more difficult to handle mathematically than the product relation oftraditional TL circuits. Therefore, in this paper a graphical analysis method is presented. Although this method does not result in an exact solution ofthe sum-of-square-roots relation, it does provide some insight into the behaviour of MOS strong-inversion TL circuits. The graphical method was implemented in a computer program, which is now used as an interactive design tool to implement nonlinear signal processing functions. Two design examples are presented in this paper: a class AB output stage for CMOS operational amplifiers and a variable-gamma circuit for colour television.
This paper addresses the design of translinear circuits in the context of CMOS-technology. First, extension of the translinear circuit principle to implementation by MOS transistors operating in strong inversion is reviewed.
Second, the supply voltage requirements are discussed and MOS-translinear circuits for low supply voltage are considered. A circuit technique suitable for the minimum possible supply-voltage is investigated. The key to this approach is allowing current-source transistors to operate in the linear region and viewing these transistors as consisting of two saturated transistors acting as current sources and connected in anti-parallel.
The Analog Circuit Design Series set reduces the concepts of analog electronics to their simplest, most obvious form which can easily be applied (even quantitatively) with minimal effort. The emphasis of the set is to help you intuitively learn through inspection how circuits work and apply the same techniques to circuits of the same class. The third volume Designing High Performance Amplifiers applies the concepts from the first two volumes (9781891121869; 9781891121838). It is an advanced treatment of amplifier design/analysis emphasizing both wideband and precision amplification. Topics include bandwidth extension, noise and distortion, effects of components, instrumentation and isolation, amplifiers, autocalibration, thermal effects, current-feedback amplifiers, multi-path schemes, feed forward, fT multipliers, buffers, voltage translators, Giulbert gain cells and multipliers.
The translinear principle has become quite familiar to IC designers during the past twenty years. Originally conceived within the narrow framework of bipolar, wideband, fixed- and variable-gain current-mode amplifiers employing closed loops of junctions [1,2]—now called TL cells, in which input and output signals and biases are all in pure current form—the scope of the concept has gradually broadened to include any circuit in which the essential function depends directly on a precise exponential relationship existing between the current at one terminal of a suitably-biased three-terminal active device and the voltage applied across the remaining two terminals. A trans linear cell not including any directly closed sloops has more recently [3] been called a translinear network (TN).
Schaltungen, deren primäre Funktionsweise die proportionale Abhängigkeit der Steilheit vom Kollektorstrom bei Bipolar-Transistoren ausnutzt, wurden von Gilbert [1] als ‘translinear’ bezeichnet, und diese Bezeichnungsweise soll hier übernommen werden. Translineare Schaltungen sind nur als integrierte Schaltungen realisierbar. Das Zusammenspiel bipolarer Transistoren in Bezug auf Geometrie und Temperatur spielt beim Entwurf translinearer Schaltungen eine signifikante Rolle.
A new four-quadrant (4Q) Multiplier Complementally using linear and saturation regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is proposed for the wide dynamic range and superior flexibility of the input range. This multiplier operates in the region except for the threshold voltage VT to zero. The validity of the proposed circuit is confirmed through HSPICE simulation.
This paper presents a 7th-order channel-select filter for a spread-spectrum wireless receiver operating with a minimum power supply of 2.5 V. The channel-select filter implements a sharp transition from 2 MHz to 4 MHz and a stopband attenuation of 50dB. The 7th-order filter is realized by a cascade of a passive RC integrator, a 3rd-order leapfrog filter, an operational amplifier based differentiator, a 2nd-order notch filter, and a 1st-order allpass filter. It is designed in a 0.35 μm single-poly BiCMOS process. Simulation results show feasibility of the proposed filter.
A cascade structure of six proposed signal-current enhancers is applied to a standard operational transconductance amplifier (OTA) to improve its gain-bandwidth (GBW) product, slew rate (SR), and voltage gain through significant enhancements of the small-signal and transient output currents from the proposed enhancers. The proposed hybrid OTA is implemented in a standard 0.13 μm CMOS technology, with an active chip area of 0.0027 mm2. Working under a 0.7 V supply and as proven by the measurement results, the resultant OTA when driving an output capacitor of 15 nF attained ~100 dB gain, a GBW of 1.46 MHz, and an SR of 0.47 V/μs, consuming only 24 μA of current and requiring no compensation capacitor.
In this paper a novel high-frequency fully differential pure current mode current operational amplifier (COA) is proposed that is, to the authors’ knowledge, the first pure MOSFET Current Mode Logic (MCML) COA in the world, so far. Doing fully current mode signal processing and avoiding high impedance nodes in the signal path grant the proposed COA such outstanding properties as high current gain, broad bandwidth, and low voltage and low-power consumption. The principle operation of the block is discussed and its outstanding properties are verified by HSPICE simulations using TSMC \(0.18\,\upmu \hbox {m}\) CMOS technology parameters. Pre-layout and Post-layout both plus Monte Carlo simulations are performed under supply voltages of \(\pm 0.75\,\hbox {V}\) to investigate its robust performance at the presence of fabrication non-idealities. The pre-layout plus Monte Carlo results are as; 93 dB current gain, \(8.2\,\hbox {MHz}\,\, f_{-3\,\text {dB}}, 89^{\circ }\) phase margin, 137 dB CMRR, 13 \(\Omega \) input impedance, \(89\,\hbox {M}\Omega \) output impedance and 1.37 mW consumed power. Also post-layout plus Monte Carlo simulation results (that are generally believed to be as reliable and practical as are measuring ones) are extracted that favorably show(in abovementioned order of pre-layout) 88 dB current gain, \(6.9\,\hbox {MHz} f_{-3\text {db}} , 131^{\circ }\) phase margin and 96 dB CMRR, \(22\,\Omega \) input impedance, \(33\,\hbox {M}\Omega \) output impedance and only 1.43 mW consumed power. These results altogether prove both excellent quality and well resistance of the proposed COA against technology and fabrication non-idealities.
This work proposes a novel translinear principle based on time domain processing of signals. The exponential relationship between voltage and time in an RC circuit is exploited to implement a logarithmic voltage-to-time converter and an exponential time-to-voltage converter. These circuits are the time domain analogs of the voltage mode translinear circuits that exploit the exponential relationship between current and voltage in BJTs and subthreshold MOS transistors. Just as Kirchoff's voltage laws provide a natural form of addition for the voltage-mode translinear principle, the progression of time can also be a natural source of addition for the proposed time-mode analog of this principle. In this work a time-mode adder circuit is used to realize a translinear principle in time. This paper describes the theory behind this time-mode translinear principle. Furthermore, the design of nonlinear circuit functions, e.g., multiplication and power law, based on the time-mode translinear principle is described. Simulation and measurement results for a two-input single quadrant multiplier are presented. The chip was fabricated in a 180 nm CMOS process with simulation results agreeing closely with experimental results. We also present error analysis for such circuits and provide a brief discussion on future prospects of this approach.
Voltage-mode filters and especially their linearity and dynamic range suffer from the low supply voltages of deep-sub-micron and nanometer CMOS. This fact served as motivation to investigate current-mode filters with the hope for a better linearity and larger dynamic range. Current-mode filters also may allow saving of current-to-voltage and voltage-to-current converters compared to the case when voltage mode filters are used in combination with current-mode mixer and current-steering digital-analog converter for instance. A lower power consumption then should be obtainable. This chapter will give on overview on current-mode filters described in literature and will introduce new current-mode filters designed in 120 nm CMOS and 65 nm low-power CMOS. Their properties are described in detail.
Analog filters are required in many mixed-signal systems. They can be used for anti-aliasing purposes, before signals are sampled in an A/D converter or they can be used for reconstructing the signal after a D/A converter. Also at the output of a mixer a filter which suppresses out-of-band interferer signals is necessary. In general, when a filter is designed it is necessary to consider the whole system in which the filter is embedded. Important parameters for filters are in-band and also out-of-band distortions. A high in-band linear dynamic range avoids intermodulation between two in-band signals. Out-of-band distortions are also essential because they describe the immunity against some blockers or disturbances to other channels in a multi-band system. Other important parameters are the noise spectral density or the integrated noise. For some applications the out-of-band spectral noise density should be under a certain level, otherwise the noise would interfere to a neighboring channel. Sometimes, when the same filter is used in the I-path and in the Q-path of a receiver, the mismatch between these two filters should not be too high. Gm -C filter topologies, a figure of merit, the state-of-art, the requirements for UWB and three implemented filters are described in this chapter.
A fourth-order Butterworth band-pass filter whose Q value is greater than 10 implemented in nanoscale CMOS process, is presented. The center frequency can be switched by an external switch. The filter integrates a Q-tuning scheme and a frequency tuning scheme. The Q-tuning
scheme has a high accuracy based on the LMS algorithm. The basic block OTA in the filter takes advantage of the dynamic source degeneration technique, which could improve the input linearity range. The pass bandwidth is 260 kHz, the adjacent channel rejection is greater than 30 dB, and the
max power consumption is only 7.9 mW.
A novel and versatile implementation for analog defuzzification with fixed singleton coefficients is introduced. It is based on differential pairs with multiple input floating gate transistors and on Gilbert translinear cells. The singleton coefficients are determined by relative capacitance values. Experimental results of a breadboard prototype that verify the proposed scheme are shown.
Analog computation traditionally processes information as differences in voltage or current amplitudes. With technology scaling resulting in reduced headroom and limited dynamic range, time-mode computation has emerged as a viable approach for low-power high-precision analog signal processing. Time mode circuits use differences in time to represent information. So far, only linear relationships between voltage/current and time has been explored for applications in data conversion, frequency synthesis and signal processing. In this paper, we present a time-mode analog of the well-known “translinear” principle using linear RC circuits and exploiting the exponential relationship between voltage and time for step charging or discharging of the capacitor. We present basic circuit analysis and utilize the technique to implement a simple single quadrant analog multiplier in an 180nm CMOS process. At 1.8V supply, the multiplier consumes approximately 5mW for a sampling frequency of 100kHz and a maximum input peak-to-peak voltage swing of 0.8V. The average non-linearity error is 0.44%. The time mode translinear principle could facilitate high dynamic range, high precision, complex linear and nonlinear arithmetic and other signal processing functions.
A 10 Gb/s analog continuous-time equalizer with integrated clock and data recovery circuit is presented. It is designed to recover signals degraded by chromatic and polarization mode dispersion. The key components in the design are a feedforward equalizer and a decision feedback equalizer, the parameters of which are electronically adjustable. Both circuit blocks are fully described and characterized with emphasis on minimizing self-induced distortion and maximizing high-speed performance. In addition to the equalizer and the clock and data recovery, the circuit also includes an integrated automatic gain control. The circuit is implemented in a commercial 0.18 μm SiGeBiCMOS technology and consumes 900 mW. The capacity of the equalizer to mitigate signal impairments is demonstrated using three electrically generated channels.
An ion-sensitive field effect transistor (ISFET) based chemical Gilbert cell is presented, capable of differential measurement of pH signals during thermocycling reactions. The proposed circuit is capable of measuring the difference between two reaction chambers allowing stable drift reduction. Implemented in a typical 0.35 μm CMOS process, the resulting topology has a tunable gain of up to 40 dB, is temperature stable, with a variation of just 0.7% within the range of 0 to 100°C and achieves a low power consumption of 198 nW.
This paper presents the trade-off between surface, biasing current and performance of an analog turbo decoder. It is shown that the biasing current and the parasitic emitter resistor can deteriorate the performance of a decoder. The parasitic emitter resistor depends on the emitter area and the biasing current depends on the maximum decoding speed required. Simulations show that the parasitic emitter resistor can deteriorate the performance by 0.35 dB for BER of 10-2 for a 0.25-mum process from NXP. It is also shown that an increase of seven percent of the size of the transistor can divide the emitter resistor by four and thus reduces the deterioration of performance to 0.05 dB. In the same way, reducing the biasing current improves the performance but reduces the maximum decoding speed.
This paper presents a single low-voltage CMOS analog multiplier with low-power consumption. It consists of four voltage adders and a multiplier core. The proposed circuit is simulated with HSPICE and simulation results have shown that, under single 0.9V supply voltage, the circuit has smaller than 1.8% linearity error and 0.88% THD under the maximum-scale input 400mVp-p at both inputs. The quiescent power consumption is 58μW and the -3dB bandwidth is 70MHz.
This paper presents the results of a study directed toward understanding the basic distortion mechanisms in transistors, (i) We develop an analytic model for the transistor which describes small signal linear performance and nonlinear effects. The linear model is matched to the measured h-parameters of the device over a wide range of frequency and bias current. We superimpose three distinct nonlinear effects on this linear skeleton model, all approximated to third order terms, (ii) We show experimental confirmation that, for some bias-load conditions, the second order distortion can be minimized and we show that it is possible to simultaneously minimize both second- and third-order distortion under the same bias-load condition. This result also is confirmed experimentally, (iii) We derive and discuss in detail an analytic expression for the optimum load. Based on this expression, we present detailed procedures for finding this optimum condition for any transistor, and give experimental corroboration, (iv) We give a qualitative description of the interaction among these three nonlinear effects based on an analog computer simulation of the model. This description makes it easier to visualize the distortion cancellation phenomena derived in this paper, and indicates a technique for extending the effect to a broad band of frequencies. We conclude that proper use of the distortion cancellation effect can greatly improve intermodulation performance in existing transistors.
By the method described, the voltage gain of a transistor amplifier is made insensitive to transistor gm variations.
The current flowing in a semiconductor junction may be divided into four components according to the location of the recombination and generation of electrons and holes. These are: 1) the bulk recombination-generation or the diffusion current, 2) the bulk recombination-generation current in the transition region, 3) the surface recombination-generation current in the transition region, and 4) the surface channel current. The current-voltage relationship for these four current components may be approximated by I = I_{s} exp (qV/mkT) , if V > 4kT/q . Analysis shows that the reciprocal slope m for the current components 1) to 3) lies between 1 and 2, while for the surface channel current component 4) m is greater than 2 for silicon junctions and may be more than 4 for large channels. The theoretical expressions for these four current components are tested with extensive experimental data taken on silicon junctions and found to account for all of the observed current-voltage characteristics. The importance of surface recombinations and surface channels on the current gain of silicon transistor is also demonstrated experimentally. The experimental data are in accord with the theoretical prediction based on the transistor current equations which include the carrier recombination in the emitter junction and the carrier generation in the collector junction.
First Page of the Article
This paper describes a technique for the design of two-signal four-quadrant multipliers, linear on both inputs and useful from dc to an upper frequency very close to the ft of the transistors comprising the circuit. The precision of the product is shown to be limited primarily by the matching of the transistors, particularly with reference to emitter-junction areas. Expressions are derived for the nonlineafities due to various causes. Copyright © 1968 by The Institute of Electrical and Electronics Engineers, Inc.
An integrated bridge network of four transistors is used as a self-neutralized active element in tuned RLC amplifier designs. The bridge network compensates for the transistor collector-base junction capacitance (C/SUB c/), yielding a 95-percent reduction in the common-emitter reverse transmission admittance. IF amplifier stages that achieve the maximum unilateral power gain of a common-emitter transistor while maintaining excellent alignability are realized using the C/SUB c/ compensated transistor structure. Variations of the relative bias current levels of the transistors in the bridge network provides gain control by way of signal cancellation. This technique produces minimal frequency response variations of the amplifier stage being controlled. A noise analysis shows output signal to noise ratio at maximum attenuation can be a performance limitation.
A direct-coupled monolithic IF amplifier that incorporates an active gain control stage and exhibits a power gain of 50 dB and an AGC range of 60 dB at 50 MHz is described. This circuit has negligible change in either input or output admittance, and has excellent signal linearity over the full range of gain control. Experimental and theoretical analyses are made of the large signal response, stability, available gain, and noise behavior of the circuit. An application to color television is discussed in which the functions of the 45-MHz IF amplifier and the dc-AGC circuitry are fabricated on a single die.
Intermodulation in common-emitter transistor amplifiers
- A E Hilling
- S K Salmon
Broadband amplifiers" in Amplifier Handbook
- J S Brownin
Dual output synchronous detector utilizing transistorized differential amplifiers
- H E Jones
U.H.F. broadband transistor amplifiers
- L F Roeshot
- Edn Mag
Broadband amplifiers
- J S Brown