A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speed wireless applications [LANs]

Abstract

A DS-CDMA demodulator uses analog sampled-data signal processing
to achieve a 75-mW power dissipation and a 128-MS/s processing rate in a
1.2-μm double-metal double-poly CMOS process. To demodulate the
signal, a low-power passive correlation technique is introduced that
eliminates the integrating opamp with its associated power and settling
time overhead. In a prototype demodulator, six 64-chip correlators
recover the 2-Mb/s data stream from the doubly modulated [pseudorandom
noise (PN) and Walsh] quadrature input signal. An on-chip 10-b pipelined
ADC sampling at 8 MS/s follows the analog correlation to permit digital
implementation of the acquisition and tracking algorithms

Full text

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998 753
A 75-mW 128-MHz DS-CDMA Baseband
Demodulator for High-Speed Wireless Applications
Keith K. Onodera and Paul R. Gray, Fellow, IEEE
Abstract—A DS-CDMA demodulator uses analog sampled-data
signal processing to achieve a 75-mW power dissipation and a
128-MS/s processing rate in a 1.2-
m double-metal double-poly
CMOS process. To demodulate the signal, a low-power passive
correlation technique is introduced that eliminates the integrating
opamp with its associated power and settling time overhead. In
a prototype demodulator, six 64-chip correlators recover the 2-
Mb/s data stream from the doubly modulated [pseudorandom
noise (PN) and Walsh] quadrature input signal. An on-chip 10-b
pipelined ADC sampling at 8 MS/s follows the analog correlation
to permit digital implementation of the acquisition and tracking
algorithms.
Index Terms—CMOS analog integrated circuits, code division
multiaccess, correlators, direct sequence spread spectrum, passive
circuits, passive correlator, pseudonoise coded communication,
sampled data filters, spread spectrum communication, switched
capacitor circuits, wireless LAN.
I. INTRODUCTION
D
IRECT sequence code division multiple access (DS-
CDMA) has been successfully applied to many low
bandwidth wireless applications, such as cellular phones [1]
and GPS systems [2]. In recovering the information for these
systems, the baseband received signal can be directly sampled
by an analog-to-digital converter (ADC) allowing DS-CDMA
demodulation in the digital domain. At these conversion
rates of less than 10 MS/s, low-power CMOS ADC’s are
realizable, permitting low-cost, high-integration solutions for
these portable wireless applications [3].
It is desirable to extend the benefits of DS-CDMA (mul-
tiuser access, spectrum-fade resistance, and noise rejection
[4]) to higher speed wireless applications such as wireless
local area networks (WLAN). To obtain these benefits, DS-
CDMA requires expanding or “spreading” the data spectrum
by one to two orders of magnitude using modulation by a
pseudorandom noise (PN) sequence. Thus, with data rates in
the 1–10 Mb/s range, DS-CDMA modulated bandwidths are
tens and hundreds of megahertz for WLAN applications. To
digitize these signals requires Nyquist sampling rates in excess
of 100 MS/s by an ADC whose power may impact the battery
life of a portable system [5].
An alternative approach would be to avoid the power
consumption of a high-speed ADC and to perform the de-
modulation in the analog domain. Then, if needed, a slower
Manuscript received September 1997; revised December 11, 1997.
The authors are with the Department of Electrical Engineering and Com-
puter Sciences, University of California at Berkeley, Berkeley, CA 94720
USA.
Publisher Item Identifier S 0018-9200(98)02232-X.
ADC can follow the analog demodulator leading perhaps
to a lower power solution since the recovered signal has
a lower bandwidth. Typically, analog demodulation of DS-
CDMA signals is implemented using transversal or finite
impulse response (FIR) filters with a PN sequence used
as the tap weights. This can be viewed equivalently as a
correlation of the incoming received signal with the PN
sequence. CMOS switched-capacitor circuits (SC), charge-
coupled devices (CCD), and surface-acoustic wave (SAW)
technologies are all viable solutions for this task. While SAW
devices are suitable for high-frequency operation [6], digital
CMOS compatible solutions are preferable for reasons of high
integration and thus lower costs. CCD devices can be added
to a CMOS process but require high-voltage clocking [7] and
tend to yield a higher cost and power implementation than an
SC realization in a standard CMOS process. The performance
attainable in a CMOS SC correlator has been demonstrated
in [8] and [9], which describe DS-CDMA demodulators that
operate at 25 and 50 MHz, while dissipating 110 and 170
mW, respectively.
This paper seeks to extend the performance of these SC ap-
proaches by considering different circuit topologies to increase
the speed while minimizing the power. To demonstrate this
approach, a prototype demodulator integrated circuit (IC) is
presented that operates at 128 MS/s on a 64-MHz DS-CDMA
baseband signal while dissipating 75 mW. The remainder
of the paper is organized into six sections. Section II gives
an overview of DS-CDMA modulation and describes how
correlation is used in demodulation. Section III presents a
comparison of different correlation approaches and introduces
a passive correlation technique. In Section IV design consid-
erations for the passive correlation structure are discussed.
Section V describes the architecture of the prototype DS-
CDMA baseband recovery chip using six passive correla-
tors. Section VI presents experimental measurements, and
Section VII concludes with a summary of the paper.
II. DS-CDMA S
YSTEM OVERVIEW
In the transmitter of a DS-CDMA system (see Fig. 1),
the serial data bit stream modulates a PN sequence code.
Because of the random nature and high frequency content
of the PN code, the resulting modulated data spectrum is
spectrally flat and much wider in bandwidth. One benefit to
spreading the signal in frequency is that a wider bandwidth
signal is less susceptible to degradation from spectrum nulls or
fades. Another benefit is the rejection of interfering signals by
the demodulation process which reduces the interfering signal
0018–9200/98$10.00  1998 IEEE

754 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998
(a) (b)
Fig. 1. Wireless DS-CDMA system: (a) modulator and (b) demodulator.
(a)
(b)
Fig. 2. (a) Direct sequence modulation process and (b) demodulation process
using discrete-time correlation.
power by the spectrum expansion factor. This expansion factor
is known as the processing gain (
) and is defined as
(1)
where
and are the modulated and unmod-
ulated bandwidths of the data signal. A third benefit is the
reduction of any random noise by the averaging process of
the demodulator’s integration step. In a DS-CDMA receiver,
demodulation is accomplished by performing a correlation
between the received signal and the PN code, i.e., multiplying
the received signal by the PN code and integrating this product.
Fig. 2(a) shows a more detailed view of the modulation
process. DS-CDMA modulation results in a mapping of “1”
data bits to one polarity of the PN code and of “0” data bits
to the opposite polarity. For a PN code that is
bits long,
the resulting modulated spectrum is
times wider than the
original data spectrum thus
is equal to . By convention,
the unmodulated bit rate is called the data rate and the PN
modulated bit rate is called the chip rate. Correspondingly, a
(a)
(b)
Fig. 3. (a) Digital and (b) analog correlation alternatives.
Fig. 4. PN modulation: sample input and modulate polarity with PN code.
data bit time ( ) and a chip time ( ) are the periods of
their respective rates.
In sampled-data systems, the demodulation process is ac-
complished by performing a discrete-time correlation of the
baseband receive signal with the PN code [see Fig. 2(b)]. This
discrete-time correlation (
) is defined as
(2)
where
are the chip-rate sampled values of the received
input signal,
are the PN code bits, and is length
of a data bit in chips. If the input samples and PN code bits
are normalized to 1, the output of the correlation equals
when the two signals are in-phase and when they are
out-of-phase. Thus, the original data bits are contained in the
sign of the correlation output and not in the magnitude, thus
permitting data recovery by employing a simple slicer.
III. C
ORRELATOR IMPLEMENTATIONS
To summarize the correlation process, samples of the re-
ceived input signal are taken at the chip rate, multiplied by PN
code bits, and summed to produce a demodulated output bit
every
chip samples, that is, at the data rate. Fig. 3 compares
how this correlation would be implemented in the digital and
analog domains. From this figure, the decision to select the
analog architecture as the lower power choice is based on
avoiding the power consumption required by a front-end ADC
sampling at the chip rate (
). Three possible approaches for
implementing an analog correlator are considered next.
A. Active Chip-Rate Correlation
The first step in performing the analog correlation is the
PN code modulation, or multiplying the input sample with

ONODERA AND GRAY: 75-mW 128-MHz DS-CDMA BASEBAND DEMODULATOR 755
(a) (b)
(c)
Fig. 5. Analog discrete-time integration methods. (a) Samples are integrated at the chip rate by the opamp, (b) samples are captured successively by sampling
array and integrated at the data rate by the opamp, and (c) sampling array is integrated passively at the data rate.
the PN code. The PN code values are , so PN code
multiplication is simply sign modulation of the input samples
prior to integration/summation. This is accomplished by using
fully differential circuits and cross-connecting MOS switches
as shown in Fig. 4.
The next step is to integrate the sign-modulated input sam-
ples via a discrete-time summation. The first analog correlation
architecture considered is the sampled-data integrator shown
in Fig. 5(a). For simplicity and clarity, the PN modulation
switches are omitted and a single-ended representation is used.
In this approach, the circuit operates at the chip rate to take
a sample, sign modulate it, and integrate it. After
samples
are processed, the correlation result is sampled, the integrating
capacitor (
) is reset, and the next data bit is processed. Since
the opamp must integrate each sample in one chip time, its
settling time must be very fast and hence its static power will
be large, contradicting the low-power goal.
B. Active Data Rate Correlation
In the previous architecture, even though the input sampling
and integration is being done at the chip rate, the output is
being sampled
times slower at the data rate. This next
architecture takes advantage of that fact to trade area for power
[see Fig. 5(b)]. Instead of having one sampling capacitor
,
there are two banks of
sampling capacitors. For a given data
bit, the
successive input samples are stored sequentially
on the
capacitors of one bank so that input sampling can
still be performed at the chip rate. After all
samples are
taken, the opamp and integrating capacitor are connected to
the bank to perform the integration of the
samples. While
one bank is sampling the input, the other bank is integrating
its samples. In this architecture, the opamp has a data-bit time
to settle rather than a chip time, therefore it can be
times
slower and dissipate roughly
times less static power than
the previous architecture.
C. Passive Data Rate Correlation
In the prior implementations, the integration is accomplished
by transferring the charge on the sampling capacitor(s) to
an integrating capacitor using an opamp to do the charge
transfer. If the integrating capacitor is eliminated by having the
sampling array double as an integrating array, then no opamp
is needed to transfer the charge [see Fig. 5(c)]. After all the
samples have been modulated, the correlation is completed by
connecting the
capacitors to one another, thus performing
a passive charge integration. Two banks of
sampling
capacitors each are still needed to interleave sampling and
integrating, but no active element is needed. This eliminates
all static power and provides a purely dynamic power solution.
Another benefit of eliminating the opamp is that the inte-
gration settling time is no longer dependent on the opamp’s
unity-gain bandwidth. Instead, the settling time constant is
(3)
where
is the on-resistance of the integration switch. Since
can be designed to be shorter than an opamp’s settling time,
the passive integration settling time is faster. With the lowest
power and the fastest settling time, this architecture is the most
suitable choice for the analog correlator.
IV. D
ESIGN CONSIDERATIONS
Before the passive integration scheme can be implemented,
a few design issues must be addressed. Two issues are related
to the absence of an opamp. The first is charge error on the
summing-node due to parasitic capacitance, and the second is
the gain of the passive integrator which is less than unity and
parasitic sensitive. These as well as the more general issues
of capacitor matching, parasitic capacitance nonlinearity, and
sampling noise are considered next.

756 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998
(a)
(b)
Fig. 6. (a) Detailed view of a differential sampling cell and (b) sampling
cell timing diagram.
A. Charge Error Cancellation
In a switched-capacitor sampling circuit, charge errors can
be caused by switch charge injection, clock feedthrough,
and charge transfer on parasitic capacitances. The first two
errors can be solved by using bottom-plate sampling and fully
differential circuitry [10]. Using an opamp can eliminate the
charge transfer error that occurs on its summing, or feedback,
node. The opamp accomplishes this by forcing the summing
node to virtual ground during the integration period, thus
backing out any charge that was deposited during the sampling
phase.
The passive integration technique also uses bottom-plate
sampling and fully differential circuitry to eliminate charge
injection and clock feedthrough errors. However, without an
opamp, charge transferred onto the summing node is no longer
automatically cancelled. Fig. 6(a) gives a detailed view of a
passive sampling cell along with its interconnection to form
one bank of a correlator. The charge error gets stored on the
parasitic capacitances (
) at the summing node. includes
the bottom-plate parasitic capacitance of
, the diffusion
capacitances of the switches, and the trace capacitances of
the metal lines. The charge error cancellation process needed
for passive integration proceeds as follows.
Initially the bottom-plate sampling switches (
) and input
switches (
) are closed connecting the sampling capacitor to
the input bus [Fig. 7(a)]. To capture a sample, the
switches
are opened injecting common-mode charge onto
, which
creates no error [Fig. 7(b)]. Next the sampling capacitors are
(a) (b)
(c) (d)
(e)
Fig. 7. Error-free passive integration: (a) the input is connected to the sam-
pling capacitors, (b) an input sample is captured on the sampling capacitors,
(c)
is disconnected from the input but error charge is injected onto ,
(d)
momentarily closes, cancelling the error charge on , and (e) the
input sample is integrated without charge error.
disconnected from the input bus by opening the switches
[Fig. 7(c)]. This creates two sources of charge error: the first
is from the signal-dependent charge injection from the
switches onto ; and the second occurs as a result of input
signal changes after
opens and before can disconnect
from the input bus. Normally, to integrate the signal charge
on
, the switches and the integrate ( or ) switches
would be closed [Fig. 7(e)], but this would include the charge
error in the integration process, corrupting the signal. So
the error must first be eliminated before proceeding with the
integration. This is accomplished by adding a switch (
)to
the cell along with a “zeroing” step prior to the integration step
[Fig. 7(d)]. In this step, the
switch is momentarily closed
converting the differential charge on
to a common-mode
charge effectively eliminating it. Now the integration step can
proceed error free.
B. Passive Correlator Gain
Without an active element, the gain of the passive correlator
is less than unity. Since only the sampling capacitor
holds

ONODERA AND GRAY: 75-mW 128-MHz DS-CDMA BASEBAND DEMODULATOR 757
the signal charge, charge sharing results in a gain equal to
(4)
where
is the sum of all the per-cell parasitic capac-
itance. Besides
, the next biggest component of
is the output bus capacitance per cell. The gain varies with
process to the extent that
and do not track.
However, for any particular device, the gain is fixed so it may
be possible to add a calibration step to achieve a well-defined
gain. As mentioned previously, in DS-CDMA demodulation
the exact magnitude of the correlation is not important, so
gain calibration was not pursued.
C. Capacitance Matching
A mismatch between the sampling capacitors
and
within a cell create a fixed skew that imparts an offset in the
sampled charge that is to be integrated. With good layout,
this skew will be random and the offset of all the cells of
one correlator will have zero mean. It is not hard to keep the
mismatch to less than 1% which will limit this noise power to
40 dB referred to the input. Via the correlation process, this
noise power will be further reduced by the averaging process
so it should not be significant. However, if the layout is such
that there is a systematic skew, the cell offsets will have a
nonzero mean in addition to the random mismatch component.
In the PN modulation of the correlation process, this nonzero
mean will be randomized and contribute an additional noise
power component. This could be much larger than the random
mismatch component and degrade the SNR. However, this
noise power will also be reduced by the averaging process
which will lessen its impact.
As a result of the parasitic sensitivity of the passive cor-
relator’s gain, matching of
and is also important.
Since
should be smaller than , its mismatch impact is
lessened by a factor equal to their ratio,
, but attention
to parasitic layout can be easily overlooked and impact the
SNR negatively.
D. Parasitic Nonlinear Capacitance
The nonlinearity of the source and drain diffusion junction
capacitances associated with the transistor switches can intro-
duce errors in the sampling process that generate an extra noise
component to the correlation process. To minimize this effect,
the sampling capacitor can be increased and/or the switch sizes
decreased. Doing either of these increases the settling time
constant (
) so there is a tradeoff between operating bandwidth
and nonlinearity error. For the experimental prototype, the
smallest switch sizes (
) were used to
minimize the power while the largest sampling capacitors
(
fF) were used that still permitted 128-MHz
operation. This resulted in a nonlinearity error of less than
1% over the maximum input voltage range.
E.
Noise
Noise power of a single sample due to sampling the thermal
noise of the input (
) switches is
(5)
Fig. 8. DS-CDMA demodulator block diagram.
where Boltzmann’s constant, temperature in Kelvin,
and
the sampling capacitance. This noise is also reduced
by
so the postcorrelation noise power ( )is
(6)
This is equivalent to the
noise of a capacitor equal to
times , that is, the whole sampling array. As can be
large,
noise should not dictate the minimum sampling
capacitor size.
V. DS-CDMA P
ROTOTYPE BASEBAND RECEIVER
To demonstrate the high-speed and low-power performance
of an analog correlation approach, a full DS-CDMA baseband
recovery prototype IC was designed, fabricated, and tested. It
was defined as part of a low-power wireless LAN subsystem
for an indoor portable pen-based terminal system [11]. Fig. 8
is a block diagram of the prototype IC which incorporates six
passive correlators, a 16-stage PN code generator, a 256-MHz
digital phase shifter (DPS), a 6-to-1 multiplexer/buffer, and a
10-bit pipelined ADC. The device is designed to process both
in-phase and quadrature (
and ) signals at 1 Mb/s each
to accommodate quadrature phase shift keying (QPSK)-type
modulations yielding an aggregate data rate of 2 Mb/s. In each
signal path (
and ), there are three correlators—Early, Late,
and Data—which are arrayed in the standard delay-locked loop
(DLL) configuration for synchronization and demodulation
[2]. Walsh function modulation is combined with PN code
modulation to create a 64-dimensional code space to allow up
to 64 channels in a base-station-type configuration similar to
the type used in the cellular phone industry [1]. One of the
channels is reserved for sending a pilot tone that is used for
synchronization in the receiver.
A. PN and Walsh Modulation
The wireless LAN subsystem is designed as a multiple
access system providing 2-Mb/s data streams per user. Each
user’s data stream is multiplexed into two 1-Mb/s data streams
for QPSK-type RF modulation. In order to accommodate
up to 50 users in an indoor cellular area, the system was
designed to use a spreading factor (
) of 64 which results
in 64 Mchips/s DS-CDMA modulated data streams. There
are only four different PN sequences for a spread factor
of length 64, allowing only four different users [12]. Gold

758 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998
codes can be generated to provide enough distinct codes,
but a better solution is to leverage the fact that the base-
station configuration can synchronously transmit the users’
data. Thus, using Walsh functions to modulate the users’
data not only yields 64 distinct codes but also makes the
transmitted modulated signals mutually orthogonal owing to
the “synchronously orthogonal” nature of Walsh functions.
The “whitening” and near-ideal autocorrelation property of
the PN code is still necessary for successful phase acquisition
and tracking, so a second modulation by a long PN sequence
is used. The PN code is 32768 chips which is longer than
the 64-chip data bit so the PN code recycles every 512 data
bits. This longer PN code allows improving the processing
gain (
) of the acquisition and tracking correlation upwards
to 45 dB by increasing their correlation lengths if more
robust synchronization is desired. Of course, longer tracking
correlations mean infrequent timing updates that can be a
problem due to the drift of the timing reference signal. The
system is set to perform 896-chip acquisition and tracking
correlations (
dB). Correlations of this length are
short enough not to cause timing drift problems nor to prolong
acquisition times, and were long enough to provide good
resistance to adjacent cell interference according to system
simulations [13]. Since a data bit is 64 chips long, data
demodulation is a 64-chip correlation (
dB).
B. Synchronization and Demodulation
Before demodulation can proceed, the internal IC’s PN
sequence must be aligned, or synchronized, to the same
sequence embedded in the incoming received signal. This is
accomplished by first acquiring a coarse open-loop alignment
and then closing a feedback loop to track and maintain the
alignment. The acquisition and tracking use two correlators
denoted as Early and Late, while the demodulation uses one
correlator denoted as Data.
Acquisition is performed as a straightforward sequential
search through all possible chip phases commonly known
as “sliding correlation.” Both the Early and Late correlators
are used so two phase alignments can be checked on each
pass cutting the search time in half. When a correlation
peak from either of the two correlators is detected, the clock
phase is locked and the tracking mode is entered. In this
implementation with a PN sequence of 32768 chips and 128
MS/s sampling rate, the average acquisition time is 131 ms.
In the DLL architecture used for tracking, the Early corre-
lator samples the input 1/2 chip time (
) ahead of the Data
correlator, and the Late correlator samples 1/2
behind it
yielding an aggregate 128 MS/s sampling rate. The feedback
of the DLL maintains alignment by keeping the magnitudes
of the Early and Late correlations equal thus ensuring that the
Data correlation is being sampled at the correlation peak for
the highest SNR.
A 10-bit pipelined ADC is used to digitize the six correlator
outputs allowing digital implementations of the acquisition and
tracking algorithms. Since the output rate of each correlator is
1 MHz, the ADC has to sample at 6 MS/s or higher, so 8 MS/s
was chosen to simplify multiplexing and clock generation.
Fig. 9. Prototype die photo.
The ADC is fed by a 6-to-1 multiplexer (MUX)/variable gain
amplifier (VGA) block. Since each correlator is configured
as two interleaved (sample/integrate) banks, the overall MUX
is 12-to-1 and is split into two stages—12-to-3 and 3-to-
1, preceding and following three VGA’s. The second MUX
stage is actually 4-to-1 with an extra zero-volt input added
to calibrate any ADC offset. Three VGA’s are used rather
than one VGA running three times faster to lower the power
dissipation since power is a square function of frequency.
Due to the need for relative gain accuracy in the Early/Late
correlation, no more than three VGA’s can be used. Thus,
-channel Early/Late correlators share one VGA as do the
-channel Early/Late and the Data correlators.
The ADC buffered outputs are connected to an off-chip
field-programmable gate array (FPGA) that implements the
synchronization circuitry. Using an FPGA allows for testing of
various acquisition and tracking routines. The DLL feedback
is closed by signals generated by the FPGA and applied to the
three inputs of the on-chip digital phase shifter (DPS) block.
The “delay2
” signal is used during acquisition to cause a
two
delay of the on-chip PN generator. The “up” and
“shift” signals are used during tracking to advance/retard and
enable/disable 1/4
shifts, respectively. These inputs are
sampled every 1024 chips, which translates to a 16-ms update
period for both acquisition and tracking.
VI. E
XPERIMENTAL RESULTS
The prototype chip was fabricated in a standard 1.2- m
CMOS double-metal double-poly process. Fig. 9 is a die
photo of the prototype DS-CDMA demodulator IC. The six
correlators and the PN generator make up the large dense block
on the left of the photo. The PN generator runs in a horizontal
row between the upper bank (1/2 of all six correlators) and the
lower bank. All correlators run horizontally and are composed
of 64 sampling cells. The 10-bit pipelined ADC is the large
block on the right. The MUX/VGA block is the thin column
between the correlators and the ADC. The
and input pads
feed the correlators from the left and the digital outputs from
the ADC are provided on the lower right pads. The die size is
9.3 mm
4.5 mm (366 mils 177 mils).
The test setup uses an arbitrary waveform generator (Tek
AWG2020) to create the desired DS-CDMA baseband input
signal. A 256 MHz external clock source is used for both the

ONODERA AND GRAY: 75-mW 128-MHz DS-CDMA BASEBAND DEMODULATOR 759
Fig. 10. Example of correlation peak from Early and Late correlators during
acquisition.
Fig. 11. Frequency response of Data correlator.
AWG2020 and the prototype IC for synchronous operation.
The digital output is sampled by a logic analyzer (HP16500B)
with a 1
-word memory and then downloaded to a computer
for plotting and data reduction.
Fig. 10 is a plot of the Early and Late correlator outputs
during acquisition using a 896-chip correlation. When the
acquisition routine detects the peak, it will close the DLL
feedback to lock on to this chip alignment and enter tracking
mode. The side skirts are larger than an ideal autocorrelation
due to using partial PN sequences lengths (896 instead of
32767 chips).
Fig. 11 is a plot of the frequency response of the Data
correlator. The response was flat up to the operating frequency
limit of the signal generator. The measured gain is about 0.72
(
2.85 dB) which agrees well with the calculated value of 0.73
(
fF fF) from design model values. The
linear behavior of the Data correlator is illustrated in Fig. 12
which is a plot of its transfer function for 1- and 128-MHz
operation.
Fig. 13 shows the measured output SNR of the Data cor-
relator versus the input signal level in decibels referenced
Fig. 12. Transfer function of Data correlator.
Fig. 13. Data correlator output SNR comparison: analog correlator (mea-
sured) versus ideal digital correlator (calculated).
to a 1.5-V peak input. Calculated output SNR curves of an
ideal digital correlator with a front-end ADC of 7, 8, and 9
bits of resolution are also plotted. For the digital correlator,
only quantization noise was included assuming the same full-
scale voltage range of the analog correlator input (±3.0 V).
This figure shows that the analog correlator has a performance
similar to that of an ideal digital correlator with a resolution
between 7 and 8 bits.
A breakdown of the power consumption for the prototype
IC is shown in Table I. According to Table I, the dynamic
power makes up 81% of the total power. Thus, the overall
power will benefit from supply voltage scaling. The correlators
themselves only consume 4 mW each to run (this includes all
clock power to sequence the switches). The overhead control
logic (PN Gen, DPS, and MUX) is pure digital logic and
consumes 33 mW so its power would scale as
.If
the overhead logic is included, the correlators require 9.5
mW each to operate at 128 MS/s. This compares to 5.3 mW
per correlator extrapolated to 128 MS/s for a similar digital
correlator [11] and represents only a 25-mW power difference
for a six-correlator implementation. The 10-bit ADC requires
only 12 mW to operate when sampling at 8 MS/s.
To implement an equivalent DS-CDMA demodulator in the
digital domain would require two ADC’s operating at 128
MS/s each. To match the performance of the analog correlator,
these ADC’s need 7–8 bits of resolution. Table II is a list

760 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 5, MAY 1998
TABLE I
P
OWER CONSUMPTION
TABLE II
H
IGH-SPEED ADC’S
of high-speed ADC’s that are suitable for this comparison.
Using the fact that a six-correlator analog block is only 25
mW more than an equivalent digital one, a power comparison
can be made based solely on the ADC(s) required by each
approach. From Table II, the 12-mW postcorrelation ADC is
about two orders of magnitude lower power than the precorre-
lation ADC’s required by the digital approach. If CMOS-only
implementations are considered, the power difference is even
larger.
VII. C
ONCLUSIONS
This paper has shown that by using analog signal pro-
cessing prior to the analog-to-digital conversion, a lower
power implementation can be realized by easing the speed
requirements of an ADC in high-speed applications such
as a wireless LAN system. To minimize the power of the
correlation function needed for DS-CDMA demodulation,
a passive integration scheme has been used. The passive
correlator requires no operational amplifier and thus eliminates
the opamp’s static power and bandwidth limitation to settling
time. An additional “zeroing” switch is incorporated into
the switching sequence of a bottom-plate fully differential
sampling circuit to eliminate signal-dependent charge injection
present in the passive scheme.
A prototype DS-CDMA demodulator IC was fabricated
that operates at 128 MS/s to demodulate a pair (
and )
of 64 Mchips/s modulated baseband data streams. The SNR
performance of the analog correlator is measured to be better
than a digital correlator with a 7-bit ADC but with a power
dissipation of 75 mW. Comparing this to an equivalent digital
demodulator indicates that the two ADC’s required by the
digital approach could dissipate up to two orders of magnitude
more power than the ADC required in the prototype analog
architecture.
A
CKNOWLEDGMENT
The authors would like to thank Dr. C. Conroy and K. M.
Stone for their useful discussions and suggestions. They also
appreciate the contribution of Dr. T. Cho for help in integrating
his ADC design into this project. A special thanks to G. M.-Y.
Li and K. P. Halsey of National Semiconductor and P. Brown
of U.C. Berkeley for their help and support in the evaluation
of the prototype.
R
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ONODERA AND GRAY: 75-mW 128-MHz DS-CDMA BASEBAND DEMODULATOR 761
Keith K. Onodera received the B.S. degree from
Harvey Mudd College, Claremont, CA, in 1974
and the M.S.E.E. degree from Stanford University,
Stanford, CA, in 1976.
He worked at Precision Monolithics Inc. from
1977 to 1978 in the product and test engineering
groups. In 1978, he joined National Semiconductor
Corporation where he worked as an IC designer
and project leader specializing in analog circuits
for high-speed data communications systems. From
1990 to 1991, he was a Visiting Industrial Fellow
at the University of California, Berkeley. Since 1992, he has been pursuing
the Ph.D. degree at University of California, Berkeley in the area of high-
speed low-power analog circuit design while consulting part time at National
Semiconductor. He has also been a Teaching Assistant and Instructor for the
upper-division analog IC design course offered at University of California,
Berkeley. He is the holder of three U.S. patents based on his past circuit
designs.
Mr. Onodera was a member of the IEEE 802.3 task force that created the
10BaseT standard in 1990.
Paul R. Gray (S’65–M’69–SM’76–F’81) was born
in Jonesboro, AR, on December 8, 1942. He re-
ceived the B.S., M.S., and Ph.D. degrees from the
University of Arizona, Tucson, in 1963, 1965, and
1969, respectively.
In 1969, he joined the Research and Devel-
opment Laboratory, Fairchild Semiconductor, Palo
Alto, CA, where he was involved in the appli-
cation of new technologies for analog integrated
circuits, including power integrated circuits and
data conversion circuits. In 1971, he joined the
Department of Electrical Engineering and Computer Sciences, University of
California, Berkeley, as a Professor. His research interests during this period
have included bipolar and MOS circuit design, electro–thermal interactions
in integrated circuits, device modeling, telecommunications circuits, and
analog–digital interfaces in VLSI systems. He is the coauthor of a widely used
college textbook on analog integrated circuits. During year-long industrial
leaves of absence from Berkeley, he served as Project Manager for Telecom-
munications Filters at Intel Corporation, Santa Clara, CA, in 1977–1978, and
as Director of CMOS Design Engineering at Microlinear Corporation, San
Jose, CA, in 1984–1985. At Berkeley, he has held several administrative posts,
including Director of the Electronics Research Laboratory (1985–1986), Vice-
Chairman of the EECS Department for Computer Resources (1988–1990), and
Chairman of the Department of Electrical Engineering and Computer Sciences
(1990–1993). He is currently the Dean of the College of Engineering and is
the Roy W. Carlson Professor of Engineering.
Dr. Gray has been corecipient of best-paper awards at the International Solid
State Circuits Conference, the European Solid-State Circuits Conference, and
was corecipient of the IEEE R. W. G. Baker Prize in 1980, the IEEE Morris
K. Liebman Award in 1983, and the IEEE Circuits and Systems Society
Achievement Award in 1987. In 1994, he received the IEEE Solid-State
Circuits Award. He served as Editor of the IEEE J
OURNAL OF SOLID-STATE
CIRCUITS from 1977 through 1979, and as Program Chairman of the 1982
International Solid State Circuits Conference. He served as President of the
IEEE Solid-State Circuits Council from 1988 to 1990. He is a member of the
National Academy of Engineering.