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Performance of CMOS differential circuits
Abstract
Differential CMOS logic family has potential advantages over the
standard static CMOS logic family implemented using NAND/NOR logic.
These circuits tend to be faster and require fewer transistors. In this
paper, various static and dynamic circuit techniques from the
differential logic family are evaluated using application circuits like
adders and multipliers. Circuits with self-timed characteristics are
also considered. Evaluations are performed in terms of area, number of
transistors, and propagation delay. Results indicate that in general,
dynamic differential circuit techniques are faster than their
conventional static counterparts. Further improvement in circuit
performance can be achieved by choosing an appropriate differential
structure to match logic structure being implemented. Second, even
though the circuit techniques such as differential split-level perform
better, they may not be widely accepted mainly because of the increase
in circuit complexity and cost. Lastly, the self-timed dynamic
differential circuit techniques yield considerable improvement in speed
without having the problems of charge distribution or race conditions
typically associated with the conventional single-ended domino circuit
technique
... In silicon CMOS integrated circuits, differential logic families were introduced to improve the speed, the transfer characteristic, the common-mode noise immunity, and to reduce the input capacitance [27], [28]. Differential circuits offer logic flexibility and can be easily extended to self-timed and dynamic logic families [28]- [30]; moreover, by adding few components and a simple level shifter, a differential gate can be used as a single-input gate with differential outputs [28]. ...
... In silicon CMOS integrated circuits, differential logic families were introduced to improve the speed, the transfer characteristic, the common-mode noise immunity, and to reduce the input capacitance [27], [28]. Differential circuits offer logic flexibility and can be easily extended to self-timed and dynamic logic families [28]- [30]; moreover, by adding few components and a simple level shifter, a differential gate can be used as a single-input gate with differential outputs [28]. On the other hand, the differential logic leads to an area overhead of at least 30% compared to the single-ended logic. ...
... In silicon CMOS integrated circuits, differential logic families were introduced to improve the speed, the transfer characteristic, the common-mode noise immunity, and to reduce the input capacitance [27], [28]. Differential circuits offer logic flexibility and can be easily extended to self-timed and dynamic logic families [28]- [30]; moreover, by adding few components and a simple level shifter, a differential gate can be used as a single-input gate with differential outputs [28]. On the other hand, the differential logic leads to an area overhead of at least 30% compared to the single-ended logic. ...
A new unipolar differential logic (UDL) for the large-scale integration of amorphous In-Ga-Zn-O (aIGZO) digital circuits is proposed. Only single-threshold, single-gate, aIGZO thin-film transistors are required. The proposed UDL logic gates are very insensitive to the transistor parameters variations (i.e. threshold voltage, mobility, off-current, subthreshold slope) that are inherently due to the large-area low-temperature fabrication processes and to the operating conditions. To assess the UDL effectiveness, a wide range of parameters variations is considered: thanks to the proposed architecture up to 1.5 × 10 7 UDL gates can be integrated with a yield greater than 90%.
... Nowadays, integrated circuit (IC) is certainly the most applied technology in electronic products, being in a great majority represented by CMOS design styles [1][2][3]. Different CMOS logic families have been frequently proposed in the literature, including static and dynamic topologies, single-output and differential structures, multipleoutput gates, pass-transistor logic (PTL) approaches, and a large number of variations [4][5][6][7][8][9][10]. ...
... Simple AND-OR-INV (AOI) gates are sometimes treated, while more complex gates are barely mentioned. Other logic families, like PTL [9,10], dynamic domino [4,6], DCVSL [7,8], and others [1][2][3]5] are normally introduced by analyzing directly their electrical behavior, advantages and limitations, without paying much attention on the logic plane generation. ...
... Once switch networks have been well understood, these ones can be then combined to build logic gates. According to the strategies of connecting such networks and the eventual use of pre-fixed PU and/or PD circuitries, a large variety of logic families with particular electrical behavior (delay and power dissipation) are resulted [1][2][3][4][5][6][7][8][9][10]. At this stage of learning, the functionality of gates is no more the main issue, but instead the circuit voltages and currents relationship, which are strictly related to each type of topology. ...
Switch networks are the basis for digital electronic design regardless the current technology applied. However, such topic has not been deeply explored in CMOS integrated circuits due to particularities and electrical restrictions of CMOS gates, which concentrate in quite simple and basic functions. This paper proposes a new pedagogical way for learning logic gate design starting from switch network building. Next, different CMOS design styles are presented according to the network (logic planes) combinations, i.e., the gate topology. By doing so, such bottom-up acquiring of concepts focuses initially only on the functional behavior of switch arrangements, treating afterwards the gate topology and electrical characteristics associated to each logic family. An innovative CAD environment, called SwitchCraft, has been developed to assist such novel educational methodology.
... Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed. Most electronics running at over 2 GHz these days require the use of dynamic, although some manufacturers such as Intel have completely switched to static logic to save on power [8] . ...
... In general, dynamic logic greatly increases the number of transistors that are switching at any given time, which increases power consumption over static CMOS [8] . There is several power saving techniques that can be implemented in a dynamic logic based system. ...
... The implementation of AND/OR can be obtained by placing the NMOS stack in series and parallel connection, whereas the gates NAND/NOR can be implemented with De Morgan's law, an OR gate with inverted input signals behaves as a NAND gate. Similarly an AND gate with inverted input signals behaves as a NOR gate [8]. However, it is observed that the logic functionality refers to operations on -pulses‖ at inputs, and, if no pulses are present at the inputs, the outputs will remain at logic LOW state. ...
Self-resetting logic is a commonly used piece of circuitry that can be found in use with memory arrays as word line drivers. Self resetting logic implemented in dynamic logic families have been proposed as viable clock less alternatives. While these circuits can produce excellent performance, they display serious limitations in terms of area cost and power consumption. A middle of the road alternative, which can provide a good performance and avoid the limitations see in dynamic self resetting circuits, would be to implement self resetting behavior in static circuits. This alterative has been introduced recently as self resetting logic. The dynamic circuits are becoming increasingly popular because of the speed advantage over static CMOS logic circuits; hence they are widely used today in high performance and low power circuits. This paper says that by using this self resetting logic the low power VLSI circuits can be designed efficiently for counters.
... By applying differential topology, a differential circuit will run faster and require fewer transistors than traditional circuit [3]. Fewer delay stage also mean more robust again PVT variations. ...
In this paper, we examine a Digital-Controlled Oscillator (DCO) design which employs cross coupled differential inverter. DCO is a key part of an All-Digital Phase Lock Loop (ADPLL). Normal ring oscillator requires much power and area. Linearity is the key factor to determine the quality of a DCO. The effects of Process-Voltage-Temperature (PVT) can reduce its performance. Differential topology gives an improvement in DCO design. The designed DCO has frequency range from 700MHz to 1200MHz, 1.8V supply voltage based on a 0.18µm CMOS process.
... Thus, this paper primarily focuses on adders and its different architectures. In order to reduce power consumption and obtain increased performance, researchers are getting inclined towards low power designs [4][5][6][7][8]. ...
Power consumption minimization in a circuit becomes imperative with growth in demands of portable goods. However, at the same time, its speed limits the performance of a system. Therefore, there is a need of choosing optimum circuit architecture that takes into account the both conflicting parameters, that is, power dissipation and speed. Arithmetic unit is one of the vital components of portable goods and out of all arithmetic operations, adders are the most commonly used. To address the issue of high power dissipation, low-power designing styles are becoming prominent now-a-days. Hybrid Dynamic Current Mode Logic is high-speed, low-power designing style that has been recently proposed in literature. Therefore, this paper presents the comparison between performances of various topologies of adders that are implemented using a high-speed, low-power designing style: Hybrid-Dynamic Current Mode Logic (H-DyCML). All the circuits are realized in Cadence Virtuoso using 180nm CMOS technology parameter. Various performance parameters are evaluated such as: Delay, Power, Power-Delay Product, and hardware utilization. It is found that carry look-ahead adder out-stands other adders in terms of overall performance.
... The main drawback of this logic style is the need of a full custom library and the need of a CMOS to iDDPL converter, as in the case of DDPL. Modified domino differential cascode voltage switch logic (DDCVSL) was also first presented as an alternative to the standard static CMOS logic family, which tends to be faster and requires fewer transistors [44], but not for security applications as in the case of DyCML. DDCVSL is based on the basic differential cascode voltage switch logic (DCVSL) [45] and its first evaluation for security application was in [46]. ...
The fast settlement of privacy and secure operations in the Internet of Things (IoT) is appealing in the selection of mechanisms to achieve a higher level of security at minimum cost and with reasonable performances. All these aspects have been widely considered by the scientific community, but more effort is needed to allow the crypto-designer the selection of the best style for a specific application. In recent years, dozens of proposals have been presented to design circuits resistant to power analysis attacks. In this paper, a deep review of the state of the art of gate-level countermeasures against power analysis attacks has been carried out, performing a comparison between hiding approaches (the power consumption is intended to be the same for all the data processed) and the ones considering a masking procedure (the data are masked and behave as random). The most relevant proposals in the literature, 35 for hiding and 6 for masking, have been analyzed, not only by using data provided by proposers, but also those included in other references for comparison. Advantages and drawbacks of the proposals are analyzed, showing quantified data for cost, performance (delay and power), and security when available. One of the main conclusions is that the RSL proposal is the best in masking, while TSPL, HDRL, SDMLp, 3sDDL, TDPL, and SABL are those with the best security performance figures. Nevertheless, a wise combination of hiding and masking as masked_SABL presents promising results.
... Therefore, power dissipation has emerged as an important issue that results in the degradation of the performance of the overall system. To reduce power consumption, researchers are getting inclined towards low-power designs [1], [2], [3], [4] and [5]. ...
... An OR gate is a electrical circuit and it implements logical disjunction and also it behaves according to the truth table. The primitive cell diagram of SRGDI OR gate is shown in Figure 5 respectively [3][4]. The NOR gate is said to be the complement of OR operator. ...
Improvement in GDI (Gate Diffusion Input) techniques have achieved major milestones such as reduction in power, reduced area and reduction in switching activities. SRGDI (Self-Resetting GDI logic) is the advanced technique used by VLSI researchers in sequential circuits. So the purpose of this paper is to design 8-bit ALU using SRLGDI technique. This ALU contains full adder, half adder, 4X4 multiplier, comparator, AND, NAND, OR and NOR gates. Comparative analysis is to be performed with other existing CMOS techniques. The earlier and the proposed SRLGDI based ALU will be simulated using Tanner EDA with IBM 130nm CMOS technology.
... It is a asynchronous dynamic circuit. Its advantage over other GDI techniques are it reduces switching activity and also reduces power consumption [5][6][7][8]. SRL represents signals as shortduration pulses rather than as voltage levels. The analysis of SRLGDI is done exhaustively in the following section. ...
The CMOS dynamic logic has some drawbacks such as charge leakage, high power consumption, loss of noise immunity etc. due to which there was a need of introduction of Self-Resetting Logic (SRL).Our proposed idea is to design SRGDI primitives suitable for combinational designs and implement them in 8-bit ALU. ALU is to be designed using Adders, Multiplier, Comparator and Logic Gates (AND, NAND, OR, XOR). Self-Resetting Logic reduces the switching activity and power consumption. SRLGDI primitives will be simulated using Tanner EDA with IBM 130nm CMOS technology.
... Another hybrid [8] adder has been proposed for lowpower applications but the performance is also not suitable for scaled-down technology applications. Similarly, few more adders are studied [29,4,52,39,40,49] each has its own advantages and disadvantages. ...
For computational arithmetic,
a full adder is the primary logic units in VLSI applications. A new full adder circuit design has been presented in this article which is based on input switching activity pattern and gate diffusion input (GDI) technique. The adder has been designed in two stages. The first stage is an XOR–XNOR module, whereas, the final stage is for the required outputs. By using the switching activity pattern of inputs and GDI techniques at each stage, the switching activities of the transistors have been minimized. This improves delay, power consumption and computational complexity. The adder has been designed and evaluated by using the synopsis tool and compared with different existing adder cells found in the literature. It is found that the presented adder shows an improvement at least 72.86% and 66.67% in terms of speed and energy consumption, respectively. Extensive performance analyses of the full adder have also been evaluated at 32 nm CMOS and 32 nm CNFET technology node which shows promising performances in both the technology nodes.
... It is a asynchronous dynamic circuit. Its advantage over other GDI techniques are it reduces switching activity and also reduces power consumption [5][6][7][8]. SRL represents signals as shortduration pulses rather than as voltage levels. The analysis of SRLGDI is done exhaustively in the following section. ...
The CMOS dynamic logic has some drawbacks such as charge leakage, high power consumption, loss of noise
immunity etc. due to which there was a need of introduction of Self-Resetting Logic (SRL).Our proposed idea is to design
SRGDI primitives suitable for combinational designs and implement them in 8-bit ALU. ALU is to be designed using Adders,
Multiplier, Comparator and Logic Gates (AND, NAND, OR, XOR). Self-Resetting Logic reduces the switching activity and
power consumption. SRLGDI primitives will be simulated using Tanner EDA with IBM 130nm CMOS technology.
Keywords: SRGDI, ALU, Primitives, Power, Logic gates
... Thus dynamic logic families are often differential (dualrail), that is each signal is computed in both true and complemented form. There are several dynamic differential CMOS logic types such as Dual-rail Domino logic [81], DDCVSL (Dynamic Differential Cascode Voltage Switch Logic ) [82], SABL (Sense Amplifier Based Logic) [83], etc. ...
Original citation Zeinolabedini, N. 2015. Average-case analysis of power consumption in embedded systems. PhD Thesis, University College Cork. Type of publication Doctoral thesis Rights © 2015. Nasim Zeinolabedini. http://creativecommons.org/licenses/by-nc-nd/3.0/
... Several full adder circuits have been proposed targeting on design variations such as power, area and delay. Among those designs with less transistor count using pass transistor logic have been widely used to reduce power consumption [2][3][4]. These designs suffer from severe output signal degradation and cannot sustain low voltage operations, inspite of the circuit simplicity, [5]. ...
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area ,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs have been proposed over last few years with different logic styles. To reduce the power consumption several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets, charge sharing by parasitic components while connecting source and drain of CMOS transistors There are situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic which are widely used in dynamic logic circuits. Overall performance of various adder designs is evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V. On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low PDP among its counterparts.
... There has been tremendous boost on the design and development of portable electronic goods in recent past [1][2][3][4]. As the battery life is critical in these systems, there has been a paradigm shift towards low power designs. ...
This paper proposes hybrid dynamic current mode logic (H-DyCML) as an alternative to existing dynamic CML (DyCML) style for digital circuit design in mixed-signal applications. H-DyCML introduces complementary pass transistors for implementation of logic functions. This allows reduction in the stacked source-coupled transistor pair levels in comparison to the existing DyCML style. The resulting reduction in transistor pair levels permits significant speed improvement. SPICE simulations using TSMC 180 nm and 90 nm CMOS technology parameters are carried out to verify the functionality and to identify their advantages. Some issues related to the compatibility of the complementary pass transistor logic have been investigated and the appropriate solutions have been proposed. The performance of the proposed H-DyCML gates is compared with the existing DyCML gates. The comparison confirms that proposed H-DyCML gates is faster than the existing DyCML gates.
... Dynamic logic families are a good candidate for high speed 66 and high performance circuit than the conventional static 67 CMOS. Dynamic logic requires fewer transistors to implement 68 a given logic function, less area and faster switching speed due 69 to its reduced load capacitance (Yee and Sechen, 1996; Balsara 70 and Steiss., 1996; Srivastava et al., 1998. However this circuit 71 suffers from charge sharing, charge leakage, loss of noise 72 immunity, timing problem due to clock input and feed 73 through. ...
The objective vividly defines a new low-power and high-speed logic family; named Self Resetting Logic with Gate Diffusion Input (SRLGDI). This logic family resolves the issues in dynamic circuits like charge sharing, charge leakage, short circuit power dissipation, monotonicity requirement and low output voltage. In the proposed design structure of SRLGDI, the pull down tree is implemented with Gate Diffusion Input (GDI) with level restoration which apparently eliminated the conductance overlap between nMOS and pMOS devices, thereby reducing the short circuit power dissipation and providing High Output Voltage VoH. The output stage of SRLGDI has been incorporated with an inverter to produce both true and complementary output function. The Resistance Capacitance (RC) delay model has been proposed to obtain the total delay of the circuit during precharge and evaluation phase. Using SRLGDI, the primitive cells and 3 different full adder circuits were designed and simulated in a 0.250μm Complementary Metal Oxide Semiconductor (CMOS) process technology. The simulated result demonstrates that the proposed SRLGDI logic family is superior in terms of speed and power consumption with respect to other logic families like Dynamic Logic (DY), CMOS, Self Resetting CMOS (SRCMOS) and GDI.
... The implementation of AND/OR can be obtained by placing the NMOS stack in series and parallel connection, whereas the gates NAND/NOR can be implemented with De Morgan's law, an OR gate with inverted input signals behaves as a NAND gate. Similarly an AND gate with inverted input signals behaves as a NOR gate [8]. ...
In this paper, circuit topologies for near-threshold computing (NTC) are proposed and evaluated. Three separate dynamic differential signaling based logic (DDSL) families are developed in a 130 nm technology to operate at 400 mV and 450 mV. The proposed logic families outperform contemporary CMOS and current-mode logic (CML) circuits implemented for near-threshold. The DDSL families are described as dynamic current-mode logic (DCML), latched DCML (LDCML), and dynamic feedback current-mode logic (DFCML). Simulation and analysis are performed through implementation of boolean functions and a 4 × 4 bit array multiplier. At a 450 mV supply voltage, the total power of the 4 × 4 DFCML multiplier is reduced to 0.95 × and 0.009 × , while the maximum operating frequency is improved by 1.4 × and 1.12 × as compared to, respectively, CMOS and CML multipliers. The DCML multiplier consumes 1.48 × the power while improving fmax by 1.65 × as compared to a CMOS multiplier. A chain of four inverters implemented with the developed dynamic logic families exhibited an energy delay product (EDP) of 0.27 × and 0.016 × that of, respectively, CMOS and CML implementations. The mean noise margins, also evaluated with a chain of inverters, of the DFCML and LDCML are at least 2.5× greater than that of CMOS.
—With the continuous growth of semiconductor
technologies, the design of high-speed circuits is a need of the
hour. Current Mode Logic (CML), a derivation from Emitter
Coupled Logic (ECL) is such an approach with concerns
present to be improvised. Targeting that, we have come up
with a new design of dynamic CML to structure a power
efficient D-Flipflop. The simulations are carried out for 90nm
CMOS using Synopsys H-Spice platform at a supply voltage
and operating frequency of 1.2V and 10GHz respectively. The
device footprint reads an area requirement of 108.624 µm2
(16.045µm × 6.77µm). This design is noted to dissipate a very
low power of 219.05uW and delay of as small as 31.30ps when
driven with aperiodic data of 2.5GHz.
Adders are an integral part of arithmetic logic units in the digital system. Performance of the adder circuits decides the performance of those circuit and systems. Full adders are designed either in a conventional approach or hybrid approach. In the conventional approach, only one logic style is used, whereas, in a hybrid approach, two or more logic styles are used. A performance analysis between conventional and hybrid 1-bit full adder circuits is presented in this paper. In the conventional design, complementary metal–oxide–semiconductor (CMOS) full adder, complementary pass logic (CPL) full adder, and transmission gate full adder (TGA) are the most popular. In this paper, CMOS full adder and CPL full adder are reported. The hybrid adder reported in this paper is designed using CMOS logic and transmission gate (TG) logic. The circuits are implemented using Cadence virtuoso tools with 180 nm United Microelectronics Company (UMC) technology. From the pre-layout simulation, performance metrics such as power, speed, and power delay products were computed. Performance of each of the circuits in terms of power, speed, power delay product (PDP), and area requirements in terms of transistor counts for the design is then compared.
Keywords: Low power, Delay Power–delay product, CMOS, CPL, Hybrid design.
An analog clock generator built with complementary logic cells in UTBB-FDSOI delivers the robust symmetrical clocks required to control high-performance differential switched-capacitor circuits. Using back-gate feedback and sizing respecting static and dynamic symmetry, the proposed solution is very tolerant to process inherent variations to the deep nanometer CMOS processes.
In a digital CMOS circuit, reducing the supply voltage V
dd
is the most effective approach to minimize dynamic power dissipation. This has been evident by the quadratic relation between the dynamic power and V
dd
in Equation (2.1). However, reducing only the supply voltage seriously degrades the circuit’s performance. One way to maintain performance is to scale down both V
dd
and the threshold voltage V
th
. However, reducing V
th
increases the subthreshold leakage current exponentially (Equation (2.5)). Dynamic logic circuits such as Domino have a significantly worse tolerance to device subthreshold leakage compared to static CMOS circuits [1]. This makes it risky to utilize low threshold voltage (LVT) devices in order to improve the critical path delay [2]. Therefore, a trade-off exists between improving the gate’s reliability (Noise Margin) and enhancing its speed.
MOS Current Mode Logic (MCML) is well known as a high performance logic family for mixed signal systems [1] [2]. Figure 7.1 illustrates thetecturearchi of an MCML inverter/buffer. Transistor Q
1 acts as a DC current source controlled by a bias voltage Vbias, and R are pullup resistors. The logic function is implemented by the logic block connected between the resistors and the current source. For an inverter/buffer, the logic block is the differential pair constructed by transistors Q
2 and Q
2′.
In the preceeding chapter, nonclocked circuit topologies were shown generally to be versatile, reliable, and relatively low in power consumption. Clocked logic, on the other hand, is recognized for its performance advantages, which may be attributed to the following:
1.
In Static CMOS, logic must be built redundantly; circuit operations must be realized in both NFET and PFET device structures to accomodate both up and down logic transitions. This reduces performance by adding gate fan-out load and interconnect RC. Higher device counts lead to longer interconnects, higher power consumption and bigger die1.
2.
In static CMOS, even when the redundant structure is off, the added diffusion and overlap capacitive loads increase power and delay.
3.
In Static CMOS, PFET devices must drive the same loads as NFET devices, at half the transconductance. This drives PFET devices to generally be 2X the width of NFET devices for balanced transitions. The impact is of particular concern structures such as PFET devices 5 and 6 in Figure 2.2a.
In this paper we show that self synchronous circuits can provide robust operation in both soft error prone and low voltage operating environments. Self synchronous circuits are shown to be self checking, where a soft error will either cause a detectable error or halt operation of the circuit. A watchdog circuit is proposed to autonomously detect dual-rail '11' errors and prevent propagation, with measurements in 65 nm CMOS showing seamless operation from 1.6V to 0.37V. Compared to a system without the watchdog circuit size and energy-per-operation is increased 6.9% and 16% respectively, while error tolerance to noise is improved 83% and 40% at 1.2V and 0.4V respectively. A circuit that uses the dual-pipeline circuit style as redundancy against permanent faults is also presented and 40 nm CMOS measurement results shows correct operation with throughput of 1.2 GHz and 810MHz at 1.1V before and after disabling a faulty pipeline stage respectively. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.
In this paper, the design of a XOR/XNOR gate for low-power cryptographic applications is presented. The proposed gate optimizes the SABL (Sense Amplifier Based Logic) gate, widely used in cryptocircuit implementations, by removing residual charge in the pull-down circuit and simplifying the pull-up. The resulting gate improves SABL in terms of area, power consumption, propagation delay and resilience against Differential Power Analysis (DPA) attacks. To demonstrate the gain in performances, both gates have been designed, physically implemented and experimentally characterized, in a 90nm TSMC technology. Experimental results show a reduction of 15% in area, 12% in power consumption, and 40% in delay in the proposed gate. To demonstrate the gain in security of the proposal, simulation-based DPA attacks have been performed on respective Kasumi Sbox9 implementations, being our proposal suitable for inmediate application in high-performance secure cryptographic applications.
Dynamic circuits using n-channel multiple-input floating-gate MOS(FGMOS) transistors to realize binary and ternary logic are presented. In binary domino circuits, the n-channel FGMOS transistors are used to replace the nMOS logic block to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a summation signal is introduced in binary circuit design. Finally, two dynamic ternary literal circuits are designed using n-channel FGMOS transistors. The proposed voltage-mode dynamic ternary literal circuits have simpler structure. All the proposed dynamic circuits are verified by HSPICE simulation results with TSMC 0.35amu;m 2-ploy 4-metal CMOS technology.
Information leakaged by cryptosistems can be used by third parties to reveal critical information using Side Channel Attacks (SCAs). Differential Power Analysis (DPA) is a SCA that uses the power consumption dependence on the processed data. Designers widely use differential logic styles with constant power consumption to protect devices against DPA. However, the right use of such circuits needs a fully symmetric structure and layout, and to remove any memory effect that could leak information. In this paper we propose improved low-power gates that provide excellent results against DPA attacks. Simulation based DPA attacks on Sbox9 are used to validate the effectiveness of the proposals.
Voltage controlled oscillator(VCO) based analog-to-digital converter(ADC) utilizes the superior time resolution and digital processing power ottime domain signal processing. Voltage controlled oscillator based analog-to-digital converters also have inherent first order noise shaping property and very high accuracy which can be achieved by reducing both area and power consumption. This paper analyses the performance of VCO implemented by current mode logic(CML) based fully differential Ring oscillator for high speed and applications that require high noise immunity. Analytical model of limitation on maximum achievable oscillation frequency of Ring oscillator by CMOS inverter is proposed showing why it cannot be used in high speed applications. Designed VCO has linear tuning range from 7.2 GHz to 1 GHz. Using control voltage for the above VCO a 6-bit analog-to-digital converter is designed in 90nm CMOS.
Applications of arithmetic operations in integrated circuits are manifold. In most of the digital systems, adders are the fundamental component in the design of application specific integrated circuits like RISC processors, Digital Signal Processors (DSP), microprocessors etc. This paper focuses two main design approaches. The former presents the problems identified in the existing Gate Diffusion Input (GDI) technique and its design solution in Modified Gate Diffusion Input (MGDI). The primitive logic cells are construction in MGDI and its performance issues are compared with existing GDI. The latter presents the implementation of 3 different MGDI full adders and a complete verification and comparison is also carried out to test the performance of the proposed adders. The performance analysis has been evaluated by Tanner simulator using TSMC 0.250 μm technologies. The simulation results reveal better delay and power performance of proposed adder cells as compared to GDI, PT and CMOS at 0.250 μm technologies.
In this paper, Phase Locked Loop (PLL) and frequency synthesizer is designed with Self Resetting Logic Complementary Metal Oxide Semi Conductor (SRLCMOS) using GDI technique. The design enables the implementation of different logic functions with less number of gates, low leakage current and low leakage power when compared with CMOS and other existing techniques. In the proposed design, the pull down tree is implemented with Gate Diffusion Input (GDI) with level restoration which apparently eliminates the conductance overlap between nmos and pmos devices, thereby reducing the short circuit power dissipation and providing High Output Voltage VOH. Simulations are done using 180nm technology.
Abstract. In Chapter 4 of book Applications of Advanced Elctromagnetics. Components and Systems, a topological approach to the theory of EM boundary value problems has been already considered, and its computational effectiveness demonstrated. Additionally to the computational aspects, the ideas of topology are applicable to the noise-tolerant signaling, computing, microwave imaging, and this application area and related results are considered below.
A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 and 60 mW.
A new high-speed domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.
A novel differential dynamic CMOS logic using multiple-input floating-gate MOS(FGMOS) transistors is proposed. In this circuit family, a pair of n-channel multiple-input FGMOS pull down logic networks is used to replace the nMOS logic tree in the conventional dynamic differential cascode voltage switch logic circuit. A simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is also discussed. By using multiple-input FGMOS, the logic tree can be significantly simplified. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed design scheme.
In this paper a new approach of reducing power for a given system is developed that is self resetting logic, a parallel compressor is developed for multiplier by reducing its power with facilitation of this low power logic technique. By using this technique the power dissipation is significantly reduced with respect to other logics. By implementing the parallel compressor the performance of the circuit is increases.
A new enhanced dynamic logic using multiple-input floating-gate MOS(FGMOS) transistors is presented. The circuit technique is designed using an n-channel multiple-input FGMOS pull down logic tree instead of the nMOS logic tree in the conventional enhanced differential cascode voltage switch logic (EDCVSL) circuit. The logic tree of EDCVSL is dramatically simplified by utilizing multiple-input FGMOS transistors. The proposed dynamic logic does not require complementary inputs, and keeps the benefits of EDCVSL. A simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is given. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology have verified the effectiveness of the proposed circuits.
We have previously presented a process variation robust self synchronous FPGA that uses dual pipelines (DP) for high throughput 3GHz operation. As process technology shrinks, the importance of not only variation robust, but error robust systems increases. In this paper, we analyze the DP robustness to single-event-upsets and propose several gate-level architectures to implement error detection and correction, autonomous disabling of faulty pipeline-stages, and programmable time-interleaved redundancy, showing that self synchronous systems are a very promising candidate for addressing reliability problems in sub-100nm circuits. Test chips are fabricated and show successful operation, detection of errors, and autonomous pipeline-disabling in 65nm and 40nm.
A new static CMOS differential logic based on multiple-input floating-gate MOS (FGMOS) transistor is proposed. In this circuit configuration, a pair of n-channel multiple-input FGMOS pull down networks is used to replace the nMOS logic tree in the conventional cascode voltage switch logic (CVSL) circuit in order to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is also discussed. On the basis of the proposed synthesis method, some logic circuits including full adder are designed. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology with a power supply of 1.5V is utilized to validate the effectiveness of the proposed logic circuits.
Low power design has become one of the primary focuses in digital VLSI circuits, especially in clocked devices like microprocessor and portable devices. Optimization of several devices for speed and power is a significant issue in low-voltage and low-power applications. These issues can be overcome by incorporating Gated Diffusion Input (GDI) technique. Now-a-days dynamic circuits are becoming increasingly popular because of the speed advantage over static CMOS logic circuits. A fundamental difficulty with dynamic circuits is the monotonicity requirement and difficulties like charge sharing feed through, charge leakage, single-event upsets, etc. These issues can be eliminated using Self-reset logic (SRL). This logic provides a design solution where the clocking overhead is minimized. So the tradeoff between speed and power can be achieved through SRL and GDI technique. A new family of Modified self-reset logic (SRL) cells implemented with modified GDI technique is presented in this paper. The implementations proposed in this work are clocked storage element like D-FF in SRL with Modified Gate Diffusion Input Technique. This technique allows reducing power consumption and delay of digital circuits, while maintaining low complexity of logic design. Delay and power has been evaluated by Tanner simulator using TSMC 0.250μm technology. The simulation results reveal better delay and power performance of proposed delay elements as compared to existing dynamic, GDI cell and CMOS at 0.250μm technology.
A 65nm self synchronous field programmable gate array (SSFPGA) which
uses autonomous gate-level power gating with minimal control circuitry
overhead for energy minimum operation is presented. The use of self
synchronous signaling allows the FPGA to operate at voltages down to
370mV without any parameter tuning. We show both 2.6x total energy
reduction and 6.4x performance improvement at the same time for energy
minimum operation compared to the non-power gated SSFPGA, and compared
to the latest research 1.8x improvement in power-delay product (PDP) and
2x performance improvement. When compared to a synchronous FPGA in a
similar process we are able to show up to 84.6x PDP improvement. We also
show energy minimum operation for maximum throughput on the power gated
SSFPGA is achieved at 0.6V, 27fJ/operation at 264MHz.
We present a low overhead technique that can be used to offset both large systematic and random process delay variation in the near-threshold voltage operation region. We present an analysis of this this technique applied to a 65nm CMOS self synchronous FPGA that is capable of operation from 2.0V to 0.37V. By using dual voltage supplies, we can offset gate-level pipeline stages that show large delay variation, to achieve energy savings per operation of up to 102x for a 200 stage pipeline.
A 65 nm self-synchronous field programmable gate array (SSFPGA) with delay insensitive operation and pipeline granularity at the gate level, is shown to be robust to process voltage and temperature (PVT) variations. The proposed SSFPGA employs a 38 38 array of four-input, three-stage self-synchronous confi gurable logic blocks, with the introduction of a new dual tree-divider four-input, three-pipeline stage LUT to achieve a 2.97 GHz throughput at 1.2 V. Correct operation is measured with 500 mVp-p, 1.12 GHz externally introduced power supply noise at 1.2 V power supply, equivalent to 42% power supply bounce. Sensitivity against power supply noise frequency has been measured, and confirmed with simulation results to show a strong correlation with the average operating frequency. Correct operation was shown over 10 chips with 16% performance variation, with VDD change from 728 mV to 2 V, and temperature change from 0 C to 120 C, without tuning any input parameters such as clock frequency, supply voltages and biases. Results show the SSFPGA can adapt and is inherently robust to these variations with internal throughput measured from 300 MHz to 4.07 GHz, while maintaining correct operation. The operation under noisey power supply conditions is compared to a conventional synchronous FPGA, which show the SSFPGA has 4.2 times error free operation. The failure mode is also measured on the SSFPGA using an accelerated stress cycle between 0 C and 120 C at 2 V, showing the SSFPGA has 8% longer correct operation before chip malfunction past a 10% delay margin commonly used in synchronous systems. Index Terms—Dynamic logic, gate-level dual pipeline, high throughput, power supply bounce, reconfigurable VLSI, self-syn- chronous field-programmable gate array (SSFPGA), variation robust.
We present a footless DCVSL logic with preconditioning free self-timed scheme. The proposed footless DCVSL employs self-timed precharge control logic to precharge DCVSL nMOS pull-down network. The footless DCVSL is free from timing generator to generate precharge signal after all the input signals become 0, which is required for the conventional footless DCVSL logics. The proposed footless DCVSL achieves 4.5% delay improvement for FO8 logic chain using 90 nm CMOS process without any complex delay tuning circuits.
Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.
Differential CMOS logic has many advantages over the static CMOS implemented nand/nor logic families. It has the ability to evaluate a complex combinational function in a single gate delay. It also provides high layout density and requires no static power consumption. In this paper we present an improved differential CMOS logic family— Enabled/disabled CMOS Differential Logic (ECDL). We also present an extension to this logic technique which enables the implementation of iterative networks. Iterative networks are useful in realizing some important logic functions. The simplicity of design, the ease of testing, and the small area-time product make iterative networks a desirable VLSI implementation method of logic functions. Two simple logic functions are implemented to demonstrate this methodology.
The use of a self-timed precharge latch (STPL) is proposed for the
design of self-timed systems based on the four-cycle and two-cycle
handshaking protocols. The techniques allow different data to be stored
and computed in consecutive pipeline stages simultaneously without using
a conventional data register. The techniques allow the propagation of
data across the pipeline stage in a fast domino manner, parallel with
the handshaking signals. The variable-length FIFOs designed using these
techniques result in a significant reduction in silicon area and
fall-through delay compared with those designed based on other
techniques
A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.
Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. Two procedures are presented for constructing DCVS trees to perform random logic functions. The first procedure uses a Karnaugh mapping technique and is a very powerful pictorial method for hand-processing designs involving up to six variables. The second procedure is a tabular method based on the Quine-McCluskey approach and is suitable for functions with more than six variables. Both of these procedures are considerably easier to implement than a recently proposed algebraic technique which relies upon decomposition and factorization of Boolean expressions. Several DCVS circuits that have been synthesized by the Karnaugh map (K-map) and tabular procedures are presented.
The authors present a study of the charge-sharing problem and its effect on the performance of CMOS-domino logic. Several solutions to the charge-sharing problem are examined, and the results are verified by simulation. Thus, the charge-sharing problem in CMOS-domino logic was identified and alternate approaches were evaluated.
Subnanosecond gate delays (0.8 ns) have been measured on complex logic gates (e.g. sum functions of a full adder) designed in the differential split-level CMOS circuit technique. This high speed has been achieved by reducing the logic swing (2.4 V) on interconnect lines between logic gates, by using current controlled cascoded cross-coupled NMOS-PMOS loads, by using combined open NMOS drains as outputs, and by using shorter channel lengths (L/SUB eff/=1 μm) for the NMOS devices in the logic trees with reduced maximum drain-source voltages to avoid reliability problems. Extra ion implantation protects these transistors from punchthrough.
Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks φ and φ~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.
Four different adders were implemented using a CMOS differential
logic, enable/disable differential CMOS logic (ECDL). The authors
discuss the design and implementation of several common addition
algorithms using ECDL. These adders have the self-timed characteristic.
Comparisons are made among these algorithms in terms of delay and area.
The actual implementation was done with MOSIS 3-μm scalable process.
Evaluations are performed in terms of area and delay. One conclusion
that can be made is that the carry-skip adder seems to have the best
speed/area combined performance. A first-order modeling method is used
to estimate the area and speed of different implementations
Differential split-level CMOS logic for subnanosecond speeds Implementation of iterative arrays with CMOS differential logic Design-performance trade-offs in CMOS-domino logic NORA: A racefree dynamic DMOS technique for pipelined logic structure Self-timed precharge latch
- K M Chu
- D L Pulfrey
- L Pfennings
- W Mol
- J Bastiaens
- J Van
- S L V G Lu
- R Oklobdzija
- N F Montoye
- H J D Goncalves
- Man
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