Design and Implementation of UART Serial Communication Module Based on FPGA

Abstract

Designing a System–on-a-Chip (SoC) on the FPGA is now a trend in digital design because it gives a lot of advantages over discrete electronic based product such as higher speed, lower power consumption, smaller size, lower cost etc. UART (universal asynchronous receiver and transmitter) is a serial communication protocol. Basically this protocol is used to permit short distance, low cost and reliable full duplex communication. It is used to exchange data between the processor and peripherals. For reliable data transmission, serial communication is very effective than parallel communication when considering the cost as well as complexity of the system increases. To design a UART which is implemented with Verilog HDL can be easily integrated onto FPGA to achieve more reliable and error free data transmission. This paper presents the hardware implementation of UART using Verilog HDL on FPGA:EP2C20F484C7, family of Altera cyclone II. Simulation is done by Quartus II simulator which is fully compatible with UART.

Full text

Design and Implementation of UART Serial
Communication Module Based on FPGA
Biswajit Roy Dakua, Md. Ismail Hossain and Foisal Ahmed
Department of Electronics & Telecommunication Engineering
Prime University
Dhaka, Bangladesh
biswajit.lrbd@gmail.com, ihtotocom@gmail.com, faisal_ete@yahoo.com
Abstract —Designing a System–on-a-Chip (SoC) on the FPGA
is now a trend in digital design because it gives a lot of
advantages over discrete electronic based product such as higher
speed, lower power consumption, smaller size, lower cost etc.
UART (universal asynchronous receiver and transmitter) is a
serial communication protocol. Basically this protocol is used to
permit short distance, low cost and reliable full duplex
communication. It is used to exchange data between the
processor and peripherals. For reliable data transmission, serial
communication is very effective than parallel communication
when considering the cost as well as complexity of the system
increases. To design a UART which is implemented with Verilog
HDL can be easily integrated onto FPGA to achieve more
reliable and error free data transmission. This paper presents the
hardware implementation of UART using Verilog HDL on
FPGA:EP2C20F484C7, family of Altera cyclone II. Simulation is
done by Quartus II simulator which is fully compatible with
UART.
Key words—UART, Verilog HDL, FPGA, SoC, Quartus II.
I. INTRODUCTION
FPGA or Field Programmable Gate Array is a type of logic
chip that can be programmed. The FPGA configuration is
generally specified using a hardware description language
(HDL). FPGAs have programmable logic components called
‘logic blocks’ and a hierarchy or reconfigurable interconnects
which facilitate the wiring of the blocks together[1].
Asynchronous serial communication can be implemented
easily on FPGA.
Asynchronous serial communication is a popular, easy and
successful method of sending and receiving data. This
technology is usually implemented by UART. Universal
Asynchronous Receiver Transmitter (UART) is a microchip
with programming that controls a computer’s interface to its
attached serial devices[2]. The UART is basically used in
between the slow and the fast peripheral devices for example:
computer and printer or in between the controller and LCD [3].
This paper implements the core function of UART and
integrates them into a FPGA chip. In our design, we have used
FSM (finite state machine) so that the design of UART
becomes more stable and reliable. The UART has mainly three
parts which are transmitter, receiver and baud rate generator.
Transmitter sends data at specific clock rate. It first sends
binary 0 as the start bit. The start bit is used to alert the receiver
that a word of data is about to be sent and to force the clock in
the receiver for synchronization with the clock in the
transmitter[4]. Then it sends the data bits serially. After
sending all data bits then it sends binary 1 as a stop bit. Stop bit
alert the receiver that a word has been send completely. The
time to take to send every bit must be equal. Figure 1 shows the
frame format of UART.
Fig. 1. UART frame format
When receiver receives all bits it discards start bit and stop
bit. Then it converts the serial data into parallel format.
Baud rate generator generates the clock frequency for
transmitter and receiver at a specific baud rate. Our design has
used 9600bps.
II.UART TRANSMITTER
Transmitter module converts the parallel data into serial
bit stream. The architecture of the transmitter will consist of a
controller, a data register (tx_datareg), a data shift register
(tx_shiftreg) and a status register(bit_counter) to count the bits
that are transmitted. The input signals are provided by the host
processor and the output signals control the movement of data
in the UART. The controller has the following inputs.
 ready: assert by the host machine to
indicate that data bus has valid
data.
 t_byte: transition of state to sending.
 bit_counter: counts the bit during transmission.
Controller forms the following output to control the datapath
of transmitter.
0/1
1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
Start bit
Stop bit
Data bits
International Conference on Materials, Electronics & Information Engineering, ICMEIE-2015
05-06 June, 2015, Faculty of Engineering, University of Rajshahi, Bangladesh
www.ru.ac.bd/icmeie2015/proceedings/
ISBN 978-984-33-8940--4

 load_shiftreg: Assertion of load_shiftreg loads
the contents of tx_datareg to
tx_shiftreg.
 clear: clears bit_counter.
In our design of transmitter, finite state machine has been
used. The transmitter state machine has three states.
A. idle
When the reset is asserted, machine enters in this state. It
is also the default state. In this state two activities will occur.
 The contents of tx_datareg are loaded into
tx_shiftreg, which contains 10 bits; LSB is the start
bit and MSB is the stop bit and middle 8 bits are data
bit.
 State transition from state idle to state waiting.
B. waiting
The machine remains in waiting state until the external
processor asserts t_byte.
C. sending
At the sending state, the LSB of tx_shiftreg will be
transmitted. The first transmitted bit is 0, which alerts the
receiver of start of transmission. At the same time, the
contents of tx_shiftreg are shifted toward LSB. As the data
shift occurring, 1s are back-filled in tx_shiftreg and
bit_counter is incremented. State remains in sending, while
bit_counter is less then [word_size+2].As the bit_counter
reaches [word_size+2], clear is driven to 1 indicating that all
bits of augmented word have been shifted to serial output. At
the next active edge clock, machine returns to idle.
In Fig. 2 state diagram of UART transmitter has been
shown.
III. BAUD RATE GENERATOR
The baud rate of a data communication system is the
number of symbols per second transferred. A symbol may have
more than two states, so it may represents more than one binary
bit.
Baud rate generator is actually a kind of frequency divider.
The baud rate frequency factor can be calculated according to a
given system clock frequency and the required baud rate.
The frequency coefficient (M) i.e. count value of the baud
rate generator is,
In our design, the system clock is 50 MHz and baud rate is
9600 bps. The output clock frequency of baud rate generator is
1×9600Hz.
So,
= 5208.333…
Here, the frequency coefficient M is not in round figure. To
obtain the efficiency in FPGA, we rely on the fact that the
serial interface can tolerate a few % of error in baud rate
generator.
IV. UART RECEIVER
The UART receiver receives serial bit stream of data. Then
it removes the start and stop bit and make the data in parallel
format.
In our design, data will be sampled at a rate of baud rate
generator determined by sample_clock, which is generated at
the receiver’s host. The cycle of the sample_clock will be
counted to ensure that the data are sampled in the middle of a
bit time. The sampling algorithm must verify:
 The start bit has been received properly.
 Generate sample.
 Load the data into local bus.
The arrival of the start bit will be determined by successive
samples of value 0 after the input data goes low. Then three
additional samples will be taken to confirm that a valid start bit
is arrived. Thereafter 8 successive bits will be sampled at
approximately centre of their bit times.
In our design, the receiver state machine has also three
states: - idle, starting and receiving. Transitions between states
are synchronized by sample_clock.
A. idle
Assertion of asynchronous active low reset put the machine
in idle state. It is also the default state. It remains there until
data_in is active low. If data_in is active high, the machine
makes a transition to state starting.
B. starting
In starting state, the machine samples data_in to determine
whether the first bit is valid start bit or not. If the bit is zero,
then it is valid start bit, otherwise it is invalid. Depending on
the sampled values, inc_sample_counter will be asserted which
increment the value of counter. It also asserts
System frequency
Factor of baud rate × baud rate
M=
M=
50 MHz
1×9600Hz
sending
waiting
idle
reset=0 t_byte=0
bit_counter=word_size+2
shift=1
ready=1 t_byte=1
Fig. 2. State diagram of UART transmitter
International Conference on Materials, Electronics & Information Engineering, ICMEIE-2015
05-06 June, 2015, Faculty of Engineering, University of Rajshahi, Bangladesh
www.ru.ac.bd/icmeie2015/proceedings/
ISBN 978-984-33-8940--4

clr_sample_counter to clear the counter. If the next three
samples of data_in is zero, the machine decides that the start bit
is valid and makes a transition to the state receiving.
C. Receiving
In the receiving state, 8 samples are taken for 8 data bits.
inc_sample_counter will be asserted here. Then bit_counter is
incremented. If the sample bit is not the last bit,
inc_bit_counter and shift are asserted. The assertion of shift
will cause the sample value to be loaded into the MSB of
rcv_shiftreg which is receiver shift register. It will also shift the
7 leftmost bits of the register towards the LSB. When all the
bits have been sampled, load and ready_out are driven to 1.
With assertion of load with logic high, the contents of receiver
shiftreg will load into the data bus as a parallel word. Assertion
of ready_out is the handshake output signal to the processor.
In Fig. 3 state diagram of UART receiver has been shown.
Fig. 3. State diagram of UART receiver
V. SIMULATION RESULTS
For simulation purposes, we use Quartus II software.
Device is Altera cyclone II, FPGA: EP2C20F484C7.
Simulations for transmitter and receiver are done separately.
A. Transmitter simulation
Figure 4 shows transmitter simulation where clock, reset,
ready, t_byte are used as input node and data_out is used as
output node which is the serial output of transmitter. Additional
two nodes serial_test and sent_word are used as output node
for inspection whether the data_out gives the desired value or
not.
According to design, the transmitter clock frequency
generated by baud rate generator is 9600Hz.
Transmitter sends the ASCII value of “u” which is 75 in
Hexadecimal value and in binary is (1110101)2. sent_word
shows that simulation is done successfully.
Fig. 4. Simulation result of transmitter
B. Receiver simulation
Figure 5 shows receiver simulation where serial_in,
sample_clock, reset, ready_in used as input node, and
rcv_datareg is used as output node. error1 and error2 ensure
that the rcv_datareg provides the desired value.
In receiver simulation, receiver sample_clock frequency
generated by baud rate generator is 9600Hz and the baud rate is
9600bps.The input value of receiver is the ASCII value of “u”
which is 75 in Hexadecimal and in binary is (1110101)2.
rcv_datareg receives it successfully. The values of error1 and
error2 are logic lows which ensure that simulation is error free.
Fig. 5. Simulation result of receiver
serial_in=1
sample_counter=3
bit_counter<8
sample_counter<3
serial_in=1
bit_counter=8
idle
starting
receiving
reset serial_in=0
Received data
Transmitted data
International Conference on Materials, Electronics & Information Engineering, ICMEIE-2015
05-06 June, 2015, Faculty of Engineering, University of Rajshahi, Bangladesh
www.ru.ac.bd/icmeie2015/proceedings/
ISBN 978-984-33-8940--4

C. Schematic diagram of UART
Figure 6 shows the schematic diagram of UART.
Fig. 6. RTL Schematic diagram of UART
VI. IMPLEMENTATION
The proposed design is implemented on Altera cyclone II,
FPGA: EP2C20F484C7. Table I shows the comparison of
resources used between reference research[4] and our
proposed design in the transmitter section where our design
shown better result.
TABLE I. TRANSMITTER FLOW SUMMARY
Parameters Proposed design Reference
research[4]
Logic elements
51(Out of 18,752)
78
Pins
5(Out of 315)
13
The total resources used in the receiver are also shown in
the Table II.
TABLE II. RECEIVER FLOW SUMMARY
Parameters Usage Percentage
Logic elements
66(Out of 18,752)
<1%
Combinational functions
59(Out of 18,752)
<1%
Dedicated logic registers
40(Out of 18,752)
<1%
Registers
40
Pins
15(Out of 315)
5%
The transmitted signal from rs-232 serial port of DE1 board
is shown in figure 7. This signal is observed from oscilloscope
which is much compatible for communicating with GSM
module. In future, this design will be implemented with full
duplex serial communication by GSM module.
Fig. 7. Transmitted signal of UART
VII. CONCLUSION
This paper describes the architecture of UART and
implemented this on the FPGA using Verilog description
language to achieve reliable serial data communication.
Function of UART has been tested using Quartus II simulator,
Altera’s Cyclone II family and FPGA chip EP2C20F484C7.
We find the simulation results are reliable and stable. The
design has great flexibility i.e. by error checking technique, we
can detect different types of error occurred during
communication and hence correct them, it also compatible with
different baud rate. So, this design can effectively play a vital
role in the SoC technology in upcoming year.
REFERENCES
[1] N. R. Laddha, A. P. Thakare, “Implementation of serial communication
using UART with configurable baud rate,” International Journal on
Recent and Innovation Trends in Computing and Communication, vol.1,
Issue 4, pp. 263-268.
[2] S. Saha, M. A. Rahman, A. Thakur, “Design and Implementation of a
BIST Embedded High Speed RS- 422 Utilized UART over FPGA,”
Fourth International Conference on Computing, Communications and
Networking Technologies (ICCCNT), pp. 1-5, 4-6 July 2013
[3] G. Bandhawarkar Wakhele, I. Aggarwal and S. Gaba, “Synthesis and
Implementation of UART using VHDL codes,” International
Symposium on Computer, Consumer and Control (IS3C), pp. 1-3, 4-6
June 2012.
[4] F. Yi-yuan, C. Xue-jun, “Design and Simulation of UART Serial
Communication Module Based on VHDL,” 3rd International workshop
on Intelligent System and Applications (ISA), pp. 1-4, 28-29 May 2011.
[5] Y. Daniel Sukumar, J. Jayanth Kumar, N. Prasad Reddy, S. David
Dhinakaran, “8-BIT UART IMPLEMENTATION IN FPGA WITH
BIST TECHIQUE,” IJERSS, vol. 1, Issue 4, April 2014.
[6] N. Patel, V. Patel, V. Patel, “VHDL Implementation of UART with
Status Register,” International Conference on Communication System
and Network Technologies (CSNT), pp. 750-754, 11-13 May 2012.
[7] N. F. Mahat, “Design of a 9-bit UART Module Based on Verilog HDL,”
10th IEEE International Conference on Semiconductor Electronics
(ICSE), pp. 570-573, 2012.
[8] Y. Wang, K. Song, “A New Approach to Realize UART,” International
Conference on Electronic and Mechanical Engineering and Information
Technology (EMEIT), vol.5, pp.2749-2752, 12-14 Aug. 2011.
International Conference on Materials, Electronics & Information Engineering, ICMEIE-2015
05-06 June, 2015, Faculty of Engineering, University of Rajshahi, Bangladesh
www.ru.ac.bd/icmeie2015/proceedings/
ISBN 978-984-33-8940--4