Implementation of DDS chirp signal generator on FPGA

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Implementation of DDS Chirp Signal Generator on
FPGA
Heein Yang
Department of Electrical and
Computer Engineering
Ajou University
Suwon, Korea
kfcddong@ajou.ac.kr
Sang-Burm Ryu, Hyun-Chul Lee, Sang-Gyu
Lee, and Sang-Soon Yong
Department of Payload Development
Korea Aerospace Research Institute
Daejeon, Korea
{sbryu11, hlee, sglee, ssyong}@kari.re.kr
Jae-Hyun Kim
Department of Electrical and
Computer Engineering
Ajou University
Suwon, Korea
jkim@ajou.ac.kr
Abstract— Synthetic aperture radar (SAR) is an active sensor
that is widely used such as military purpose, land observation,
and etc. The main characteristics of SAR system are as follow.
First, as SAR uses microwave, it can be operated regardless of
the weather and day-night conditions. SAR system uses the signal
called chirp to acquire large bandwidth then it provides high-
resolution images. The conventional analog type chirp generator
of SAR system occupies large amount of space and weight. To
implement chirp generator in small satellites, implementation of
chirp generator on FPGA will be discussed in this paper.
Keywords—Chirp signal; FPGA; synthetic aperture radar;
direct digital synthesizer; chirp generator)
I. INTRODUCTION
Synthetic aperture radar (SAR) is an active sensor platform
that uses the microwave of 1-1000mm wave length to observe
land surface. Different from optical sensor which uses sun light
for its illumination source, SAR sensor can acquire the high-
resolution target image regardless of the weather condition and
day-night condition. SAR system is usually loaded on flight
vehicle such as satellite or aerial vehicle and as it moves along
the flight path it transmits and receives microwave to perform
its mission. When evaluating the performance of radar system,
the resolution is a dominant factor. Resolution means the
capability of a detecting system to distinguish between two
adjacent targets. The resolution of SAR image depends on the
transmit signal characteristics. Commonly, radar system
transmits pulse-train type microwave signal, and larger the
bandwidth of signal and narrower the pulse width, sensor gets
higher resolution. However, there are limitations on designing
the system, hence SAR system adopts the signal called chirp.
The chirp is a kind of frequency modulation signals and the
instantaneous frequency of chirp increases or decreases as the
time increases. The characteristic of chirp is that it can enlarge
the bandwidth then consequently it can acquire higher
resolution than non-modulated signal. By the reason that SAR
system needs large bandwidth to acquire high-resolution, it
adopts chirp signal.
When designing the signal generator of space-borne SAR
systems, the size, weight, space, and etc. of payload are
considered to be as smaller as possible. Usually analog chirp
signal generator is equipped with heavy and large components
such as workstation, analog signal generator, and etc. To
minimize the size and weight of SAR payload, various digital
chirp generators are introduced in [1]-[4]. Compared to analog
chirp generators, digital types are free from work station which
occupies large portion in chirp generator system. In this paper,
implementation of chirp generator on FPGA (field
programmable gate array) will be discussed. First, the
characteristics of chirp signal will be explained, then the types
of digital chirp generator will follow.
II. CHARACTERISTICS OF CHIRP SIGNAL
A. Definition of Chirp Signal
Resolution is an important factor of radar performance
evaluation and (1) indicates the resolution of radar systems
/2rc B

(1)
Where c and B mean the speed of light (m/s) and the
bandwidth of signal (Hz) respectively. Smaller the value r,
higher the performance of resolution, imaging radar systems
such as SAR are aiming to provide large bandwidth. However,
if the bandwidth of radar signal is large, the signal power also
get larger, then the system needs more power and size so the
SAR system use chirp signal. Chirp signal is a kind of linear
frequency modulation (LFM), and the frequency of signal
increases and decreases according to time. The equation of
chirp signal is in (2),


2
exp 2
t
x
t rect A j Kt
T



 (2)
Where T is pulse duration of rectangular waveform, A and K
are amplitude of signal and chirp rate respectively. The
polynomial inside the exponential term in (2) indicates the
phase component of signal and can be presented as (3).


2
tKt

 (3)
When expressing the phase of signal in frequency term, the
derivative form of (3) is used and expressed as (4).

Constant
Source
Frequency
Accumulator
Phase
Accumulator
Sin ROM Chirp Pulse
Output
Time integration Time integration
Figure 1. Functional block of DDS chirp generator
Frequency
Register
Phase
Register
Phase to
Amplitude
Converter
(Sin ROM)
D/A
Converter Filter
Phase Accumulator
Figure 2. Structure of DDS chirp generator
Chirp
Pulse
Output
90°
Phase
Shifter
HPA
Output
LPF
LPF
I data
Q data
LO
Figure 3. I and Q data generation in DDS chirp generator
TABLE I. DEVELOPMENT SPECIFICATION OF FPGA CHIRP GENER ATOR
 
11
2
22
dt
K
tKt
dt



(4)
(4) indicates that frequency of chirp signal varies linearly as
the time increases. By doing so, chirp signal can acquire the
bandwidth of Kt.
B. Types of Chirp Generator
Commonly there are two types of digital chirp generator
(CG): memory-based type and direct digital synthesizer (DDS)
type [5]. Memory-based CG save the chirp waveform in
advance and loads the saved signal. As this type loads already
saved waveform, the signal generator is quite easy and the
accuracy of signal is relatively higher than DDS type CGs.
However, when it needs to load the signal different from saved
signal, the configuration of CG is complicated. The
characteristics chirp signal such as PRI (pulse repetition
frequency) and PRF (pulse repetition frequency) vary when the
detection modes of SAR change, but when it is needed to
provide all the types of signal, memory-based CG requires
large amount of memory. When memory-based CG is
implemented space-borne SAR system, it occupies large space
in payload and it means the hardware characteristics of
memory-based CG are not suitable for space-borne SAR
especially for small satellites. Also, the memory components
are easily broken in space orbit and the electric components are
limited in space mission.
DDS type CG is introduced to overcome the weak points of
memory-based CG. DDS CG separates the whole waveform
little by little and then loads the stored fraction of waveform
according to the clock frequency. The system structure of DDS
type CG is depicted in Figure 1 [4]. The constant source
generates the chirp rate K then CG integrates it with time, then
the frequency component is expressed same as (4) in frequency
accumulator. Time-integrated component is integrated again,
then it becomes the phase which is expressed as (3). Finally
CG system loads the amplitude of pulse in Sin ROM according
to the signal phase. Due to the fact this system needs less
memory than memory-based CG, the hardware size can be
smaller. Moreover the signal configuration is a lot easier than
memory-based CG. Table 1 show the comparison between
analog type CG and digital CG.
C. Structure of DDS Chirp Signal Generator
The structure block diagram of DDS chirp generator is
presented in Figure 2. As the signal pass through frequency
register and phase register, sample index is counted with clock
frequency. Phase accumulator output makes linear ramp
function increasing with time. Next, there is phase to amplitude
converter called Sin ROM. Each phase component in phase
accumulator output is converted into signal amplitude then the
output signal shapes sine function. To utilize the chirp signal,
Sin ROM signal is processed in D/A converter. Sine pulse
shape signal is digitized with clock frequency.
Chirp signal (2) can be expressed with sinusoidal function
as below using Euler’s formula.

 
22
sin cos
t
x
t rect A Kt j Kt
T




 (5)
In (4), there are real part and imaginary part terms. Sine and
cosine terms present real and imaginary parts respectively and
System requirements Analog type Digital type
FM noise Low Low
Frequency response High Very high
Linearity Good Very good
System complexity Low High
Digital compatibility Impossible Possible

Figure 4. Pulse output of chirp generator (I data, Q data, and phase of chirp signal)
System requirements Specification
Bandwidth 10 MHz
Pulse width 30 us
Reference clock 100 MHz
Length of phase accumulator 16-bit
Chirp rate 0.3 MHz/us
TABLE II. DEVELOPMENT SPECIFICATION OF FPGA CHIRP GENE RATOR
Figure
3
.
I and Q data generation in DDS chirp generator
each term is called I and Q data respectively. Figure 4 shows I
and Q data generation in DDS chirp generator. Output in
Figure 3 is drawn out in chirp pulse output of Figure 3. Two
chirp pulse output pass through LPF (low-pass filter) to get rid
of harmonic components. To modulate the signal from
baseband, LO (local oscillator) oscillates the signal. Then, on
of the filtered signals is modulated by 90° with phase shifter.
This process separates I and Q data. Finally, HPA (high-power
amplifier) amplifies I and Q data respectively. With a series of
signal processing, chirp signal can be made with DDS chirp
generator.
III. DDS CHIRP GENERATOR IMPLEMENTATION ON FPGA
Chapters above explain about the definition of chirp signal
and signal generation using DDS chirp generator. In this
chapter, characteristics of FPGA and performance of FPGA
based chirp generator will be drawn out.
A. Characteristics of FPGA
FPGA is acronym of field programmable gate array and it
has high-speed processing capability. Moreover with the help
of light weight and small size, it is widely used in many areas.
We adopted FPGA to minimize the system size that will be
used in small satellite (< 100kg) because payload in small
satellite is limited by around 25-35kg. Also, it can be driven
with lower power and switching speed is faster.
B. Simulation Output of Chirp Generator
Chirp pulse output and system development requirements
are presented in Figure 4 and Table 2 respectively. Bandwidth
of signal is set to 10MHz and with (1) resolution using this
chirp generator is 15m then it is suitable value for SAR system.
Signal on top indicates the I data of chirp pulse. As the I data is
defined with sine function, the signal shape is similar to sine
graph. The frequency of signal decreases from starts to center
and increases again. If the frequency of chirp increases
according to time, it is called up-chirp and in opposite case, it is
called down-chirp. The signal in Figure 4 is called down and
up-chirp. As the instantaneous frequency increases, there are
some aliasing but if the oversampling rate is set 1.2, this
problem would disappear. Signal in middle indicates Q data of
chirp pulse and it also has a shape of cosine wave. The bottom
graph in Figure 4 presents the phase of chirp signal. Phase
component of chirp is expressed as quadratic term following
(3) and this figure shows that the FPGA-base DDS chirp
generator has high linearity.
C. FPGA-based Chirp Generator
To realize the DDS chirp pulse, chirp signal is implemented
on FPGA board. Altera DE2-115 board is used and realized
using Verilog language. Output from FPGA is presented in
Figure 5. Also in FPGA output, aliasing can be seen in both I

and Q data. Instantaneous frequency is decreasing and
increasing linearly and when inspecting the signal from the
center, it is shown that signal is symmetric so that there is no
phase lagging error in this chirp signal.
IV. CONCLUSION
In this paper, the characteristics, the waveform of FPGA-
based chirp signal generator, and development of chirp
generator are explained. First, to realize the DDS chirp signal,
simulation is done on Simulink. Then using Verilog with
Altera DE2-115 board, we drive the FPGA platform and
implemented with DDS type signal generator utilizing tuning-
word LUT (look up table) and phase LUT. In case of analog
type chirp generator, it needs waveform generator and
workstation however FPGA-based has light weight and small
size so that it is suitable for to be implemented to small satellite.
In the respect of signal characteristics, FPGA-based DDS chirp
signal has high linearity. Only baseband characteristic is
examined in this paper, so further research will be verification
of FPGA-based chirp generator in RF stage. Also, there are
some error truncation error and insufficiency of Sin ROM
memory due to the lack of bit number. The method to realize
and verify the chirp pulse in RF stage is needed. Next, error
occurred when using DDS method is needed to be checked to
compensate it to be used in actual SAR system.
ACKNOWLEDGMENT
This research was supported by NSL (National Space Lab)
program through the National Research Foundation of Korea
funded by the Ministry of Education, Science and Technology
(2012-0009092) and KARI (Korean Aerospace Research
Institute) though the Ministry of Science, ICT and Future
Planning.
REFERENCES
[1] A. Meta, O. Hoogeboom, L. P. Ligthart, “Signal Processing of FMCW
SAR”, Trans. on IEEE Geoscience and Remote Sensing, Vol. 45, No. 11,
2007, pp. 3519-3531.
[2] G. Eason, B. Noble, and I. N. Sneddon, “On certain integrals of
Lipschitz-Hankel type involving products of Bessel functions,” Phil.
Trans. Roy. Soc. London, vol. A247, pp. 529–551, April 1955.
(references)
[3] J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol.
2. Oxford: Clarendon, 1892, pp.68–73.
[4] I. S. Jacobs and C. P. Bean, “Fine particles, thin films and exchange
anisotropy,” in Magnetism, vol. III, G. T. Rado and H. Suhl, Eds. New
York: Academic, 1963, pp. 271–350.
[5] K. Elissa, “Title of paper if known,” unpublished.
[6] R. Nicole, “Title of paper with only first word capitalized,” J. Name
Stand. Abbrev., in press.
[7] Y. Yorozu, M. Hirano, K. Oka, and Y. Tagawa, “Electron spectroscopy
studies on magneto-optical media and plastic substrate interface,” IEEE
Transl. J. Magn. Japan, vol. 2, pp. 740–741, August 1987 [Digests 9th
Annual Conf. Magnetics Japan, p. 301, 1982].
[8] M. Young, The Technical Writer's Handbook. Mill Valley, CA:
University Science, 1989.