Analytical comparison between capacitor assisted and diode assisted cascaded quasi-Z-source inverters

Abstract

The quasi-Z-source inverter is a very attractive topology because of its unique capability of voltage boost and buck functions in a single stage. But its voltage boost property could be a limiting feature in some applications where very high input voltage gain is required. The input voltage gain could be extended by the implementation of the cascaded quasi-impedance network. This paper discusses four novel cascaded quasi-Z-source inverters. Steady state analysis of topologies operating in continuous conduction mode is presented. Performances of topologies were compared and experimentally validated. Moreover, some problematic issues of proposed topologies were pointed out and discussed.

Full text

212 PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 1a/2012
Dmitri VINNIKOV1, Indrek ROASTO1, Tanel JALAKAS1, Ryszard STRZELECKI2,3, Marek ADAMOWICZ2,4
Tallinn University of Technology (1), Gdynia Maritime University (2), Electrotechnical Institute (3), Gdańsk University of Technology (4)
Analytical Comparison between Capacitor Assisted and
Diode Assisted Cascaded Quasi-Z-Source Inverters
Abstract. The quasi-Z-source inverter is a very attractive topology because of its unique capability of voltage boost and buck functions in a single
stage. But its voltage boost property could be a limiting feature in some applications where very high input voltage gain is required. The input voltage
gain could be extended by the implementation of the cascaded quasi-impedance network. This paper discusses four novel cascaded quasi-Z-source
inverters. Steady state analysis of topologies operating in continuous conduction mode is presented. Performances of topologies were compared
and experimentally validated. Moreover, some problematic issues of proposed topologies were pointed out and discussed.
Streszczenie. Quasi-Z falownik z prostym obwodem impedancyjnym jest bardzo interesującym rozwiązaniem topologicznym ze względu na
unikalną możliwość jednostopniowego przekształcanie DC/AC w połączeniu z funkcjami obniżania i podwyższania napięcia. W niektórych
aplikacjach jego właściwości podwyższające są jednak niewystarczające. Wyższe napięcie wejściowe można uzyskać w wyniku zastosowania w
quasi-Z-falownikach kaskadowych obwodów impedancyjnych. W artykule omówiono cztery nowe topologie kaskadowych quasi-Z-falowników.
Przedstawiono wyniki analizy stanów statycznych tych układów przy przewodzeniu ciągłym. Porównano właściwości badanych topologii,
zweryfikowane eksperymentalnie. Omówiono także inne problemy związane z proponowanymi układami. (Porównanie analityczne układów
kaskadowych quasi-Z-falowników z kondensatorem wspomagającym i z diodą wspomagającą).
Keywords: quasi-Z-source inverter (qZSI), PWM converter, continuous conduction mode (CCM), discontinuous conduction mode (DCM).
Słowa kluczowe: quasi-Z-falownik, przekształtnik PWM, tryb przewodzenia ciągłego, tryb przewodzenia impulsowego
Introduction
Quasi-Z-source inverter (qZSI) is a new promising
power conversion technology perfectly suitable for
interfacing of renewable (i.e., photovoltaic, wind turbines)
and alternative (i.e., fuel cells) energy sources [1-3]. The
qZSI has the following advantages:
 boost-buck function by the one-stage conversion;
 continuous input current (input current never drops
to zero, thus featuring the reduced stress of the
input voltage source, which is especially topical in
such demanding applications as power
conditioners for fuel cells and solar panels);
 excellent reliability due to the shoot-through
withstanding capability;
 low or no in-rush current during start up;
 low common-mode noise.
However, the efficiency and voltage gain of the qZSI are
limited and comparable with the conventional system of a
voltage source inverter with the auxiliary step-up DC/DC
converter in the input stage [4]. The concept of extending
the qZSI gain without increasing the number of active
switches was recently proposed by several authors [5-8].
These new converter topologies are commonly referred to
as the cascaded qZSI or extended boost qZSI and could be
generally classified as capacitor assisted (CA) and diode
assisted (DA) topologies [5]. In this paper four different
cascaded qZSIs with continuous input current will be
presented, analyzed and compared. Moreover, some
problematic issues of these converters will be pointed out
and discussed.
Cascaded qZSIs – Basic Topologies
It should be noted here that this paper provides a
general coverage of the cascaded voltage-fed qZSIs with
continuous input current. All the topologies to be discussed
and analyzed have a common property - the input inductor
L1 that buffers the source current. It means that during the
continuous conduction mode (CCM) the input current of the
converter never drops to zero, thus featuring the reduced
stress of the input voltage source.
Capacitor Assisted Cascaded qZSI
The investigated topologies are presented in Fig. 1. The
basic topology of a capacitor assisted cascaded qZSI (CAC
qZSI, Fig. 1a) could be derived by the adding of one diode
(D2), one inductor (L3) and two capacitors (C3 and C4) to the
traditional qZSI with continuous input current [6-8].
a)
b)
Fig. 1. Capacitor assisted cascaded qZSI topologies: basic CAC
qZSI (a) and MCAC qZSI (b).
a)
b)
Fig. 2. Diode assisted cascaded qZSI topologies: basic DAC qZSI
(a) and MDAC qZSI (b).

PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 1a/2012 213
(3)
The modified topology of a capacitor assisted cascaded
qZSI (MCAC qZSI) could be derived from the CAC qZSI
simply by the changing of the connection points of
capacitors C2 and C3, as shown in Fig. 1b.
Diode Assisted Cascaded qZSI
The investigated topologies are presented in Fig. 2. The
basic topology of a diode assisted cascaded qZSI (DAC
qZSI, Fig. 2a) could be derived by the adding of one
capacitor (C3), one inductor (L3) and two diodes (D2 and D3)
to the traditional qZSI with continuous input current. The
modified topology of a diode assisted cascaded qZSI
(MDAC qZSI) could be derived from the DAC qZSI simply
by the changing of the connection points of the capacitor
C3, as shown in Fig. 2b.
Steady State Analysis of Cascaded qZSIs
Generally, the topologies shown in Figs. 1 and 2 could
be represented by the PWM inverter coupled with the
cascaded qZS-network. In the same manner as the
traditional qZSI, the cascaded qZSI has two types of
operational states at the dc side: the non-shoot-through
states (i.e., the six active states and two conventional zero
states of the traditional three-phase voltage source inverter)
and the shoot-through state (i.e., both switches in at least
one phase conduct simultaneously) [7]. To simplify the
analysis the inverter bridge was replaced by a switch S
(Fig. 3). When the switch S is closed, the shoot-through
state occurs and the converter performs the voltage boost
action. When the switch S is open, the active (non-shoot-
through) state emerges and previously stored magnetic
energy in turn provides the boost of voltage seen on the
load terminals.
Fig. 3. Simplified power circuit of the cascaded qZSI used in the
analysis.
The operating period of the qZS-converter in the CCM
generally consists of a shoot-through state tS and an active
(non-shoot-through) state tA:
(1) SA ttT  .
Equation (1) could also be represented as
(2) 1 SA
SA DD
T
t
T
t
,
where DA and DS are the duty cycles of an active and
shoot-through states, correspondingly.
Capacitor Assisted Cascaded qZSI
Fig. 4 shows the equivalent circuits of the CAC qZSI
operating in the CCM for the shoot-through (a) and active
(b) states. At the steady state the average voltage of the
inductors over one operating period is zero:
0
11  
Tt
t
LL dtuU ; 0
22  
Tt
t
LL dtuU ;
0
33  
Tt
t
LL dtuU .
Based on that fact and defining the shoot-through duty
cycle as DS and the non-shoot-through duty cycle as (1-DS),
the inductors’ voltages over one operating period could be
represented as
(4)

  


 











01
01
01
01
4333
311422
241422
1211
CSCSLL
CCSCCSLL
CCSCCSLL
CINSCINSLL
UDUDuU
UUDUUDuU
UUDUUDuU
UUDUUDuU
.
The peak DC-link voltage is
(5)
S
INDC D
Uu
31
1
ˆ
.
The boost ratio of the input voltage is
(6)
SIN
DC
DU
u
B
31
1
ˆ

 .
(a)
(b)
Fig. 4. Equivalent circuits of the CAC qZSI: during the shoot-
through state (a) and during the active state (b).
Fig. 5 shows the equivalent circuits of the MCAC qZSI
operating in the CCM for the shoot-through (a) and active
(b) states.
(b)
(b)
Fig. 5. Equivalent circuits of the MCAC qZSI: during the shoot-
through state (a) and during the active state (b).
Based on (3) and defining the shoot-through duty cycle
as D
S and the non-shoot-through duty cycle as (1-DS), the
inductors’ voltages over one operating period could be
represented as

214 PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 1a/2012
(7)















01
01
01
01
41333
31422
21422
14211
CSCCSLL
CSCCSLL
CSCCSLL
CINSCCINSLL
UDUUDuU
UDUUDuU
UDUUDuU
UUDUUUDuU
.
The peak DC-link voltage is and the boost ratio of the
input voltage of the MCAC qZSI is exactly the same as of
the CAC topology (Eqs. (5) and (6), correspondingly).
Diode Assisted Cascaded qZSI
Fig. 6 shows the equivalent circuits of the DAC qZSI
operating in the CCM for the shoot-through (a) and active
(b) states.
C2C1
L1L2
UIN
iL1
iIN
iL2
iD1=0
R0
C0
L0
I0
uDC=0
D1L3
+
D2
iD2=0
+
+
+
C3
+
iL3
+
uD3=0
D3
iD3
(a)
(b)
Fig. 6. Equivalent circuits of the DAC qZSI: during shoot-through
state (a) and during the active state (b).
Based on (3) and defining the shoot-through duty cycle
as D
S and the non-shoot-through duty cycle as (1-DS), the
inductors’ voltages over one operating period could be
represented as
(8)

  
  








01
01
01
213333
31122
1211
CCCSCSLL
CCSCSLL
CINSCINSLL
UUUDUDuU
UUDUDuU
UUDUUDuU
.
The peak DC-link voltage is
(9) 13
1
ˆ2

SS
INDC DD
Uu .
The boost ratio of the input voltage is
(10) 13
1
ˆ
2

SS
IN
DC
DD
U
u
B.
Fig. 7 shows the equivalent circuits of the MDAC qZSI
operating in the CCM for the shoot-through (a) and active
(b) states. Based on (3) and defining the shoot-through duty
cycle as DS and the non-shoot-through duty cycle as (1-DS),
the inductors’ voltages over one operating period could be
represented as
(11)

  









01
01
01
231333
3122
1211
CCSCCSLL
CSCSLL
CINSCINSLL
UUDUUDuU
UDUDuU
UUDUUDuU
.
The peak DC-link voltage is and the boost ratio of the
input voltage of the MDAC qZSI is exactly the same as of
the DAC topology (Eqs. (9) and (10), correspondingly).
(a)
(b)
Fig. 7. Equivalent circuits of the MDAC qZSI: during the shoot-
through state (a) and during the active state (b).
Comparison of Operating Properties of Different
Cascaded qZSI Topologies
Voltage boost properties
Generally, capacitor assisted and diode assisted
cascaded qZSIs have common advantages, such as
continuous input current and increased boost factor of the
input voltage for the same value of the shoot-through duty
cycle as with the traditional qZSI [1-3]. Moreover, in the
lossless approach the CAC and MCAC qZSIs could ensure
up to 1.25 times higher boost than that of DAC and MDAC
topologies (Fig. 8).
1
2
3
4
0 0,05 0,1 0,15 0,2 0,25
InputvoltageboostratioB
Shoot‐throughdutycycleD
S
TraditionalqZSI CACandMCACqZSI
DACandMDACqZSI
Fig. 8. Comparison of idealized boost properties of capacitor
assisted and diode assisted cascaded qZSIs
Operating voltages of capacitors in qZS-networks
The central idea of the modified cascaded qZSIs is to
reduce the operating voltages of capacitors in the qZS-
network. Thus, by changing the interconnection points of
capacitors C2 and C3 (as shown in Fig. 1b) the CAC qZSI
could be easily transformed to the MCAC qZSI, which will
feature significantly reduced voltage of capacitor C3.
Moreover, the voltages of capacitors C2…C4 will be
equalized. In the similar way, simply by changing the
connection points of the capacitor C3 of the DAC qZSI (see
Fig. 2b) its operating voltage could be decreased by more
than six times. The average values of capacitor voltages in
different cascaded qZSIs are compared in Table 1.

PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 1a/2012 215
Table 1. Average voltages of capacitors in different cascaded qZSIs
Analysis of Simulation Results
To verify theoretical assumptions a number of
simulations were performed by the help of PSIM simulation
software. The proposed cascaded qZSI topologies were
evaluated with the switching frequency f=30 kHz and shoot-
through duty cycle DS=0.167. The input voltage was set at
30 V and the load resistor selected was 5 Ω. To simplify the
analysis losses in the components were neglected.
Capacitors and inductors selected for the qZS-networks
have the following parameters:
L1…L3 = 65 uH;
C1…C4 = 180 uF.
Capacitor Assisted Cascaded qZSIs
Fig. 9 shows the general operating waveforms of the
CAC and MCAC qZSI topologies. As expected, both
converters operate normally, producing twofold boost of the
input voltage (UIN=30 V, UDC=60 V, Figs. 9a and 9b).
Moreover, both topologies ensure the continuous input
current (Fig. 9a) in the CCM.
(a)
(b)
Fig. 9. Simulated waveforms of the CAC and MCAC qZSIs: input
voltage and current (a) and DC-link voltage and current (b).
Fig. 10 shows the operating voltage profiles of
capacitors in CAC and MCAC qZSIs. The average values of
capacitor voltages are compared in Table 2. It shows that
by changing the interconnection points of capacitors C2 and
C3, as in Fig. 1b, the operating voltage of the capacitor C3
was reduced by five times. Moreover, the voltages of
capacitors C2…C4 are equalized now.
(a)
(b)
Fig. 10. Capacitor voltages: CAC qZSI (a) and MCAC qZSI (b).
Table 2. Comparison of average voltages of capacitors in CAC and
MCAC qZSIs
Capacitors Average operating voltages
CAC qZSI MCAC qZSI
C1 39.9 V 40.4 V
C2 19.8 V 9.8 V
C3 49.6 V 9.8 V
C4 10.1 V 10.3 V
Diode Assisted Cascaded qZSIs
Fig. 11 shows the general operating waveforms of the
DAC and MDAC qZSIs. Both converters operate normally,
producing the demanded boost of the input voltage
(UIN=30 V; UDC=57 V, Figs. 11a and 11b). As expected,
both topologies ensure the continuous input current
(Fig. 11a) in the CCM.
Fig. 12 shows the operating voltage profiles of
capacitors in DAC and MDAC qZSI topologies. The average
values of capacitor voltages are compared in Table 3. It
shows that by changing the interconnection points of the
capacitor C3 (Fig. 2b), its operating voltage could be
decreased by more than six times.
Table 3. Comparison of average voltages of capacitors in DAC and
MDAC qZSIs
Capacitors Average operating voltages
DAEB qZSI MDAEB qZSI
C1 39.5 V 39.5 V
C2 17.2 V 17.4 V
C3 47.4 V 7.7 V
Capacitors Average voltage, V
CAC qZSI MCAC qZSI DAC qZSI MDAC qZSI
C1
S
S
IN D
D
U
31
21


S
S
IN D
D
U
31
21


13
12
2
2


SS
SS
IN DD
DD
U
13
12
2
2


SS
SS
IN DD
DD
U
C2
S
S
IN D
D
U
31
2

S
S
IN D
D
U
31 
13
2
2
2


SS
SS
IN DD
DD
U
13
2
2
2


SS
SS
IN DD
DD
U
C3
S
S
IN D
D
U
31
1


13
1
2

SS
S
IN DD
D
U
13
2
2


SS
SS
IN DD
DD
U
C4
S
S
IN D
D
U
31  -------- --------

216 PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 1a/2012
(a)
(b)
Fig. 11. Simulated waveforms of the DAC and MDAC qZSIs: input
voltage and current (a) and DC-link voltage and current (b)
(a)
(b)
Fig. 12. Capacitor voltages: DAC qZSI (a) and MDAC qZSI (b).
In Fig. 13 the operating waveforms of the diode D3
(see Fig. 2 for details) are presented. It is shown that for the
discussed application the low-voltage low-power fast
recovery or the Schottky diode could be used.
Fig. 13. Operating voltage and current of diode D3.
Experimental Results
In order to verify theoretical assumptions the laboratory
setups corresponding to the investigated topologies were
assembled. 600 V/200 A IGBT with extra low saturation
voltage was selected for S (Fig. 3). Components used in the
qZS-networks had the following properties:
L1…L3 = 50 uH; RL=3 mΩ; type: toroidal inductors;
C1…C4 = 180 uF; type: polypropylene capacitors;
D1…D3 = 100 V/80 A power Schottky diodes.
In the first experiment, main operating waveforms of the
proposed topologies were acquired and compared. The
shoot-through duty cycle was set at 0.167. As seen from
Fig. 14b, due to the losses in the components of the qZS-
network both of the capacitor assisted topologies could
provide only a 90% of a theoretically predicted input voltage
gain (DC-link voltage amplitude 54 V instead of 60V). In the
case of diode assisted topologies (Fig 15b) the practical
voltage gain for the same operating conditions was reduced
by 9% in comparison with the theoretically predicted (DC-
link voltage amplitude 52 V instead of 57 V).
(a) (b)
Fig. 14. Experimental waveforms of input voltage and current (a)
and DC-link voltage and current (b) of the CAC and MCAC qZSIs.
(a) (b)
Fig. 15. Experimental waveforms of input voltage and current (a)
and DC-link voltage and current (b) of the DAC and MDAC qZSIs.
During the second experiment the boost properties of
the proposed topologies were experimentally verified and
compared with theoretical results. In the conditions of fixed
input voltage (30 V) and constant load (5 Ω), the shoot-
through duty cycle of the converters was increased step by
step from 0 to 0.25.
30
60
90
120
0 0 ,05 0,1 0,15 0,2 0,25
DC‐linkvoltageU
DC
[V]
Shoot‐throughdutycycleD
S
CACandMCAC(experimental) DACandMDAC(experimenta l)
CACandMCAC(theoretical) DACandMDAC(theoretic al)
Fig. 16. Theoretical and practical boost properties of the proposed
topologies.
Fig. 16 shows that all of the presented topologies suffer
from the boost factor reduction, which is mostly caused by
the losses in the inductors and diodes of the qZS-network
as well as by voltage drops in the interconnection wires. In
order to achieve higher possible voltage gain and efficiency
these problematic issues should be first addressed during
the design routine of cascaded qZSIs. Another interesting
UIN(10V/div)
IIN
(
10A/div)
UIN
(
10V/div)
IIN(10A/div)
UDC(25V/div)
IDC
(
20A/div)
UDC
(
25V/div)
IDC
(
20A/div)

PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 88 NR 1a/2012 217
fact is that all four topologies have demonstrated identical
boost properties within the shoot-through duty cycle range
of 0…0.15, which could be considered during proper
topology selection for different applications.
Due to the presence of the input inductor L1 all the
proposed topologies feature the continuous input current in
the CCM, as predicted in the analysis. It means that in the
CCM the input current never drops to zero during the shoot-
through states, thus featuring the reduced stress of the
input voltage source, which is especially topical in such
demanding applications as power conditioners for fuel cells
and solar panels. However, in the case of small loads,
relatively low switching frequency and low inductance
values of L1…L3 the proposed converters could start to
operate in the discontinuous conduction mode (DCM) and
the input current falls to zero during some part of the
switching period. This DCM operating mode causes the
overboost effect of the DC-link voltage, which can lead to
instabilities of the converter and must also be taken into
account during the sizing of converter components.
To demonstrate the overboost effect of the DC-link
voltage the proposed topologies were tested in light load
operating conditions when the DCM occurs. The converter
was loaded by a 33 Ω resistor and the shoot-through duty
cycle was increased step by step from 0 to 0.25. The results
of the experiment are presented in Fig. 17. It was stated
that the overboost effect is most pronounced in the DAC
and MDAC qZSIs with the shoot-though duty cycle DS lying
in the range from 0.04 to 0.24 (Fig. 17b). In the case of
CAC and MCAC qZSIs the maximal voltage overboost was
11% from that theoretically predicted while in the case of
DAC and MDAC qZSIs the maximum overboost reached
was 20%. In practice, this undesirable effect can be
compensated with appropriately chosen inductances and
switching frequencies.
30
50
70
90
110
0 0,05 0,1 0,15 0,2 0,25
DC‐linkvoltageU
DC
[V]
Shoot‐throughdutycycleD
S
ExperimentalIdealized
DCMoperation
(a)
30
50
70
90
110
0 0,05 0,1 0,15 0,2 0,25
DC‐linkvoltageU
DC
[V]
Shoot‐throughdutycycleD
S
Experimental Ideal ized
DCMoperation
(b)
Fig. 17. Transition from CCM to DCM operation: CAC and MCAC
qZSIs (a); DAC and MDAC qZSIs (b).
Conclusions
In this paper four cascaded qZSI topologies were
proposed, discussed and compared. These topologies were
classified as capacitor assisted and diode assisted. A
steady state analysis of topologies operating in the
continuous conduction mode was performed. Theoretical
study was validated by the simulations and experiments.
Moreover, some problematic issues of proposed topologies
were pointed out and discussed.
It was experimentally stated that in similar operating
conditions the discussed topologies provide an identical
boost factor of the input voltage within the shoot-through
duty cycle range of 0…0.15. Thanks to the presence of the
input inductor L1 all the discussed cascaded qZSIs have
continuous input current in the CCM, thus featuring the
reduced stress of the input voltage source.
This research work has been supported by Estonian
Ministry of Education and Research (Project
SF0140016s11), Estonian Science Foundation (Grant
ETF8538) as well as by Estonian Academy of Sciences and
Polish Academy of Sciences.
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Authors: Dr. Sc. techn. Dmitri Vinnikov, Senior Researcher,
Tallinn University of Technology, Ehitajate str. 5, 19086 Tallinn,
Estonia, E-mail: dmitri.vinnikov@ieee.org; PhD Indrek Roasto,
Senior Researcher, Tallinn University of Technology, Ehitajate str.
5, 19086 Tallinn, Estonia, E-mail: indrek.roasto@ttu.ee; PhD Tanel
Jalakas, Senior Researcher, Tallinn University of Technology,
Ehitajate str. 5, 19086 Tallinn, Estonia, E-mail:
tanel.jalakas@ieee.org; Prof. Ryszard Strzelecki, Gdynia Maritime
University, 81-87 Morska Str., 81-225 Gdynia / Electrotechnical
Institute, 28 Pożaryskiego Str, 04-703 Warszawa, Poland, E-mail:
rstrzele@am.gdynia.pl; PhD Marek Adamowicz, Researcher,
Gdynia Maritime University, 81-87 Morska str., 81-225 Gdynia,
Poland, E-mail: madamowi@am.gdynia.pl.