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High-Speed Mixed Signal ASIC Design
1
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
SEI-Frühjahrstagung
7.-9.04.2008
Forschungszentrum Karlsruhe (FZK)
in der Helmholtz-Gemeinschaft,
Institut für Prozessdatenverarbeitung und Elektronik (IPE)
High-Speed Mixed-Signal
ASIC Design
Hassan Safdary, Günter Grau
hs@advico.de
+49(0)2361/90438-73
High-Speed Mixed Signal ASIC Design
2
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
About advICo
Introduction
ASIC Design Styles & Design Flow
Standard Cell Design
Structured ASIC
Mixed-Signal ASIC Design
Presentation Overview:
High-Speed Mixed Signal ASIC Design
3
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
advICo is an IC Design House
located in Recklinghausen,Germany
Chip Design:
EDA Software:
Core
competences:
➔
Design Kit Development
and Support
➔
SiGe BiCMOS and CMOS
(0.25-0.13µm)
➔
tool Development
(Cadence, AWR)
➔
IC Design Services
(Mixed-Signal Analog IP/
broadband/RF)
➔
HDL-Based System
Design
➔
Multi project Wafer (MPW)/
Prototyping service/
Measurement
High-Speed Mixed Signal ASIC Design
4
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Software costs overtakes total hardware costs at 130nm
source:STMicroelectronics
part of Architecture overtakes physical design at 90nm
●
Introduction
Relative Effort by Designer Role (e.g. SOC)
High-Speed Mixed Signal ASIC Design
5
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Chosen Design Styles depends on:
Cost & Risk
e.g. Non-Recurring Engineering (NRE)
Time-to-Market
(TTM)
Performance,
Power
Area
Reliability
Quality and IP-
Intergration
ASIC
High-Speed Mixed Signal ASIC Design
6
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
ASICs
Field
programmable
FPGA
Full
Custom
Semi
Custom
Standard-
Cell
ASIC Design Styles:
Full- Custom ASICs:
All mask layers are customized
Highest performance
Lowest power consumption
Optimum of area
Lowest per-unit cost
Structured
ASIC
Gate-
Arrays
Cell-based ASIC
Standard Cell ASIC (SC ASICs)
High-Speed Mixed Signal ASIC Design
7
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Full custom
Standard Cell
Gate array
FPGA
Structured
ASIC
Density
Performance
Flexibility
Manufacturing
-
time
Unit cost-
same quantity
Unit cost-
large quantity
Very high
Very high
Very high
Very long
Very high
Low
High
High
High
High
Low
High
High
Design time
Medium
Short
Medium
Medium
Short
Short
High
Low
Medium
Medium
Low
Very short
Very short
Low
High
Medium
High
high
short
Very short
Medium
Low
Comparison of Design Styles:
High-Speed Mixed Signal ASIC Design
8
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Structural
Behavioural
Physical
Transistor
Device, gate
Cell
ALU, registers
Processor,memory
Transfer function
Boolean equation
Module
State machine
Program
Masks
Gate
Functional unit
Macro
IC
Architectural
Algorithmic
Functional
Logic
Circuit
Design-Strategy in “Y-Diagram”:
High-Speed Mixed Signal ASIC Design
9
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Standard-cell-based Design Flow:
HDL entry
Schematic entry
Transistor
simulation
Layout design
Timing-Models
Test Models
Layout rules
Verification
Specification
Design
Logic simulation
Boolean compare
LVS
DRC
Parasitic extraction
source: IBM
Behavioral
Structural
Physical
High-Speed Mixed Signal ASIC Design
10
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Row of standard cells with same height,
fixed I/O, on grid (“abutment”).
^
output
input
crtl
Routing Channels
Routing Channels
Gnd
Gnd
vee
ve
e
Standard cell Design:A library of pre-characterized cells
which customer can use to implement own design.
Benefit:
- Lower Risk
- Performance
- Power
- Capacity
- IP Integration
- Verified (Timing..)
Drawback:
- NRE-Cost
- Time to market
power rails vee,gnd
Cooperation: IHP microelectronics, FH-Brandenburg, Humboldt University,
advICo microelectronics
High-Speed Mixed Signal ASIC Design
11
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Pseudo-Random Binary Sequence Generator (PRBS)
ECL-Standard cells
same height,
varying width
VDD-Line of
upper cell and
bottom cell
GND-line
(upper cell)
GND-Line
(bottom cell)
ESD-Protection
GND-Ring
836.4u
426.3u
•
Verification of Design specification
(T, fmax, Timing, Jitter, swing, ...)
•
Verification of Design specification
depending on marginal conditions (MIN,
TYP, MAX)
•
Measurement of VDD-/GND -Drop
and therewith the effect on
Power-Grid respectively its max. length
and min. line width
Test Chip for:
High-Speed Mixed Signal ASIC Design
12
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
An application example:Components of Fiber Optic Transceiver
MUX
Retimer
FF
Frequency
synthesizer
PLL
Divider
Decision
Circuit
FF
Clock
Recovery
Divider
DMUX
Laser
Driver
Laser
Driver
Receiver
Transmitter
input
output
Amplifier (TIA)
Automatic gain
control (AGC)
Power control
Limiter
....
....
High-Speed Mixed Signal ASIC Design
13
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Structured ASIC:Alternative architecture structured ASIC
Hard IP:standard I/O and Interface
(Pads, power rails,Buffer, ECL to CMOS...
Corner cell
Firm IP: High-level function, optimally
mapped, placed, routed
(Clock Tree, RAM...
Soft IP:source-level library of
high-level function , designed and routed
by customer (synthesizable)
Analog Tile
Logic Tile
Clock Tree generation
e.g. H tree
Benefit:Low NRE and TTM ,Prototype design, design flexibility,
Short development time medium volume,high performance,
IP Integration, Power consumption,fast design re-spins
High-Speed Mixed Signal ASIC Design
14
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Simplified Circuit of NOR/OR Latch:
High-Speed Mixed Signal ASIC Design
15
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Simplified Circuit of clock Driver:
High-Speed Mixed Signal ASIC Design
16
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Primitive logic gates Manufactured (“Hard” layout)
255 u
110 u
Load resistor
Pmos
CMOS
NMOS
SUB
High-Speed Mixed Signal ASIC Design
17
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
NOR/OR Latch
Master
Slave
High-Speed Mixed Signal ASIC Design
18
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
I/O- Master Cell
300u
200u
Pad with Pitch 100u
50 R Buffer
ECL to CMOS
CMOS Gate
ESD
Diode
CMOS Driver
High-Speed Mixed Signal ASIC Design
19
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Master slice contains
60 basic cells in a
matrix by 12 rows
and 5 columns.
28 Differential I/O
(ECL_logic, CMOS-logic)
VCC, VCCIO,
GND-Power rails
4 Corner cells
Technology SiGe:C BiCMOS SGB25VD
2mm
2 mm
High-Speed Mixed Signal ASIC Design
20
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Pseudo random bit sequence generator
PRBS-7 (Block diagram):
High-Speed Mixed Signal ASIC Design
21
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Pad limited Chip:Design of PRBs-7 Based on structured ASIC (10GHz)
used 12-Cells
I/O Cells
used 23- I/O cells
corner cells
Layout
Chip photo
High-Speed Mixed Signal ASIC Design
22
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Block Diagram of a Master- Slave D- Filpflop (MS-D-FF)
input-
stage
Latch
EF
Latch
clk -
stage
B uffer
+
EF
Master
Slave
clk input
input
output
Johnson divider
50R
50R
50R
Mixed-Signal ASIC Design:
High-Speed Mixed Signal ASIC Design
23
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
ECL Master- Slave-D-Flip-flop (40 GHz)
Technology:High-Performance 0.25 um SiGe BiCMOS SG25H1 IHP
950um
1311um
High-Speed Mixed Signal ASIC Design
24
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Layout of Divider
Technology:High-Performance 0.25 um SiGe BiCMOS
SG25H1 IHP
752um
924um
High-Speed Mixed Signal ASIC Design
25
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
100 G/bs Divider: (SG25h1m4)
input=50 GHz
pre_simulation
post_simulation
current=148 mA
output=25 GHz
20ps
20ps
10ps
s wing 600mV
Differential input and output
High-Speed Mixed Signal ASIC Design
26
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Input power sensitivity
Measured output spectrum
at 44.6 GHz input frequency.
Preliminary Measurements Results:
High-Speed Mixed Signal ASIC Design
27
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Block Diagram of Bandgap Reference Circuit
R3
R3
R1
R2
R1
R2
R3
Uref
Borkaw Reference
Widler Reference
amplifier with
start- up
Q2(n)
Q1
Q2(n)
Q1
dUBE/ dT=-2 mV/K
UBE
UBE
UBE=UT*ln(IC2/IC1), (IC2=nIC1), UT=KT/e
IC1
IC2
UBE
Utemp=UT*(R2/R1)*(1+n)*ln(n)=UT*A PTAT (Proportional-to-absolute-temperature)
Utemp
Uref=Utemp +UBE
Uref
dUtemp/ dT=A*UT/T =+2mV/K
High-Speed Mixed Signal ASIC Design
28
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Specification :T - 40..120 C°, power: 1.8V..3.3V, TC: 9ppm/C°
Technology:High-Performance 0.25 um SiGe BiCMOS SG25VD IHP
Layout of Band gap
700u
415u
High-Speed Mixed Signal ASIC Design
29
Steinstraße 12
D-45657 Recklinghausen, Germany
www.advico.de
info@advico.de
Pre- Versus Post-Simulation of curvature corrected bandgap references
post simulation
pre simulation
1.156mV
0.912mV
TC: 9ppm/C°
T= -40C°....120C°