NEW APPLICATIONS FOR ION IMPLANTATION: LIFE IN A VERTICAL CMOS WORLD, MATERIALS MODIFICATION and DEEP PROTON IMPLANTS:

Abstract

This chapter looks in some detail at the methods and process issues for high-dose implantation for formation of planar and 3D CMOS devices and materials. Among the topics discussed are: implants for enhancement of carrier mobility in CMOS channels, doping of sub-10 nm fully-deleted CMOS in planar and finFET structures, tuning of damage accumulation profiles by control wafer temperatures during implantation for both cryo and " hot " conditions, use of dopant and non-dopant ions for materials modification, diffusion controls, resist stability enhancements and local plasma etch rate tuning. The chapter concludes with some examples of the use of MeV protons for membrane separation and lamination of 3D CMOS device layers. .

Full text

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Chapter 7:
NEW APPLICATIONS FOR
ION IMPLANTATION:
LIFE IN A VERTICAL CMOS WORLD,
MATERIALS MODIFICATION and DEEP PROTON IMPLANTS
Michael I. Current
Current Scientific, San Jose, CA, USA
currentsci@aol.com
ABSTRACT
This chapter looks in some detail at the methods and process issues for high-dose implantation for
formation of planar and 3D CMOS devices and materials. Among the topics discussed are:
implants for enhancement of carrier mobility in CMOS channels, doping of sub-10 nm fully-
deleted CMOS in planar and finFET structures, tuning of damage accumulation profiles by
control wafer temperatures during implantation for both cryo and “hot” conditions, use of dopant
and non-dopant ions for materials modification, diffusion controls, resist stability enhancements
and local plasma etch rate tuning. The chapter concludes with some examples of the use of MeV
protons for membrane separation and lamination of 3D CMOS device layers.
.
CHAPTER CONTENTS Page
1. Implant technology in a post-scaling world
1.1 60 years of scaling; shallow junctions to finFETs 7-2
1.2 Mobility enhancers 7-6
1.3 Fully-depleted channels; finFET doping 7-12
1.4 Leakage current controls for bulk finFETs 7-22
2. Materials modification applications 7-39
2.1 Dopant diffusion controls 7-41
2.2 Etch rate controls 7-44
2.3 Resist adhesion 7-47
3. Deep proton implants 7-49
4. Summary 7-52
References 7-53

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1.0 Introduction: Implant technology in a post-scaling world
The modern world of high-performance electronics has largely been built on the steady increases
in the performance of CMOS transistor driven devices, accompanied by the proportional
decrease, over many orders of magnitude, in the cost per transistor and memory storage bit. The
linked progression in increasing IC chip complexity and decreasing cost comprise the basics of
Gordon Moore’s “laws” [ref to IEEE Spectrum articles]. The basic switches in these electronic
devices are predominantly variations on a planar CMOS transistor (Fig. 1.0.1), with the current
flow between a heavily-doped “source” junction to a corresponding “drain” controlled by
voltages applied to a “gate” electrode placed over a lightly-doped “channel” region.
Figure 1.0.1. Sketch of major structures in a planar CMOS transistor.
Providing the doping levels and locations for the various junctions and conducting regions in
planar CMOS transistors has been the principal function of ion implantation equipment in IC
fabrication. The precision, stability and overall flexibility of ion implantation techniques has led
to doping process spanning a dose of range of 106 and energies from ≈100 eV to several MeV
(Fig. 1.0.2). For 28 nm planar CMOS process, the number of implants per system-on-chip (SOC)
device ranges from 40 to 60 implant steps [Tsukemoto10].
Figure 1.0.2. Doses and energies for major doping implants for CMOS transistors, Si-based PV
cells and formation of SOI and laminated materials.

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This chapter will discuss the changes in ion implantation processing in present day (2014) and
near-future applications, driven by improvements in logic and memory IC devices, Si-based
photo-voltaic (PV) devices and the emerging range of methods for formation of laminated
heterogeneous materials wafers and intimate stacking of 3D circuits.
1.1 60 years of scaling: shallow junctions to finFETs
For over half a century, the principal method for improving CMOS transistor drive currents,
switching speeds and chip size has been to systematically shrink the lateral and vertical
dimensions of the basic source/gate/drain regions (Fig. 1.1.1).
Figure 1.1.1. Scaling of IC devices from 1958 through the ITRS09 roadmaps for high-
performance logic (micro-processors). The CMOS features tracked are the physical gate length,
Lgate, source/drain extensions junction depth, XjSDE and equivalent oxide thickness of the
dielectric layer insulating the gate electrode from the channel region, EOT.
The long time scale and near-exponential trends in feature sizes masks the challenges to be met to
achieve this unprecedented record of consistent feature size shrinking, “scaling”, and the many
changes to ion implantation (and other) tools and process needed to accomplish this result. For
example, since the mid-1980’s, the main new developments in ion implantation have been along
two diverging paths; continual improvements in the throughput of low-energy, near and sub-keV,
for doping of “shallow junctions”, sub-20 nm, for source/drain extensions (SDE) and
development of MeV ion implanters for doping of deep wells for memory and imaging devices.
For the last 20 years, device modelers have been aware that materials limitations of doped Si
junctions and SiO2 insulators were leading to an “end of the roadmap” for planar CMOS at gate
lengths of ≈25 nm (fig. 1.1.2) [Taur 98 &02].

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Figure 1.1.2. Approximate dimensions, doping levels and depletion boundaries for a 1998 model
of an nMOS transistor with a 25 nm effective gate length at the limits of leakage current and
switching performance [Taur98]. The principal doped regions in this model nMOS transistor are
(1) a source/drain (without shallow SD extension structures), (2) a highly-doped “super-halo”
channel (formed by tilted wafer implants) and (3) a doped poly-Si gate electrode.
“End of Roadmap” bulk planar CMOS doping profiles
With the general consensus that shrinkage of bulk planar CMOS to gate lengths significantly
shorter than 20 to 25 nm will not result in improved device performance and will lead to
unacceptably high leakage currents and device variability, one can develop a stable picture of the
doping profiles to be used in high performance planar bulk Si CMOS going forward using the
Denard scaling relationships and associated ratios for “well tempered” CMOS transistors
[Denard73]. The leading scaling ratio linking lateral (lithography and etching driven) and
vertical (doping driven) features is that the source/drain extension (SDE) junction depth is
between ½ to 1/3 of the gate length dimension. In order to avoid current crowding, high series
resistance and problems in forming metal/junction contacts, the source/drain contact junction is
significantly deeper, approximately equal to the gate length. The halo doping region under the
SDE extends down to the depth of the contact region. CMOS well depths for single-well devices
commonly extend to the depth of shallow trench isolation (STI) structures, which are 200 to 300
nm deep for logic devices. The dose-energy windows and doping profiles (calculated by
SRIM) for 25 nm gate length bulk planar CMOS transistors are shown in Fig. 1.1.3.
Figure 1.1.3. Dose-energy and profiles for 25 nm bulk planar CMOS.

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“End of Roadmap” Strategies: New Materials and Vertical Devices
The limitations of “end of roadmap” planar CMOS transistor performance, even after achieving
stable control of shallow junction formation, has led to:
(1) introduction of new materials and strained structures for improved carrier mobility
and
(2) use of fully-depleted channel designs.
In addition to fully-depleted channels, the desire to continually increase device packing density
(for improvements in performance, yield, cost of manufacturing and chip size) has fostered the
development of vertical channel and memory devices.
Vertical and “ultra-slim” junctions
The transition to the use of vertical channels, led by the use of “tri-gate” transistors in 22 nm
logic at Intel, has actually been underway for most of the last decade. The need to increase the
density of memory cell arrays in DRAMs drove the replacement of planar transistor gates by
“recessed channels”, where the gate electrode and oxide was placed in a deep trench surrounded
by source and drain contacts, establishing long channel, low leakage cell control behavior while
minimizing the lateral area of the “RCAT” device (Fig. 1.1.4) [Kim03, Kim06, Lee08].
Figure 1.1.4. Sketch of planar and vertical (“recessed channel array transistor”, RCAT) word
line transistor gates in DRAM devices.
Elaborations of the RCAT gate design to include buried channel paths through the bottom of the
vertical gate have evolved into an increasingly wide variety of buried and exposed multi-fin
structures in advanced DRAM and NAND memories [Lee07, Koo08].
The development of dual-gate transistors in the form of various “finFET” designs has also been
under active development for over a decade (Fig. 1.1.5). The difficulties in limiting off-state
currents in planar CMOS gates of less than 25 nm led to the switch to finFET devices. In the case
of Intel, finFETs are referred to as “tri-gate” channels to reflect the gate control from the top as
well as the two sides of the exposed channels [Bohr11].

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Figure 1.1.5. Side-on view of a planar MOS channel (left) and end-on view of channels for bulk
and silicon-on-insulator (SOI) finFETs (right).
The first production ICs made with finFET transistors were 22 nm Intel logic and SRAMs using a
“bulk” finFET design built on Si wafers and deep etch fins with a pitch of ≈60 nm (Fig. 1.1.6).
The doping issues for these and other fully-depleted channel transistors will be discussed later in
section 1.4.
Figure 1.1.6. Sketch of a 3 channel bulk finFET after fin etching, oxide re-fill, deposition and
patterning of the gate electrode and before formation of spacer oxides, doping of extension and
contact regions, deposition of fin links with heavily-doped CVD “bars” and first level metal
contacts (left) and a cross-section TEM image of the fin channel and gate stack for the 22 nm
Intel “tri-gate” transistor [Giles12].
1.2. Mobility enhancers:
Throughout most of the IC development timeline shown in Fig. 1.1.1, improvements in transistor
drive currents and switching speeds were obtained by reducing the lateral and vertical dimensions
of the transistors, “scaling”, with appropriate changes in doping concentrations, oxide thickness
and drive voltages [Dennard73]. For CMOS transistors smaller than 130 nm, leakage current
through SiO2 and SiONx gate oxides limited the gate oxide thickness to ≈1.2 nm. Although gate
and contact pitch dimensions continued to shrink for 90 nm and smaller nodes, the limitations on
gate oxide thickness restricted further scaling of the S/D and channel regions.

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CMOS performance, especially drive currents, continued to improve by use of various methods to
increase the carrier mobility in the channel regions by introduction of strain on the channel
materials. At the introduction of 45 nm CMOS production, the classic poly-Si/SiO2 gate stack
was replaced by a variety of metal gates and high-dielectric constant, “high-k”, oxides mostly
based on HfO2. The net effect of channel strain and high-k/metal gate, HKMG, materials
includes improved CMOS drive currents over 4x the levels obtainable by dimensional scaling
alone (Fig. 1.2.1).
Figure 1.2.1. Drive current performance factors for Intel pMOS transistors for 130 to 32 nm
devices [Kuhn10].
Stress engineering with epitaxial deposition of source/drain regions
Since 90 nm CMOS (circa 2000), the focus on process development shifted from “Dennard
scaling”, that is, proportional shrinking of gate lengths, gate oxides and junction depth by ≈0.7 for
each scale cycle (or “node”), to finding ways to increase transistor drive currents by increasing
carrier mobilities in the channels by application of uniaxial strain. For pMOS devices, the
required compressive strain was provides by the growth of B-doped SiGe stressors by selective
epi in etched regions close to the spacer edges [Ghani03]. Additional compressive strain was
applied to the pMOS channel with various “stress memorization” implants into the poly-gates,
from shallow trench isolation (STI) processes and from a capping nitride layer. The principal
CMOS stressor regions are sketched in Fig. 1.2.2.

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Figure 1.2.2. Sketch of CMOS stress methods providing compressive stress in the pMOS
channel and tensile stress in the nMOS channels (stress directions shown with arrows).
Application of the B-doped, SiGe epi approach for the nMOS channels, selective epi growth of P-
doped Si:C, are more challenging, even though the required C concentrations are much less (≈2%
substitutional C) than the Ge levels on the pMOS side (≈45%) [Kim07]. The principal difficulty
is that the growth of epitaxial Si:C with high substitutional C levels requires repeated deposition
and etch-back steps at low temperatures and limits the chamber throughput to 1 or 2 wafers per
hour.
Stress engineering with implantation
Adequate nMOS stress levels, sufficient for ≈10% drive current improvements, can be obtained
by intentional formation of stacking fault defects by regrowth of deep amorphous layers at the
spacer edges [Wei07, Lim10]. Such defects are common features of implant process as studied in
detail by Sanger et al. [Sanger07a]. The general process is sketched in Fig. 1.2.3.
Figure 1.2.3. Sketch of formation of nMOS tensile stressors through formation of angled
stacking faults at the intersections of vertical and horizontal regrowth fronts following deep Ge
amorphization implants.

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Stacking fault tensile stressors are common features in 32 nm nMOS transistors from Samsung
and Intel (Fig. 1.2.4) as easily seen by the characteristic 45o orientation defects in TEM analysis.
Figure 1.2.4. 32nm nMOS from Samsung and Intel showing stacking fault stressors [James11].
Tensile strain with atomic and molecular Carbon ion implants
Direct high-dose implantation of C, combined with n-type dopants and some variant of a
diffusion-less anneal, provides a direct and productive approach to obtaining higher tensile strains
in nMOS transistors [Liu07, LiFatou07]. The key to achieving high (1 to 2%) C substitutionality
seems to be the regrowth of a C-rich amorphous Si layer. In one approach, a sequence of PAI,
doping and C+ ion implants are followed by a low-temperature SPE anneal, yielding a 1.65% C
substitutional level in the SDC regions, a 35% increase in electron mobility and 15%
improvement in drive current (when combined with a nitride stress layer) at the cost of a 10x
higher junction leakage current (related to the SPE anneal and EOR damage from the PAI step)
(Liu07].
When C-rich molecular ions are used for the implant, a dense amorphous layer is formed (similar
to the case for Borane-type molecular dopants) removing the need for a separate PAI cycle (Fig.
1.2.5). After laser annealing (1175 C, 0.8 ms), the amorphous layers created by the molecular
ions are regrown resulting in high level of tensile strain, seen in the displacement of the
secondary peaks from the Si lattice peak in XRD rocking curves (Fig. 1.2.6). The use of C14H14+
ions resulted in a near doubling of the substitutional C levels (to 1.35%) over the C7H7+
implanted regions (Table 1) for a common C-dose of 2x1015 C/m2 for all cases.

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Figure 1.2.5. TEM images of Si implanted with 6.6 keV/atom implants at 2x1015 C/cm2 using C+
(left) and C7H7+ (right) ions [Li-Fatou07].
Figure 1.2.6. XRD rocking curves for C+, C7H7+ and C14H14+ implanted Si after a 0.8 ms laser
anneal at 1175 C [Li-Faou07].
High-mobility materials
With the shift to vertical channels in finFETs, the group of strain enhancement techniques used
for planar CMOS (Fig. 1.1.2) become more complex and can be harder to implement [Bedell14].
Attention has shifted to use of channel materials with intrinsically higher carrier mobility, such as
Ge, SiGe and GeSn for hole conduction in pMOS and InGaAs and GaAs for electron conduction
in nMOS (Fig. 1.2.7 and 1.2.8).

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Figure 1.2.7. InGaAs quantum well device (QW) and switching times for various compound
semiconductor and elemental channels [Sadana10].
Figure 1.2.8. QW and finFETS for InGaAs channels [Radosavljevic11].
The implant requirements associated with the use of these high-mobility channel materials
include the need to develop efficient ion sources and process for doping of III-V compound
semiconductors, such as Si, Te, Sn and S for n-type and C, Ge and Zn for p-type materials.
“Monolayer” channel materials
The next step in this process of utilization of high-mobility channel materials is the incorporation
of 2-dimensional, “monolayer” conductors, such as MoS2, WSe2, GeHx, graphene as well as some
of the many varieties of carbon nanotubes (CNT) and Si (and other semiconductor) nanowires
into planar and vertical CMOS transistors (Fig. 1.2.9).
Figure 1.2.9. The combination of a MoS2 molecular channel and an array of single-walled
(carbon) nanotubes (SWNT) on an SOI substrate to form a CMOS inverter circuit [Huang12].

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Doping of molecular MoS2 and CNTs has been done in saturation mode by absorbtion of
chemical vapors and hydrocarbon-based dopants (Fig. 1.2.10). To achieve controlled doping of
molecular channels by ion beam means, the ion energy must be low enough (≈100eV or less) so
that the dopants are incorporated in the thin channel film without extensive disruption of the
molecular structure. This “deposition with dose control” will require a new level of beamline
designs to achieve the required level of ion beam quality, with tight controls on the ion energy
distribution and angular divergence.
Figure 1.2.10. Saturation doping of MoS2 a film by vapor doping of a donor layer of K[Fang13].
1.3. Fully-depleted CMOS channels:
A characteristic feature of “post-roadmap” CMOS is the use of fully-depleted (FD) channels,
where the gate/channel geometries are arranged so that the electrostatic potential from the gate is
sufficient to exclude all mobile carriers from the channel, resulting in very low off-state leakage
currents.
FD-SOI CMOS
The most direct implementation of FD CMOS is a modification of the planar CMOS designs that
have been used for the last decade for “partially-depleted” SOI-CMOS. In FD-SOI CMOS, the
channel thickness is reduced to <10 nm so that the voltage swing of the vertical gate is sufficient
to fully deplete (ie. “turn off”) the planar channel (Fig. 1.3.1). When the buried SiO2 layer
(BOX) is also thinned down to ≈25 nm, a variety of ”short channel effects”, such as the slope of
the channel current with gate voltage swing and the “roll off” of the threshold voltage with
shorter gate lengths, are improved.
The thin BOX increases the coupling of the channel with the buried substrate allowing the well
doping under the BOX to act as a second gate electrode. The thin dimensions of the channel Si
and BOX layers allow for direct implant doping of the sub-BOX region with ion energies and
doses that are easily within the capabilities of mid-current ion implanters (Fig. 1.3.2).

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Figure 1.3.1. Cross-section sketches of two variants of FD-SOI with sub-10 nm channel
thickness for 25 nm gate lengths [D.K. Sadana10].
Figure 1.3.2. Sketch of back-gate planes for UTSOI formed by heavily doped under-BOX planes,
doped by high-dose implants [Bergemont12] (upper) and SRIM profiles for 30 to 50 keV Boron
(left) and 70 to 100 keV Phos (right) implants for back plane doping for a 10 nm Si channel and
25 nm BOX and a dose of 1014 dopants/cm2 (to keep the channel Si doping level at <1e18
dopants/cm3 and peak sub-BOX well doping at ≈1e19 dopants/cm3) (lower).
When strongly doped regions are added below the thinned BOX layer are connected to variable
bias contacts, the ”back-gate “ bias can be used to dynamically shift the threshold voltage on the
channels of many local device regions (Fig. 1.3.3).

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Figure 1.3.3. Well, ground-plane and contact doping for threshold control for UT-SOI CMOS
devices allowing for dynamic power/speed tradeoffs across the chip. [Haond12].
FinFET CMOS
Vertical channel CMOS designs were developed at UC Berkeley and elsewhere in the late 90’s,
based on previous work done at Hitachi. In its basic form, a finFET consists of and etched
vertical channel with a gate electrode deposited over the channel and down to the bottom of the
channel, forming a 2-gate structure (Fig. 1.3.4). The channel is lightly or un-doped with heavily
doped source and drain regions (often also including SD extension regions under the gate spacer
insulation). A common variation on the classic finFET uses a wider fin width to allow the gate to
control the channel depletion volume from the top as well as the sides of the channel, forming a
“tri-gate” structure.
Figure 1.3.4. Sketch of a dual-gate finFET (left, T-J. King-Liu, UCB) and projection views of an
early n-finFET fabricated on SOI [Hisamoto98].
Doping challenges for finFETs
The first commercial utilization of finFET devices was introduced by Intel in their “22 nm”
products in 2011. Each CMOS transistor was formed from single or multiple fin-channels etched
in bulk Si (Figs. 1.3.5 and 1.1.16). The challenges for doping CMOS junctions in these vertical
arrays are significantly different than planar devices. These include: (1) the need for conformal
(uniform in depth) doping in the SD contact and extension regions so that the carrier conduction
is uniform in the body of the fin-channel bounded by the gate electrodes, (2) the use of little or no
doping the channel region to take full advantage of carrier mobility and avoid threshold voltage

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variations, (3) the tight pitch (≈60 nm for the Intel 22 nm designs) of the fins limit the beam
incidence angles that can be used and still avoid shadowing from neighboring fins to ≈10o off-
vertical or less, (4) the combination of the increased surface area of a multi-fin array over the
equivalent planar area and the ion reflection, recoils and sputtering for grazing angle ion
incidence increases the effective dose and desired beam currents for doping finFET devices, and
(5) damage accumulation and annealing in high-aspect ratio vertical fins are significantly
different from the well-known challenges for planar junctions and need to be re-learned in this
new context. These challenges are discussed in the following sections.
Figure 1.3.5. TEM of Intel 22 nm fin arrays with nMOS (left) and pMOS (right) channels
[James12]. The fin pitch is ≈60 nm, the total fin height is ≈100 nm and the active channel height
is ≈35 nm. The active channels are triangular in shape with a width of ≈8 nm at the half height
position.
Additional challenges for bulk finFET doping include the need to provide junction isolation
doping in the base of the finFET below the gate controlled region to block carrier leakage paths
during off-state conditions. At the same time, the fin base doping levels cannot be so high that
defect recombination and tunneling effects in the SD/base doping depletion region do not
contribute significant additional leakage currents. These problems are similar to the dose and
damage tradeoffs in SD extension and halo doped regions in planar CMOS.
Creation of “ultra-slim” doping by grazing angle ion incidence
The doping of vertical structures with energetic ions, with either beamline or plasma immersion
systems, always involves the incidence of ions at some degree of glancing incidence to the
surface. These conditions increase the rate of ion reflection and surface sputtering as well as
reduces the ion penetration depth, all of which decreases the retained dose in the surface region to
far below the levels one gets with normal incidence ions. Lighter ion masses, with wider
straggling ranges, tend to lose a higher fraction of the implanted dose through back reflection
although the retained dose for highly glancing angle incidence falls rapidly for all ion types (Fig.
1.3.6) [Duffy08].

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Figure 1.3.6. SIMS profiles for 5 keV As at various incidence angles (left) and SRIM
calculations of projectiles and retained doses for a variety of ions with a normal incidence mean
range of ≈10 nm in Si (right) [Duffy08].
The effect of beam incidence angle on isolated fin structures is shown in Fig. 1.3.7, where
increasing the grazing angle to 45o results in much higher sidewall doping levels and uniformity
(conformality).
Figure 1.3.7. Poly-fill-SIMS (left) and Scanning Spreading Resistance Mapping (SSRM) images
(right) for B implants into “fat” (40 nm) fins at incidence angles of 10 and 45o (grazing incidence
angle) [Mody11].
When the a-Si region after high-dose implant extends across the entire width of the fin, the crystal
re-growth occurs from the c-Si seed in the base of the fin (for bulk finFETs). However the
crystalline re-growth front is slowed near the fin sidewalls leading to formation of twinned
regions and nucleation of poly-Si regions deeper in the a-Si segments (Fig. 1.3.8) [Duffy07].
Highly defective fin structures can be expected to show low carrier mobilities and poor dopant
activation from carrier scattering and dopant segregation to grain and twin boundaries.

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Figure 1.3.8. TEM images of As and P implanted ≈15 nm wide Si fins and after anneals at 600
and 1050 C for a shallow implant (left) (45o quad implants with 5 keV As at 1e15 As/cm2) and a
deep implant (right) (normal incidence 25 keV As at 3e15 As/cm2 and 8 keV P at 2e15 P/cm2).
Note the effect of pinning of the re-growth front by the fin sides and formation of twin defects
[Duffy07].
For high-dose implants into planar surface layers in Si(100), the broad area of the a-Si layer re-
grows rapidly towards the surface, growing from the large area seed of crystalline Si base, with
few residual defects and high dopant incorporation into the Si lattice (except for end-of-range
defects and defects created by the merging of horizontal and vertical re-growth fronts near mask
edges). However, in heavily damaged fins, re-growth initiates from limited c-Si areas at the
boundary of the undamaged channel region under the gate electrode (or from the fin base in the
case of bulk finFETS). Even when the fin re-growth front is along the fast-growing (100)
direction, the a/c front is slowed down and pinned along the fin surfaces creating a non-planar re-
growth and resulting in the formation of {111} twins and, eventually, poly-Si regions in the
upper portions of the fin (Fig. 1.3.8).
The re-growth conditions are much better when the implant damage is shallow enough so that a
central c-Si region is preserved after the implant to act as an additional seed region for re-
crystallization of the fin during anneal. The lower residual defect density in annealed fins with
post-implant central c-Si cores results in lower fin resistivity from higher active dopant
concentrations (less dopant trapping at defects) and lower carrier scattering (Fig. 1.3.9).

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Figure 1.3.9. Sketches showing the limited c-Si seed area for a fully a-Si fin and benefits of a
central core of c-Si for a partially amorphized fin (left) [Duffy07] and improved (lower) Si fin
resistivity as a function of fin width for various levels of implant damage (right) [vanDal/08].
Recoil implantation doping
Choosing ion energies so that the a-Si layer expends only part of the way into the fin body results
in good fin re-crystallization, however the use of low ion energies reduces retained ion dose (see
Fig. 1.3.6). A good way to minimize fin damage depths and still obtain high dopant loading in
the fin body is to use the incident ions to recoil implant atoms from an absorbed layer of dopant
atoms. By having a large part of the ion stopping occur in the dopant atom layer, the amount of
damage in to the Si fin is reduced. Because the dopants atoms are implanted by a large number of
secondary atom collisions, the number of recoil events can be higher than the incident ion flux if
the projected range of the ions is approximately the same as the dopant atom layer thickness (Fig
1.3.10).
Figure 1.3.10. SRIM calculations of B and Si damage profiles for direct and recoil implantation
with a 1 keV B beam incident at 45o on a deposited B layer with a thickness of 1 to 8 nm. The
concentrations are for an incident dose of 1e15 B/cm2. Note that the recoil B concentration is
higher than the direct beam profile levels at the B/Si interface for tB ≈ <XB> ≈ 35 A.
When a PIII system is run under conditions which favor dopant deposition and recoil implant of
the fin sidewalls, such as the “self-regulated plasma doping” (SRPD) process for As-doped fins
(Fig. 1.3.11), a high level of active dopant concentration and high fin channel Ion is obtained
[Zschatzsch11]. The method has also been proposed for use with beamline systems combined
with an initial CVD deposition step (Fig. 1.3.11) [Fuse10].

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Figure 1.3.11. Sketch of recoil implant doping of a CVD-doped layer on a fin sidewall by a
glancing angle ion beam (left) and characteristics of finFETs doped by plasma and tilted beamline
implants (right) with the highest Ion and active dopant concentration for a “self-regulated plasma
doping” (SRPD) case [Fuse10, Zschatzsch11].
Bulk-finFET base doping
Bulk finFETs require a deep fin doping for isolation of the fin channel from the substrate to
contain the fin drive current in the depletion volume controlled by the surrounding gate
electrodes. The trick is to find ways to place the fin isolation doping into the lower part of the
bulk fin while keeping the channel doping levels low (for high-mobility channel conduction,
minimal threshold voltage shift). Doping levels in the fin body for good isolation are ≈3e18
dopants/cm3, similar to ideal halo doping in planar CMOS (Fig. 1.3.12) [Hook12].
Figure 1.3.12. Side view sketch of a bulk finFET with fin height, Hfin, above a CVD oxide filled
fin separation with a deep gate extending below the bottom of the fin channel (left) and
proportional off-state leakage, Ioff/Wfin (A/um) variations with base doping levels (right). Also
shown are off-state leakage paths under the gate electrode for low base doping and band-to-band
tunneling (BTBT) leakage paths for high base doping.

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A key challenge in bulk finFET doping is to arrange the doping of the base at a tightly controlled
level (≈3e18 dopants/cm3) under the channel and S/D regions while keeping the channel region
under the gate in an undoped (or lightly doped) state to maximize carrier mobility.
Numerous methods to achieve this combination of doping regions. One method to dope the lower
part of a fin with only a top-fin mask is shown in Fig. 1.3.13, where the fin body doping is
accomplished by lateral straggling of ions in the upper layer of the CVD oxide fill with a normal
incidence beam. The channel region of the fin is masked with top SiN layer. The location of the
peak doping is set by the range profile of the doping ions in the CVD oxide. The only upper
portion doping occurs from backscattered ions from the CVD oxide surface and from glancing
angle ions due to Coulomb divergence in the ion beam. Any slope to the fin sidewall would
result in additional doping below the SiN mask in this top-mask process.
Figure 1.3.13. Body doping of fins by lateral straggling on ions in the CVD fill layer for a normal
incidence beam on a vertical side-walled fin with a fin-top SiN mask blocking ions from the
upper channel region [Kawasaki07].
More direct method is to mask of the fin top and sides, with a SiN (or similar) layer extending
down the sides of the channel region leaving the fin body and etch trench bottom open to an ion
beam. This would allow for selective implant doping of the “triangular” finFET base region.
An alternative approach to bulk fin base doping in the body of the bulk fin is to implant a
counter-doping profile directly through the fin channel with the dopant peak at the bottom of the
channel (Fig. 1.3.14). This vertical implant needs to be done with a relatively heavy ions (with
low diffusion rates) to minimize up diffusion of the punch through dopant in to the channel
region. However there is always considerable channel doping from the vertical implant (as there
also would be if the angled body implant doping is done without a fin-top cap dielectric mask).

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Figure 1.3.14. SIMS and Atom Probe Tomography (APT) vertical profiles for SD doping by
plasma doping (diborane/He, 300 W) and beamline (3 keV B+, 30o incidence, 1e15 B/cm2)
(upper) and SIMS profiles for Boron doping and vertical As implant (45 and 45 keV, 7e13
As/cm2) with the As peak tuned to be close to the bottom of the channel defined by the SD
doping profiles to minimize SD punch through (lower) [Izumida11].
A simple process flow for baser doping using only routine implantation conditions together with a
two-step epi blanket deposition is outlined in Fig. 1.3.15. The use of epitaxial Si layers to
provide controlled resistivity device layers with no local wafer-originating defects, such as
oxygen precipitates and vacancy cluster voids, has been a standard procedure for advanced IC
devices for several decades. In this case an initial un-doped epi layer is deposited on a Si wafer
with a thickness approximately equal to the fin base height. After masking and implant doping
of n and p-type regions, a second un-doped epi layer is deposited with a thickness close to the
desired channel height. Bulk fins are then etched to their full depth at the epi/wafer interface,
separated by a CVD oxide deposition with a thickness equal to the fin base region and the HKMG
electrode is deposited and the gate electrode patterned. This is followed by conformal doping of
the SD extension region, capping by a spacer oxide along the sides of the gate electrode and
additional conformal doping the SD contacts and deposition of doped epi “bars” to provide
contacts across the transistor fin arrays and facilitate metal contacts for the circuit wiring.

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Figure 1.3.15. Process flow and sketch for a simple process flow for base doping of bulk
finFETs with a combination of routine implant doping and two epi depositions of un-doped Si
(upper) and sketch of gate and S/D implants for channel regions of finFET (lower).
1.4. Damage engineering for low-leakage junctions:
Leakage current effects: PAI & dopant ion damage, cyro- and hot-implants
Off-state power levels in advanced logic devices have been rapidly approaching the dynamic (on-
state) switching levels, leading to severe problems for chip reliability, packaging and battery
lifetime (Fig. 1.4.1). The historical trends indicate that for CMOS devices with gate lengths of
≈20 nm, off-state power densities will be comparable on active device levels. This cross-over
may occur even sooner, for ≈50 nm transistors, when the junction leakage at chip operating
temperatures (≈125 C) are considered.

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The principal leakage sources in the CMOS transistors shown in Fig. 41.4.1 were gate currents
for thin (≈1 nm) gate SiO2 and SiON dielectrics, followed by junction leakage and sub-threshold
current flows in short-channel devices. A figure of merit for the desired levels of junction
leakage currents is to be below the leakage current densities, ranging from 4x10-5 to 2x10-3
A/cm2, of high-k, Hf-based oxides that replaced SiON-type gate dielectrics for 45 nm CMOS
devices [Huff05].
Figure 1.4.1. Active and sub-threshold (“off-state”) power densities from historical device
performance and room-temperature (25 C) junction leakage [Nowak02].
The leading mechanisms for junction leakage current are band-to-band tunneling, thermionic
emission from metal contacts and carrier generation/recombination and trap-assisted tunneling in
the junction depletion layer (Fig. 1.4.2) [Solomon03, Jones96, Faifer07]. Of these causes of
junction leakage, generation/recombination (often labeled as SRH, for Shockley-Read-Hall) and
trap-assisted tunneling (TAT) currents are the most amenable to control by alteration of
implantation and annealing conditions. For a given dopant distribution, usually tightly specified
by the transistor design, the reduction of generation/recombination currents is closely dependent
on the reduction of residual implant damage after annealing which is present in and near the
junction depletion layer. As annealing cycles are driven towards ultra-short thermal pulses, of
the order of ms or less, in order to minimize dopant profile broadening by diffusion, the ability of
these anneal cycles to remove implantation damage is strongly reduced for these “diffusion-less”
conditions. The result of these effects is a new set of process constraints on implantation to
minimize the creation of lattice damage during the doping cycle. A sketch of the carrier leakage
across a depletion layer containing defect centers for forward and reverse bias is shown in Fig.
1.4.3.

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Figure 1.4.2. Sketch of the local sources of transistor (right) and test wafer (left) leakage for a
SDE/Halo/Well junction. The principal leakage sources that depend on implant and anneal
conditions are carrier generation/recombination, trap-assisted tunneling and band-to-band
tunneling (added for reverse bias junctions).
Figure 1.4.3. Carrier flows across a depletion layer containing defect sites.
The need to restrict the power requirements and heating effects of high-performance logic devices
has moved these issues to the center of new process and device development. The impact of
process and device optimization on junction and sub-threshold leakage for low-power 65 nm
CMOS is shown in Fig. 1.4.4. The principal objective of the “low damage junction engineering”
steps was to ensure that all SDE and SDC doping had junctions diffused to deeper locations than
any implant-induced residual damage sites [Jan05]. This strategy removed carrier generation and
trap-assisted-tunneling from the list of leakage current sources.

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Figure 1.4.4. Junction and sub-threshold leakage improvements with process optimization for
low-power 65 nm CMOS, combining effects of junction engineering and adjustments to gate
length, gate oxide thickness and composition, local strain and drive voltage [Jan05].
A clear example of residual damage types in earlier Intel Pentium devices is shown in Fig. 1.4.5
for CMOS with gate lengths of 130 nm. Visible in this image are end-of-range (EOR)
dislocations under the SDC junctions and regrowth “misfit” dislocations (the line of dislocations
angled at 45o on either side of the gates) arising from the mis-match of amorphous layer regrowth
in the vertical and lateral directions [Saenger07, Rudawski07].
Figure 1.4.5. TEM image of dislocation types in CMOS transistors with 130 nm gate lengths.
PAI damage depth effects
Control of the relative locations of SD junctions and residual implant damage, primarily the end-
of-range (EOR) below the a-Si/c-Si interface for high-dose implants, requires control of both the
implant and anneal conditions. One of the key process details is the depth of any “pre-
amorphization” implants (PAI) done to disrupt the wafer crystallinity and eliminate ion
channeling during the following doping implants. The leakage impact on the choices for PAI
conditions can be estimated from the location of EOR damage after annealing relative to the SDE
junction. When significant amounts of residual damage are within the depletion layers on either
side of the junction boundary, the leakage currents from SRH and TAT mechanisms are very
large and decrease as the EOR is separated from the junction location and /or reduced in density
(Fig. 1.4.6).

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Figure 1.4.6. Leakage current densities for Si or Ge PAI implants and BF3 PIII (PLAD) doping
after SPE annealing at 560 to 650 C, with some junctions also RTA annealed at 900 C for 30 s.
Data on the left side are for junctions where the EOR damage is deeper than the junction
boundary and on the right side for junctions deeper than the EOR damage from the PAI and
doping. The Si wafer resistvity was 10-20 Ohm-cm [Felch02].
The depth of the EOR damage increases as the PAI ion energy increases (Fig. 1.4.7 (left)). The
layer of EOR damage after annealing is usually located at and slightly deeper than the amorphous
layer boundary. The amorphous layer thickness can increase for PAI implants with higher ion
beam currents and into Si wafers held at cooler temperatures during implantation. If the EOR
range damage is shallower than the junction or deeper than the combined depth of the junction
and the depletion layer (which depends on the sub-junction, halo, doping), defect related leakage
is minimized (Fig. 1.4.7 (right)).
Figure 1.4.7. Ge implant mean range and straggling, amorphous layer thickness for room
temperature implants and range of EOR damage depth (left) and high and low leakage conditions
for various sub-junction (halo) doping for EOR deeper than the SDE junction (right).
Halo profile doping effect on junction leakage
Because of its location adjacent to the SDE junction, the active doping level and residual defect
densities in the halo profile are key issues for controlling leakage in CMOS transistors. As the
doping density in the halo increases, the SDE depletion layer thickness rapidly decreases,
increasing both band-to-band (BBT) and trap-assisted tunneling (TAT) for reverse bias junctions
(Fig. 1.4.8). BBT leakage is set by the halo doping levels, which in term are linked to control of
short-channel effects such as threshold roll-off with gate length shrinkage, sub-threshold leakage
currents and the location of the SDE/halo junction. While BBT effects favor the use a minimal
halo dose consistent with the other device requirements, the halo profile and dose is not generally

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available for manufacturing process optimization. However, TAT And SRH leakages, which
depend on the density of residual damage in the SDE junction depletion layer, are highly
dependent on process and tool choices for implant and anneal processes.
Figure 1.4.8. Reverse-bias leakage current densities (right) for an As-doped SDE with various B-
doped halo profiles (left) with an RTP-spike anneal process showing strong increase in leakage
for increased halo doping as the SDE junction. The dominant leakage mechanisms, identified by
their temperature dependence, are labeled in Fig. 2-44 (right) as generation/recombination (SRH,
Shockley-Read-Hall), trap-assisted tunneling (TAT) and band-to-band tunneling (BTB)
[Duffy06].
Defect effects in implant: damage accumulation, defect location
For 45 nm and smaller device sizes, the restrictions on dopant diffusion strongly limit the ability
of anneal cycle to either eliminate residual defect structures or to diffuse the dopant junction
deeper than the defect layer (as in Figs. 1.4.5 and 1.14.6). Under these thermal budget
restrictions, control of the density, type and location of residual defects created by the implant
damage is a principal process development goal.
The initial damage events that occur while and soon after ions stop in the semiconductor target
depend on the ion type, energy and process conditions, such as the arrival rates of ions in nearby
regions adjacent to an earlier ion impact. The “primary” state of damage, which is established as
the ion stops, on a timescale of less than 10 ps, depends on the ion type, energy and mass and
target binding energies. A pair of a vacant lattice site and a displaced interstitial target atom is
called a “Frenkel pair”, where the number of Frenkel pairs created by a single ion impact
increases with ion energy about a certain “threshold” energy for displacements (between 15 and
40 eV for Si). The motion and recombination of secondary defects, starting with the target atom
interstitials and vacancies, continues over a much longer time frame, or the order of several ms
(Fig. 1.4.9)
The size and local defect density of the “primary state of damage” created by a single ion impact
on a solid crystalline target depends on ion energy and the relative masses of the ion and target
atoms. For lighter ions in heavy targets, where the stopping is dominated by electronic scattering,
the damage “cascades” are relatively spread out in the target with small local regions of dense
damage. With heavier ions, with larger number of core electrons, the ion energy loss is
dominated by “elastic” or “nuclear” collisions between the core electrons of the ion and target
atoms, resulting in compact, dense regions of vacancy-rich defects with a surrounding cloud of
displaced interstitial target atoms. (Fig.1.4.10).

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Figure 1.4.9. Sketch of “primary” damage for various ion types (left) and the effects of defect
diffusion and recombination and a-Si region regrowth occurring over ms timescales (right).
Figure 1.4.10, Views of vacant sites in W crystals after single ion impacts of 30 keV 183W+, 96Mo+
and 64Cu+ ions mapped by atomic-resolution imaging and field evaporation with a field-ion
microscope after implants at ≈10 K [Wei81].
As many ions are implanted, the accumulated damage can increase to the level where the target in
a large portion of the implant profile is converted from crystalline to an amorphous form, with
complete loss of long-range order in the target atoms. Damage in the region below the a-Si layer
often forms into primitive defect types, such as 311 linear defects as well as various types of
dislocation loops (see the chapters on defect formation and annealing in this schoolbook). Since
these residual defects occur deeper than the amorphous layer boundary, they are referred to as
“end of range” (EOR) defects (Fig. 1.4.11).

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Figure 1.4.11. Sketch of damage accumulation after a high-dose ion implant.
Large molecular and cluster dopant ions
Use of large-molecular and “massive” cluster ions can result in significantly altered as-implanted
damage levels. Using molecular ions, such as B10H14 and B18H22, the large number of Boron
atoms impacting the wafer surface within a ps-timescale greatly increases the local rate of
damage accumulation and results in formation of surface amorphous layers without the need to
use a PAI implant cycle [Aoyama05, Ishibashi05]. The effect of this self-amorphization process
with the use of Boron-molecular ions with 10 or 18 dopant atoms per ion results in suppression of
dopant channeling and also provides a surface amorphous layer which is required to gain the full
advantages of either low temperature (SPE) and high temperature (laser) annealing.
The self-amorphized layers formed with B18H22 molecular implants results in fully-regrown
layers with no extensive EOR layers after ms-timescale flash annealing (Fig. 1.4.12 (upper)). In
contrast, Ge PAI combined with 200 or 500 eV B implants results in clearly visible EOR layers in
TEM images after flash annealing (Fig. 1.4.12 (lower, middle).
Figure 1.4.12. TEM images of B18H22 implanted Si (upper) after ms-anneal with flash lamps and
PAI+LEB implants (lower). Note EOR damage in PAI + LEB junctions after flash anneal
(center images, lower), showing distinct EOR damage layers, related to high-leakage junctions
and damage-free annealed junctions for B18H22 implants (upper). [Harris07].

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The self-amorphizing effect of the high damage rate of B18H22 ions, which occurs at a dose of
≈1014 B/cm2, results in B as-implanted profiles that show only slight effects of channeling and
approximate the PAI + B dual implant combination (Fig. 1.4.13 (left)). The lack of an extensive
EOR damage layer after annealing with B18H22 implants, compared to PAI process (Fig. 1.4.12),
results in low defect–related recombination/generation and tunneling leakage currents, even for
“diffusion-less” anneals such as 650 C SPE And 1300 C laser anneals (1.4.13 (right)).
Figure 1.4.13. SIMS profiles (left) for B doping with 500 eV B and 10 keV B18H22 into bare Si
and after Ge PAI implants and leakage currents (right), measured by RsL, after SPE, spike, flash
and laser anneals showing low leakage with B18H22 doping for all anneals [Borland06].
Temperature effects on damage accumulation
As the fundamentals of ion implantation for semiconductor processing were developed in the 60’s
and 70’s by many of the same people who were also studying in detail the diffusion and
activation of dopants, it was a natural thing to study the effect of wafer temperature during
implantation (Fig. 1.4.14) [Morehead71]. The effect of ion mass was understood in terms of the
denser regions of damage created by impact of heavier ions, leading to formation of stable highly-
damaged impact zones which eventually overlapped to form a continuous band of amorphous Si.
The Morehead data highlighted the strong sensitivity of light ions, such as Boron, to implant
temperatures near 300 k (approximately the routine temperature of fabs). For the low beam
currents used in Morehead’s 1970 study, the amorphization dose for Boron was much higher than
any practical doping application. 15 years later, as high-current implanters, with active wafer
cooling to limit beam power heating, became standard, the formation of amorphous layers with
Boron doses in the mid-1015 B/cm2 became a common effect.
Later studies mapped out the ion beam and temperature conditions where exposure to additional
ion beams could lead to either the growth or shrinkage of amorphous layers in Si, GaAs, SiC and
related materials [Elliman87]. And the ability of high-temperature conditions to forestall the
onset of amorphization was exploited in the design of ion implanters operating at 550 to 650 C
while implanting high doses of Oxygen to form buried SiO2 layers for SOI wafers [Sadana06].

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Figure 1.4.14. Implant dose for formation of an amorphous layer in Si for various ions and
temperatures. The open symbols and lines are from [Morehead71] and the filled symbols are
from [Mok08]. The Morehead ion energies were 200 keV for B and P and 40 keV for As, Sb
and Bi. The Mok ion energies were 200 keV for B and P (same as Morehead) and 300 keV for
Sb. All implants were done at relatively low flux levels, 1.125x1012 ions/cm2-s for the Mok data.
Cryo-implants
Since the physical basis of the generally lower leakage behavior of molecular ion implants,
discussed in the previous section, is the increase in damage associated with the simultaneous
impact of large number of incoming ions, resulting in thicker amorphous layers for the same total
ion dose and equivalent ion energy, a renewed interest has developed in enhancing damage
accumulation rates, even for single ion implants, by lowering the wafer temperature during
implant to well below 0 C [Hatem08].
Detailed studies and modeling in recent years has yielded closely predictive codes that include
also the effects of beam current density, beam scan rate, ion energy and dose on amorphous layer
formation (Fig. 1.4.15) [Mok08, Zographos08]. These models contain the effects of ions mass,
(the ability of heavier ions to create dense single-ion damage regions), dose rate (the impact of
subsequent ions before the initial ion damage distribution has stabilized) and temperature
(annealing rate of local damage sites through Si interstitial diffusion over short distances). Dose
rate effects occur because, although the ion stopping and recoil cascade effects are rather fast
(within 10 ps of the initial impact), the short-time annealing of the vacancy and interstitial pairs
created by the ion impact extends over a ms-timeframe and is highly sensitive to defect diffusion
rates and the kinetics of the regrowth of local amorphous zones created in the damage cascade.
The effect of wafer temperatures on accumulated damage profiles in Si for 1 keV B implants is
shown in Fig. 1.4.16 [Van den Berg02]. While implants at 25 C result in only partially damaged
surface material, a 10 nm thick amorphous layer is formed for the same (low current) implant
conditions at –150 C. Following RTA anneals at 900 C, the cryo-implant at –150 C had
measurably lower residual damage levels below the Si surface compared to the higher
temperature implants.

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Figure 1.4.15. Data (points) and model results (lines) for the amorphous-crystalline transition
temperature in Si(100) for 80 keV single ions at doses of 1x1015 ions/cm2, except for C at 2x1015
C/cm2 [Mok08].
Figure 1.4.16. Medium-energy (200 keV He+) ions scattering (MEIS) depth profiles for damage
from 1 keV B (3x1015 B/cm2) after implants at -150, 25 and 300 C and anneal at 900 C. Also
shown are the as-implanted Boron profile and location of the peaks in the vacancies and recoil
interstitial distributions calculated by TRIM [Van den Berg02]. Note the much deeper as-
implanted damage profile and lower residual damage ≈7 nm depth after anneal for the –150 C
implant case.
Molecular ions vs cryo-wafer conditions
Although cold wafer conditions can increase the damage accumulation rates for single ions, the
use of multi-atom or molecular ions is much more effective in creating deep and dense a-Si
layers. A comparison of a-Si layers created by atomic and molecular C atoms in a temperature
range from 25 to -30 C showed that the C7 molecular ions at 25 C created deeper a-Si at a dose of
1e14 C/cm2 than atomic C ions at -30 C and a dose of 1e15 C/m2 [Sekar11]. C16 ions created
even deeper a-Si layers at lower doses and all temperatures (Fig. 1.4.17).

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Figure 1.4.17. Damage accumulation for atomic and molecular C ions at temperatures between
25 and -30 C. Note the deep a-Si layers created by C7 and C16 ions [Sekar11].
Leakage current for cryo-wafer conditions
Diode leakage studies for As and B implanted junctions showed consistently lower leakage
current for cryo-implants (Fig. 1.4.18) compared to room temperature process [Suguro01]. The
effects increased with ion dose used to form the diodes and were substantially larger for As
implants at high doping levels.
The general nature of the effect of higher damage accumulation rates, arising from either cryo-
implants, high beam currents or molecular and cluster ion impacts, on residual damage can be
understood in terms of the effect of damage rate on amorphous layer thickness (Fig. 1.4.15). For
conditions of low damage accumulation rates (such as light ions, low beam current densities and
high wafer temperature) the surface amorphous layer, if the dose is high enough for it to form,
extends into the implant profile to a certain depth. During the anneal, the amorphous layer
generally regrows to the surface as a relatively defect-free, crystalline region (except for the
possible formation of twins nucleated at the amorphous/crystalline (a/c) interface and mask edge
effects) with high dopant activation. At depths below the a/c interface, damage annealing is
incomplete leading to the formation of an end-of-range (EOR) damage layer.
Figure 1.4.18. Leakage current in diodes formed by B and As implants at 25 C (RT) and –160 C
for various doses [Suguro01].

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Figure 1.4.19. Sketch of as-implanted and annealed damage for the same implant profile for low
and high damage accumulation rates. The amorphous layers after implant are indicated by gray
bands. (Graphics courtesy of M. Ameen of Axcelis).
For conditions of high damage accumulation rates (high ion mass and simultaneous impacts with
a large number of atoms (molecular and cluster ions), high beam currents and low wafer
temperature), the amorphous layer, for the equivalent implant conditions (ion, energy and dose),
extends deeper into the implant profile, leaving a smaller fraction of the total damage recoils
remaining below the a/c interface. During the anneal, the high-activation region in the re-
crystallized material above the a/c interface contains a larger fraction of the dopants in active
lattice sites, resulting in lower sheet resistance values. And with a smaller number of Si defects
(vacancies and interstitials) remaining below the a/c interface, the resulting defect structures (311
and loop dislocations) contain fewer Si atoms and are less dense than the lower damage rate
implants, leading to correspondingly lower leakage current levels (see Fig. 1.4.18 and related
discussion).
Damage accumulation effects in ion implanters
The implant conditions which effect damage accumulation vary widely with the design of
individual implantation systems. Among high-current implanters, there are 4 major types, (1)
fixed beams with multiple wafers mounted on rapidly spinning disks which are scanned at a
slower speed across the beam diameter, and single-wafer tools with (2) fixed ion beams with a
wafer mounted on a pendulum arm which is rocked back and forth across the beam and scanned
up and down across the beam height, (3) ion beams scanned in one direction (usually horizontal)
with vertical wafer motion across the scanned beam and (4) a fixed ribbon beam wider than the
wafer diameter and vertical wafer motion across the beam. In batch wafer tools with rapidly
spinning wheels, the tangential wafer velocity can be up to 90 m/s resulting in ≈0.25 ms beam
pulses (for a 2 cm beam height) separated by up to ≈50 ms (depending on the wheel batch size
and rotation speed). For single wafer tools with pendulum arm scanning, the wafer speeds are
much lower, resulting in longer exposures to the beam. And for ribbon beams, where the ions are
distributed at much lower current densities than a “spot” beam, the beam exposure times are
determined by the relatively slow (≈5 cm/s) vertical wafer motion of the mounting chuck
assembly.
Typical parameters for types of spot and ribbons beam implants are compared in Fig. 1.4.20
[Ameen08]. For the 2D mechanical single-wafer scanning, with a 25 mm spot beam and a
pendulum rocker motion, results in short beam pulses separated by ≈150 ms between the ion
pulses. The ribbon beam case results in a continuous ion beam exposure of the wafer, at 1 to 2
orders of magnitude lower local beam current density, as the wafer passes across the 25 mm beam
width. The higher local beam current density for the spot beam case can be expected to result in
lower amorhization doses and thicker amorphous layers for the same ion mass, energy, dose and
wafer temperature. Differences in the onset of amorphization also effect the depth profiles of the

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implanted ions due to varying effects of ion channeling in the early stages of the implant (for non-
pre-amorphized implants) [Ameen08].
Figure 1.4.20. Model implant conditions for a 13 wafer spinning wheel, and single wafer scans
with spot and ribbon beams (table) and ion flux rates over time for a single wafer scan through
scanning spot and ribbon beams (figure) [Ameen08].
Slowing ion beam scan rates, which vary the local ion flux rate, have a comparable impact to
increasing the ion current density, generally increasing the damage accumulation rate in the
target. A comparison of ion scan rates between 1.3 and 338 Hz in a scanning beam (SEN SHX
type) implanter showed a modest increase in the measured a-Si thickness for 6 keV C implants at
a dose of 1e15 C/cm2 at wafer temperatures of -40 and -60 C (Fig. 1.4.21) [Ninomiya11].
Figure 1.4.21. Measured a-Si thickness after 6 keV C implants using beam scan rates of 1.3 and
338 Hz and wafer temperatures of -40 and -60 C in a SEN-SHX scanned beam implanter
[Ninomiya11].

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Hot implants.
Although most of the recent interest in temperature-controlled damage rates has focused on
colder than room temperature implants, the study and use of hot implants is also a well-developed
process. There are three general regions of “warm” implants:
1. “Room temperature” implants, usually at temperature above a nominal “room temperature” of
25 C as a result ion beam heating. A nominal maximum temperature for these common-use
reference conditions is ≈120 C, at the onset of rapid volatilization of short-chained polymer
components (leading to the formation of gas filled blisters and break down of many commonly
used photoresist masks).
2. “Ion regrowth” conditions (approximately 125 to 500 C), where ion beam damage in the region
near the a-Si/c-Si interface of an existing amorphous layer will lead to regrowth of the amorphous
layer with increasing ion doses [Williams92].
3. “SIMOX” regime (approximately 500 to 700 C) where heavily implanted Si layers retain a
degree of crystallinity (if heavily damaged) at very high doses. This regime is used for formation
of buried SiO2 (and SiC or SiN) layers by a “Separation by IMplantation of OXygen” process at
doses in the 1e17 to mid-e18 O/cm2 range for manufacture of SOI wafers [Sadana06].
Figure 1.4.22. Temperature regimes for ion implantation processing of Si. The dashed line is the
estimated Si interstitial diffusion length within a time of 10 ms, taken to be the approximate
maximum time for post-impact ion damage to recombine to a stable “as-implanted” condition
during the implantation process. The Si interstitial diffusivity is derived from observation of
diffusion of thin B-doped layers in Si under ion damage surface layers [Gossmann93]. Note that
only in the SIMOX regime does the Si interstitial diffusion distance extend to a few atomic lattice
lengths, highlighting the importance of short-range relaxation and growth kinetics of small
amorphous pockets at lower temperatures [Mok08].
Ion stimulated regrowth of amorphous layers
In the “hot” implant regime, above room temperature, previously formed a-Si layers can be
stimulated to regrow by the passage of energetic ions through the amorphous layer (Fig. 1.4.23)
[Williams85]. Aspects of this behavior are presently under study to develop processes for high
dose-rate implants at elevated temperatures to dope thin finFET S/D regions without amorphizing
the fin volumes (see Fig. 1.3.8 and related discussion).

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Figure 1.4.23. Regrowth in an a-Si layer at 318 C stimulated by the passage of sequential
exposure to a 1.5 MeV Ne+ beam at a dose of 3e16 Ne/cm2 (left). The a-Si layer was formed by
an implant with 50 keV Si+ at a dose of 2.5e14 Si/cm2 at a temperature of 77 K. Prior to the 1.5
MeV Ne+ exposures, the a-Si was annealed at 450 C for 15 min to remove deep damage regions
and form a sharp a/c boundary. The efficient stimulation of a-Si regrowth by MeV ions extends
over a wide temperature range, with an apparent increase in regrowth rate for exposures above
400 C (right) [Williams85].
“Hot” implants for FDSOI doping.
The desire to implant dopants into thin fully-depleted layers and fins without creating entirely
amorphous layers which are difficult to anneal (see Fig. 1.3.8 and related discussion) has led to
recent interest in implantation in the “ion regrowth” regime from 150 to 500 C.
The effectiveness of direct implant doping into thin Si layers for FDSOI devices at high (up to
400 C) temperatures has been reported for the case of As implants. For relatively thick (28 nm)
Si on BOX, higher temperature implants resulted in lower net accumulated damage and lower
sheet resistance after annealing (Fig. 1.4.24). However, for the practical FDSOI Si thickness of 8
nm, the sheet resistance trends were reversed for the 400 C implants compared to room
temperature.

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Figure 1.4.24. Sheet resistance results for As implants into 28 (upper) and 8 nm (lower) Si layers
on BOX at room and elevated temperatures [K.Saenger08].
Looking closely at the As implants into 8 nm Si, as expected, the 400 C case resulted in
measurably less accumulated damage and lower damage levels after annealing (Fig. 1.4.25). This
was also confirmed by medium-energy backscattering analysis. However, ≈40% of the delivered
As dose was lost for the 400 C implant. The reduced dose retention in thin Si layers for As
implants at 400 C and above were confirmed in recent studies for thin SOI layers
[Mizubayashi13].
Figure 1.4.25. TEM images of as-implanted and annealed 8 nm Si on BOX for 0.75 keV As,
1e15 As/cm2 implants at 25 and 400 C. [K.Saenger08].
Kinetic Monte Carlo studies of implant damage formation and annealing in model fin structures
show the effects of implantation temperature on residual defect distributions as well as the details
of a-Si layer regrowth in the confined geometries of finFETs and other vertical device structures
(Fig. 1.4.26) [Noda13].

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Figure 1.4.26. Distributions, modeled by kinetic-Monte Carlo (KMC) calculation, of residual
defects in a model fin structure after 5 keV As (vertical) implants at implant temperatures from
-50 to 400 C and annealing under low-temperature solid-phase regrowth conditions [Noda13].
Note that, as the implant temperature increases, the density and length of {311} defects increases
and vacancy clusters (voids) appear near the implanted top surface above 300 C.
Process integration challenges to be solved for the use of implant temperature to control damage
accumulation include reduction of the effects of resist cracking and wafer vapor buildup for cryo
implants and development of hard mask techniques for implant temperatures above 125 C.
2.0. Materials modification:
The keynote talk at IIT10 in Kyoto featured a wide-ranging review and update to applications of
ion implantation for CMOS and organic devices as well as “bio” (medical sensors, etc.) and
“green” (power devices) (Fig. 2.0.1) [Tsukamoto10]. Most of the ions discussed in this review
were non-dopants (not As, B, P, Sb, etc.).
Figure 2.0.1. Example novel applications of ion implantation for Si and organic-based mobile
devices, power switching devices bio-medical applications [Tsukamoto10]. The detailed
numbered references are found in the IIT10 paper. Note that most of the ions are “non-dopants”.

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The diversity of modern implantation process is shown for an example of a 28 nm CMOS SOC
device, which includes ≈40 implant steps with a third of them being “materials modification”
implants using non-dopants (Ge, Xe, C, F, N) (Fig. 2.02). A wider look at CMOS implant
applications brings in additional ions (Al, La, S, Mg) and increases the number of “mat mod”
implants in modern process to become the majority of total implants per finished die (Fig. 2.0.3).
Additional implant applications for modification of metals, bio-active materials and optical
devices adds additional ions to implant process, Ta, Cr, Ni, Fe, Sn, Li, Cl, Cu, Ta, Er, etc.
[Larson11].
In this chapter we highlight three of the applications for Si-based CMOS devices, control of
dopant diffusion, local modification of plasma etch rates in oxides and stabilization of
photoresists in multi-litho exposure sequences.
Figure 2.0.2. Implant steps for 28 nm system-on-chip (SOC) devices. The use of optimized
doping for multiple on-chip threshold voltages leads to the use of ≈40 implant steps shown in the
dose-energy plot [Tsukamoto10].

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Figure 2.0.3. Summary of “new ions” in CMOS processing [Tsukamoto10].
2.1 Control of dopant diffusion by co-implantation of “cocktail” ions
Even when a sub-10nm dopant profile is achieved, the thermal processing required to
recrystallize the damaged Si lattice and to move dopants into electrically active, substitutional
sites also can lead to a substantial amount of dopant diffusion creating a deeper and less abrupt
profile. The detailed nature of the thermal cycles can vary over a wide range of temperatures,
time and ambient atmospheres, with each combination producing characteristic effects. The
effects of even a relatively short (≈1 sec) and modest peak temperature (1050 C) anneal can be
seen in Fig. 2.1.2 (left) where the 500 eV B implanted profile shifts approximately twice as deep
after annealing. The range of thermal cycles used for implant annealing of shallow junctions can
range from 500 to 800 C for several minutes associated with solid-phase epitaxy (SPE) regrowth
of amorphous layers containing dopant profiles, to “rapid thermal processing” (RTP) anneals at
900 to 1100 C for times of several seconds to ≈1s for “spike” cycles, to very short (sub-msec)
thermal pulses to peak temperatures of 1300 to >1400 C achieved by scanned laser beams or
whole-wafer “flash” lamp bursts. In all shallow junction annealing, controlling dopant diffusion
within precise (and usually minimal) amounts is central goal of the process design.
The initial diffusion rates of dopants, during the ramp-up to peak temperature and the first
seconds of the “soak” at full temperature, can be substantially higher than later in the anneal
cycle. Since dopant diffusion is strongly effected by the local concentrations of lattice defects,
with B and P diffusing rapidly in partnership with Si interstitials, these dopants often move at
high rates until the lattice defect population is depleted of mobile interstitials through
recombination with vacancies and trapping into extended defects and the “transient enhanced
diffusion” (TED) phase is completed.
A particularly effective utilization of the properties of Si defects is the use of “cocktail” implants
to control the diffusion of certain dopants. In this method, deep pre-amorphization implants with
Ge or Si are combined with implants of “cocktail” atoms, such as F, C, N, S, etc. along with
shallow implants of dopants that diffuse rapidly in the presence of Si interstitials, such as B or P.
The process starts with a Si or Ge implant creating an amorphous layer deeper than the desired
final junction depth. Then shallow dopant atoms and “cocktail” elements are implanted so that
the cocktail atoms are deeper than the dopant profile but still within the amorphous layer (Fig.
2.1.1). When the combined implants are annealed in an RTP at ≈1050 C, the deep amorphous
layer regrows early in the anneal cycle leaving an interstitial-rich array of defects at and just
below the amorphous/crystalline interface. As the anneal continues and Si interstitials are

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released from this layer of “end-of-range” (EOR) damage, they are trapped in the region where
the cocktail atom co-implant is located, if those atoms are chosen for their ability to form
immobile defect clusters. The shallow dopant atoms diffuse deeper into the Si but not at the rate
that would occur in the presence of the Si interstitials flowing from the EOR damage and the net
effect is a shallower, more abrupt dopant profile.
Figure 2.1.1. Sketch of atom profiles and defect locations for “cocktail” co-implantation process.
The success of the use of C co-implants and deep pre-amorphization along with B and P dopants
is shown in Fig. 2.1.2, where the junctions are much shallower and more abrupt than for the use
of the dopant atoms only in the same anneal. The strength of the impact of the co-implants on
modifying normal diffusion behavior can be seen in Fig. 2.1.3, where increasing the peak
temperature of the RTP cycle from 1030 to 1070 C results in deeper junctions, as expected,
however the profiles are much shallower than expected for un-restricted diffusion and the slope of
the profile edge, abruptness, is essentially unchanged, in contrast to the broadening of the profile
edge expected for normal diffusion processes. By providing a means to increase dopant
activation by annealing at higher temperatures with only a modest cost in increased junction
depth, co-implanted “cocktail” processes offers considerable opportunity for process
optimization, especially for tailoring of SDE lateral diffusion for proper amounts of gate overlap.

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Figure 2.1.2. SIMS profiles for 500 eV B (left) and 1 keV P (right) implants as implanted and a
after 1050 C spike RTP anneals. The C implants were at doses of 1015 C/cm2 at energies of 2, 4
and 6 keV. The PAI for the B profiles was 20 keV Ge at 5x1014 Ge/cm2 and for the P profiles
was 25 keV Si at 1015 Si/cm2 [Collart06].
Figure 2.1.3. SIMS profiles of 0.2 keV B (left) and 0.5 keV P (right) implanted at a dose of
7x1014 B/cm2, with Ge (for B) or Si (for P) pre-amorhization and C co-implants annealed at 1030,
1050 and 1070 C [Pawlak06a. Pawlak 06b].
Cocktail co-implant effects on leakage current
Since the placement of the “cocktail” co-implant profile, deeper than the dopants and shallower
than the EOR damage (see Fig. 2.1.1), the co-implanted atoms, combined with trapped Si
interstitials, can nucleate electrically active defects in the depletion layer near the dopant junction
depth. These conditions result in strong SRH and TAT leakage currents for both forward and
reverse biased junctions. The level of leakage current appears to depend on the chemistry of the
co-implanted atoms, with C and combinations of C and F ions resulting in higher leakage currents
than the use of F atoms alone for the “cocktail” implant (Fig 2.1.4).

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Figure 2.1.4. Reverse bias leakage for BF2-doped junctions combined with co-implants of Ge, C
and F and annealed with RTP-spike (1030 to 1070 C, ≈1 s) cycles [Pawlak06c].
2.2. Implantation effects on local etch rates.
The mixing of plasma chemistries to form local mask layers, often made up of compounds of F, C
and other components of the plasma gases, are fundamental techniques in high-selectivity etching
in IC and MEMS fabrication. Ion implantation of similar ions (F, C, O, N, etc.) used in plasma
processing can provide a combination of results, local modification of etch rates as well as
changes in the film dielectric properties, for instance. The etch selectivity for a high-C content
Si is widely used for formation of MEMS structures, with selectivity in the range of 102 to 103 for
C concentrations in the range of ≈1021 C/cm3 (Fig. 2.2.1).
Figure 2.2.1. Etch selectivity for C implanted Si in EDP and KOH solutions. [Goesele99].

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Fundamental mechanisms in etching reactions related to ion implantation.
The etch rates of Si and related forms of oxides and nitrides can be changed by local implantation
which change (1) material damage levels, (2) doping levels (in semiconductor materials) and (3)
key pathways in autocatalytic reactions. There are additional effects on etching following ion
implantation, including residual stress effects and chemical reactions. Both of these types of
effects are enhanced by thermal processing after the implant and before the etch step.
1. Damage and amorphization effects on etch rates
The local degree of lattice damage (in the case of Si or Ge) or broken bonds (in the case of
dielectrics such as SiO2 and Si3N4), caused by the stopping of energetic ions from ion
implantation or reactive-ion etching (RIE) and high-power laser ablation, can greatly increase the
etch rates for certain etching chemistries.
Damage related etch rate increases increase proportional to the dose of arriving energetic ions and
the fraction of the ion kinetic energy which is lost during stopping in the surface due to scattering
and recoil events between the ion and the core electrons and nucleus of the target atoms
(“nuclear” stopping power). The net damage effect tracks with the “deposited energy”, the
product of the nuclear stopping power, Sn, and the ion dose,  The degree of damage does not
depend on chemical reactions but only on the masses and electronic configurations of the ion and
target atoms (see Fig. 2.2.2 (left). Damage effects on etch rates saturate at a deposited energy
sufficient to result in ≈16% volume fraction of broken bonds (in the case of SiO2) or the creation
of an amorphous surface layer (in the case of Si and Ge).
Figure 2.2.2. Etching of SiO2 in 3% HF solution (left) and with vapor-phase HF (right) after
implantation damage with various ions [Charavel06].
In some cases, the effect of damage is also related to a surface chemical effect. Note the
difference in scale in etch rates between the wet HF etch rates and vapor-phase HF (Fig. 2.2.2) for
ion damaged SiO2. In both cases, the oxide etch rate increases strongly for heavily damaged
surfaces. However the effect of ion damage on etch rate is much greater for the case of vapor-
HF etching.
In the case of oxide etching with HF, the detailed reaction begins with the formation of active
HF2- radicals in the presence of water. In the case of the aqueous HF etch, the H2O is present in
copious amounts from the 97% fraction of water in the solution. However, in the case of vapor-
HF exposure, there is no H2O present on the surface at the start of the etch cycle, so the oxide
removal rate is minimal. But once some HF-SiO2 reactions occur, even at low levels, H2O is
produced as one of the reaction products. The presence of the product-H2O now greatly
increases the rate of the overall reaction in the areas that have been damaged by energetic ions

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prior to the etch cycle. Such reactions, where a reaction product (in this case, H2O) also
encourages further reactions, are called “autocatalytic”. The net effect of ion damage and the
autocatalytic chemistry greatly increases the selectivity (ratio of etch rates for damage and un-
damaged oxide) for vapor-HF etching.
2. Doping effects on etch rates
Implantation of dopants is widely used to change the etch rates of Si and Ge. The detailed
mechanisms have been linked to (a) the induced local stress after annealing with the incorporation
of the dopant atoms (see Fig. 2.2.3, left) and (b) changes in surface reaction rates due to the
presence of extra mobile carriers from the activated dopants (Fig. 2.2.3, right).
Figure 2.2.3. Etch rate in Boron-doped poly-Si and c-Si B in a 20% solution of TMAH (Tetra
Methyl Ammonium Hydroxide) etch at 80 C (left) and removed layer thickness for poly-Si doped
with B and As in [1:1:2] HNA (hydrofluoric, nitric and acetic acids) in a static solution (right)
[Charavel06].
The decrease in Si etch rates (for KOH and other etches) for heavily B-doped materials is widely
used in MEMS fabrication to serve as an etch stop layer. The B doping can be accomplished by
an epitaxial deposition step early in the process or by implantation doping prior to etching. In the
case of Si etching in KOH (potassium hydroxide) or EHP (ethylene diamine pyrocatachol)
solutions, the etch rate drops to very low levels for highly doped (>1020 h/cm3) p-Si (an opposite
trend than the case shown for HNA in Fig. 2.2.3 right).
In another example where the doping effect depends on the specific etch chemistry, heavily n-
doped poly-Si etches quickly in Cl+ based plasmas. However, the doping effect on etch rate is not
present in F+ based plasma etching [Reyes-Betano03].
3. Selected autocatalytic etching reactions.
Autocatalytic reactions produce reaction products that influence the reaction rate. An example is
the etching of SiO2 by HF (in solution, vapor and plasma environments). Details of the
mechanism depend on the local pH and concentration of primary components and various buffers.
HF etching of SiO2 also changes with various forms of oxide with different densities and
chemical bonding; formed by thermal reactions (as “dry” or “wet” (H2O containing atmospheres
of O2), by CVD and sputter deposition, etc.) [Knotter09]. For conditions where H2O on the
surface is scarce, such as in vapor-HF flows and plasma environments, the product H2O from
low-rate initial reaction is a catalyst for initiation of the more rapid reaction outlined above (see
Fig. 2.2.2, right).

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Etching of Si in HNA solutions has far more complex chemistry, with various local Si surfaces,
acting as anodic and cathodic sites in sequence, leading to Si oxidation and oxide dissolution
[Darling12]. The important intermediary in the HNA reaction on Si is HNO2, which assists the
oxidation of Si and acts as an autocatalytic agent. In acid baths that are agitated by stirring and
ultrasonic vibrations, reaction products are rapidly removed from the etched surface and
dissolved into the solution. However, for heavily-doped Si, the presence of free carriers
increases the formation rate of important intermediate reaction products such as HNO2. So for
heavily doped (>1019 carriers/cm3) Si, the HNA etching reaction is sustained, even with strong
solution agitation, resulting in strong etching action for heavily-doped compared to more lightly
doped regions (Fig. 2.2.4).
Figure 2.2.4. Etched thickness in Si doped with B and As in [1:2:3] HNA in a stirred, ultrasonic
mixed solution [Charavel06].
Plasma etching reaction paths “mimic” many cases of wet etching reactions, with additional
complications from more diverse intermediate elements, multiple charge states, energetic ion
impacts, variable evaporation rates and partial pressures and generally less well-known specific
reaction rates between components. The net effect is that the influence of ion implantation,
through damage and doping effects, on plasma etching rates is still a highly empirical art form,
evolving continually.
2.3. Photoresist “freezing” for multi-exposure lithography
Ion implantation has long been used to pre-condition photoresist (PR) patterns for various
processes, such as adding a deep cross-linked and C-rich skin to PR for enhanced durability
during exposure to reactive ion etch plasmas and to reduce the amount of PR outgassing for
sensitive dopant implants in order to avoid dose errors.
With the extended use of sub-wavelength optical patterning, ion implant conditioning and the
resulting PR line shrinks have become a routine process. With the elaboration of litho patterning
to include dual and quad exposures, the effects of ion implant conditioning have been extended to
include enhancement of the adhesion of multiple litho patterns of PR to the underlying wafer
coatings and reduction of line edge and line width roughness [Samarakone11].
PR line shrinkage with ion implantation is illustrated in Fig. 2.3.1 for a dual-exposure process.
The usual ion for PR conditioning is Ar+, mainly for its ease of use and relative lack of process
complications.

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A key challenge for dual-exposure litho process is that the first level PR layer needs to stay in
place throughout the spin coat, exposure, develop and curing of the second layer. If the first
level PR adhesion to the wafer is not sufficient, the solvents in the develop cycle of the second
layer can de-laminate the PR lines (Fig. 2.3.2).
As the C-rich crust forms on the surface of the PR line, the dimensional integrity of the printed
line increases as the surface “stiffens” and solvent absorption decreases. These effects improve
both the line edge and line width roughness of fine lines, especially if the implant included
exposures with high beam tilt angle so that the sides as well as the tops of the PR line are
encrusted [Martin10]. The effects of both adhesion and line roughness improvements with ion
implantation are shown in Fig. 2.3.2.
Figure 2.3.1. Sketch of PR lines for a dual-exposure process utilizing ion implant line shrinks.
Figure 2.3.2. PR lines implanted with 2 keV (left (a)) and 5 keV (left (b)) Ar+ ions showing
resist lifting after subsequent processing for the 2 keV case and shrinkage of PR line width, CD,
and reduction of line width roughness, LWR, with 2 and 8 keV Ar+ ion implants into PR (right)
[Martin11].
Ion beam effects on photoresists.
As ions are stopped in organic PR masks, many local bonds are broken by the ion and secondary
recoil atom impacts. This forms a C-rich, heavily cross-linked “crust” is formed with a depth
roughly equal to the full extent of the implanted ion profile [Hattori09, Oerhlein11]. Detailed
measurements of G-rich crusts formed after high-dose implants give a crust thickness equal to the

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ion beam range, <X>, in the resist plus 3 times the straggling, <X> (Fig. 2.3.3). As the C-rich
crust is formed, the PR line shrinks in both the vertical and lateral directions.
Figure 2.3.3. Sketch of ion beam effects on photoresist, showing outgassing of volatile resist
materials leaving a C-rich surface crust and formation of H2-filled bubbles under the crust layer
(if the wafer temperature during implant rises above the decomposition point of short-chained
resist components) (left) and ion range and crust thickness for As, B and BF2 implants (plot based
on data from Hattori09).
Detailed measurements of Ar+ ion energy, dose and incidence angle on PR adhesion and LER
showed the positive effects of low-energy bombardment with strong side-wall exposure (Fig.
2.3.4) [Kikuchi11].
Figure 2.3.4. Line edge roughness (LER) for Ar ion exposures showing the usefulness of low-
energy beams and large tilt and twist angles [Kikuchi11] (left) and sketches of crust layer
thickness and location for various ion beam incidence on a resist line.
3. H-Cut Wafer Splitting for membranes, laminated materials and 3-D CMOS
Hydrogen implantation at high enough doses (≈5x1016 H/cm2) to induce planar lateral splitting in
crystalline Si, Ge and GaAs, etc., under proper conditions has been used for the last decade to
manufacture silicon-on-insulator (SOI) wafers as well as for lamination of diverse types of
photonic and photovoltaic materials and structures [Soitec12, Atwater03, Henley08]. The
development of high-current beamlines for higher energy, up to several MeV, proton beams has
led to commercial applications for formation of free-standing membranes of Si, sapphire and
other materials [Henley08, GTAT]. In addition, increasing attention is being paid to the options

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for H-cut implants for direct lamination of CMOS device layers to for 3-D circuit arrays [Or-
Bach11, Koyanagi13].
The effects of high-dose H implant into Si are sketched in Fig. 3.1. For relatively shallow H
implants, up to a few hundred nm, into an exposed Si wafer, H2-filled surface blisters form during
the implant and during subsequent thermal processing. The thickness of the blister skin is equal
to the H range in Si, increasing with energy. If the H-implanted Si wafer is bonded to an oxidized
“handle” wafer before thermal processing, the chemical etching of Si by the accumulated H
atoms results in the formation of thin “platelet” voids aligned along the wafer surface plane in
Si(100) at the depth of the H implant peak. If this bonded pair of wafers is heated to ≈450°C or
subjected to appropriate mechanical force, a planar “cleave plane” will form along the platelets in
the H-rich region and the wafers can be separated. After removal of the H-rich damaged layer,
the handle wafer, oxide, and transferred layer becomes an SOI wafer ready for CMOS and
photonic device processing. If a higher energy proton beam is used to implant H at a deep
enough location, the overlying Si is stiff enough to drive the formation of planar platelets rather
than surface blisters, without the need for the bonded handle wafer.
Figure 3.1. Schematic for high-dose (≈5x1016 H/cm2) implants into Si for (left) a shallow H
profile into an open Si wafer surface, resulting in surface blisters, (middle) a shallow H profile
with an oxide covered Si handle wafer bonded to the implanted wafer before thermal treatment,
resulting in Si layer splitting and (right) a deep H profile into a Si wafer, resulting in a free-
standing membrane after layer splitting.
Monte-Carlo calculations [Ziegler] of H and target atom recoil profiles for high-dose, low and
high-energy proton profiles in Si and sapphire are shown in Fig. 3.2. The residual damage
associated with the target recoils during the ion stopping is important for H implants because H
diffuses easily in Si and migrates away from the initial stopped profile unless it is trapped by
local defects. The resulting H distribution follows the damage profile, peaking near the H range
but slightly shallower than the initial H depth profile. For a 40keV H profile, typical of SOI
wafer and photonic materials fabrication, the H depth and transferred layer thickness is ≈0.4 μm.
For a 2 MeV proton beam, used for splitting of free-standing Si membranes for low-mass
photovoltaic cells, the range and thickness is ≈50 μm. A 1 MeV proton beam results in 20 um
free standing sapphire membranes [Ryding14].

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Figure 3.2. Monte-Carlo (SRIM) calculations of initial H and Si primary recoil distributions for
high-dose, 40 keV and 2 MeV protons in Si and 1 MeV protons into sapphire.
H-cut splitting can be accomplished in a number of ways, such as thermal splitting at ≈450°C for
≈30 min [Soitec12], mechanical separation at room temperature [Current00b], by exposure to
microwave radiation for short periods of time [Thompson05] and thermal stress from high-power
laser scans [Henley07]. The heavily damaged and H-rich layer that surrounds the cleave plane
can be removed by chemical-mechanical polishing (CMP) [Soitec12], exposure to H2 at
temperatures above ≈1100°C [Thilderkvist00], or by specialized etching and polishing
procedures, leaving relatively un-damaged crystalline material in the transferred layer.
Measurements of carrier recombination rates in free-standing Si membranes, an important
consideration for PV cell materials, indicate that high quality Si material survives the passage of
high-dose MeV proton beams [Henley08].
H-cut techniques are envisioned to play a central role in formation of 3D ICs [Or-Bach11,
Koyanagi13]. In the methods proposed by MonolithIC 3D, a completed CMOS circuit, stopping
at the S/D contact formation, is implanted with H at a depth sufficient to separate the device level
from the fabrication wafer. Then a temporary bond is made to a transparent handle wafer and the
CMOS device layer is separated from the wafer, aligned with a fully interconnected 2nd CMOS
device layer and bonded to it. The 3D structure is completed with the fabrication of shallow vias
and interconnects linking the two device layers. Many similar 3D integration methods have been
explored, including bonding of CMOS device layers formed on SOI wafers thinned by removal of
the handle wafer material by grind and etching methods using the buried oxide layer as an etch
stop [Guanari02]. It is estimated that proton acceleration to less than 50 keV would be sufficient
to implement the process shown in Fig. 3.3, with a cleave plane depth of less than 500 nm and the
use of a temporary bonded carrier wafer.

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Figure 3.3 Schematic of the use of H-cut techniques to split away a completed CMOS front end
device (upper) and laminate it to a fully metalized 2nd CMOS layer, to be connected by vias and
final metal layers (lower) [Or-Bach11].
5. Summary
The use of ion implantation for doping of CMOS source/drains and gates has extended the scaling
of transistors to the “end of the roadmap” for planar CMOS with gate electrode lengths of ≈20 nm
and SDE junction depths of less than 10 nm. The transition to fully-depleted planar and vertical
channels is well underway in logic, memory and power devices. The interesting story going
forward will be the increasingly complex interplay of ion beam and CVD-type methods for
formation and doping of 3D device structures.
New technologies, such as the use of individually implanted dopants in precise locations to form
Qbit structures for “quantum computers”, and use of alternative semiconductor materials for
high-mobility channels, such as Ge, III-V alloys and C-based nano-tubes, will be discussed in
papers at the Ion Implantation Technology conference that follows this school. Looking beyond
the fabrication of CMOS-based switching circuits towards the development of new switching
technologies and the more immediate prospects for integration of electrical and optical signals in
“photonic” materials and devices, the utility of providing additional atoms to materials and
devices with the precision and economic efficiency which are hallmarks of ion implantation
techniques point to long and fruitful careers for young, inventive process engineers.
The key to progress is always the recognition that innovation is not a “commodity” item. The
complexity of the materials challenges and economic pressures for “quick and cheap” solutions
continues, as always, to limit the apparent options for innovative engineering. We hope that this
school will contribute to the education of young ion implantation process engineers and machine
designers and provide information and ideas that, against all the usual odds and with a lot of hard
work, luck and gumption, will result in new miracles.
“The best way to predict the future is to invent it.” Alan Kay.
Acknowledgements
The author wishes to thank many contributors to the work described in this chapter and in
particular, Takeshi Kuroi at Renesas, Amitabh Jain at Texas Instuments (now at Global
Foundries), Susan Felch previously at Varian for many years (now independent), Paul Timans at
Mattson (now independent), Dale Jacobon at SemEquip (now at Coherent), John Hautala at Epion
(now at Varian) and Mike Mack at Epion (now at Cape Ann Technology LLC).

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