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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014 2575
Analysis and Design of a High-Order Discrete-Time
Passive IIR Low-Pass Filter
Massoud Tohidian, Student Member, IEEE, Iman Madadi, Student Member, IEEE,and
Robert Bogdan Staszewski, Fellow, IEEE
Abstract—In this paper, we propose a discrete-time IIR
low-pass filter that achieves a high-order of filtering through
a charge-sharing rotation. Its sampling rate is then multiplied
through pipelining. The first stage of the filter can operate in
either a voltage-sampling or charge-sampling mode. It uses
switches, capacitors and a simplegm-cell,ratherthanopamps,
thus being compatible with digital nanoscale technology. In the
voltage-sampling mode, the gm-cell is bypassed so the filter is
fully passive. A 7th-order filter prototype operating at 800 MS/s
sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth
of this filter is programmable between 400 kHz to 30 MHz with
100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the
averaged spot noise is 4.57 nV/ Hz. It consumes 2 mW at 1.2 V
and occupies 0.42 mm2.
Index Terms—CMOS, digital equalization, discrete time, high
linearity, high order, IIR, low noise, low-pass filter, low power, pas-
sive, real pole, reconfigurable, switched capacitor.
I. INTRODUCTION
INTEGRATED low-pass filters (LPFs) are key building
blocks in various types of applications, such as wireless
communications [1]–[7], hard-disk drive read channel [8], [9],
video signal processing [10], smoothing filtering in a DAC
[11], and anti-aliasing filtering before a sampling system. Noise
of these filters is one of the key system-level concerns. This
noise can be usually traded off with the total filter capacitance
and, consequently, total power and area. Therefore, for a given
system-level noise budget, a filter with a lower noise coefficient
reduces the area and power consumption. On the other hand,
linearity of the filter should be high enough to maintain fidelity
of the wanted signal.
As shown in Fig. 1, three types of commonly used analog
filters are Gm-C, active RC, and active switched-capacitor
(SC) filters [12]–[17]. In Gm-C and active RC filters, pole/zero
locations are set by value, capacitance (C),andresis-
tance (R). Due to the poor matching of /C and R/C values,
Manuscript received April 21, 2014; revised July 18, 2014, July 22, 2014;
accepted September 13, 2014. Date of publication October 13, 2014; date of
current version October 24, 2014. This paper was approved by Associate Ed-
itor Anthony Chan Carusone. This work was supported in part by the EU ERC
Starting Grant 307624.
The authors are with the Electronics Research Laboratory/DIMES,
Delft University of Technology, 2628CD Delft, The Netherlands (e-mail:
m.tohidian@ieee.org).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2014.2359656
Fig. 1. Conventional analog filters: (a) Gm-C, (b) active-RC, and (c) active
switched-capacitor.
process-voltage-temperature (PVT) variations have consid-
erable impact on filter transfer function. Therefore, many
applications require component (i.e., ,R,andC) calibra-
tion/tuning [16], [17]. However, pole/zero locations of active
SC filters are accurately set by capacitor ratio, thus minimizing
the effect of PVT variations.
Implementation of such filters in deep nanoscale CMOS is
becoming increasingly difficult, especially due to the design
challenges of high-quality opamps and high-linearity gm-cells.
In contrast, switching performance of MOS transistors is im-
proving due to the technology scaling. Consequently, passive
switched-capacitor filters are expected to work at much higher
sampling rates than do the active SC filters, where the speed is
limited to opamp settling. Also, the passive filters will consume
much less power. However, it might not be possible to synthe-
size complex poles in a fully passive structure.
The passive LPF proposed in this paper benefits from these
advantages. Using a sampling capacitor to rotate charge be-
tween several history capacitors, a high-order IIR low-pass filter
is created. To further increase sampling rate, a pipelining tech-
nique of the sampling capacitor is introduced. Using these tech-
niques, a 7th-order LPF is implemented, that operates up to
1 GS/s [18]. In [1]–[5], passive switched-capacitor FIR/IIR fil-
ters have been used for baseband signal processing of an RF re-
ceiver. However, none of the prior publications have proposed
such a high-order passive filtering in one stage. A somewhat
similar structure resembling the charge rotating filter has been
reported in [19]. However, a 3rd-order LPF filter is used in an
N-path filter to form a band-pass transfer function. Furthermore,
0018-9200 © 2014 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/
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2576 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014
its LPF does not exploit any pipeline techniques such as one in-
troduced in this work.
The proposed filter has a very low input-referred noise, be-
cause of using only one sampling capacitor for all the filtering
stages. Thanks to the passive operation, it has an extremely high
linearity. A simple invertor-based gm-cell might be used in front
of this filter to provide gain. This filter consists of only switches,
capacitors, a clock waveform generator, and a simple gm-cell.
Therefore, it is amenable to the digital deep nanoscale CMOS
technology. The proposed filter has been successfully verified
at the system level in a discrete-time superheterodyne receiver
[6]: The 6th-order charge-rotating filter is employed there as the
first baseband channel selection filter.
The rest of this paper is organized as follows. Section II
provides an overview of basic DT passive LPF. Section III
describes the proposed high-order DT filter. Design and
implementation of the filter are described in Section IV.
Section V summarizes measurement results. Section VI pro-
vides the conclusion.
II. BASIC DISCRETE-TIME LOW-PASS IIR FILTERS
A. First-Order Filter
Perhaps the simplest analog discrete-time (DT) filter is a pas-
sive 1st-order IIR low-pass filter, as depicted in Fig. 2(a) [20].
In each cycle at , a sampling capacitor samples a con-
tinuous-time input voltage . Hence, we call it a voltage
sampling filter. Then at shares its stored charge with a
history capacitor .Attheendof , we have the following
equation for the discrete-time output voltage:
(1)
Hence, its transfer function can be written in z-domain as
(2)
where coefficient is . This is a standard form
of a DT LPF with unity dc gain and half-a-cycle delay, .
Switch driving clock waveforms are shown in Fig. 2(c).
The step response of this filter is shown in Fig. 3(a). and
are chosen 1 pF each, just for illustration’s sake. Discrete-
time output samples are available in each cycle at the end of .
Fig. 2(b) shows an alternative 1st-order DT LPF (IIR1) ex-
ploiting charge sampling [2], [20], [21]. At first, the contin-
uous-time input voltage is converted into current by the gm-cell
of transconductance gain . This current is integrated over a
time window on and during and on during
. However, we can assume for simplicity that discrete-time
input charge packets arrive only at :
(3)
Although this assumption slightly changes transient waveforms
of and voltages, it leads to exactly the same values of
the output samples while simplifying the analysis of the filter.
Fig. 2. (a) Voltage sampling and (b) charge sampling 1st-order DT IIR filter
with (c) their clock waveforms.
Fig. 3. Step response of (a) the voltage sampling, and (b) charge sampling 1st-
order DT filter ( pF, mS, GHz, and
MS/s).
During shares its charge with and a new charge is
input. Consequently, we have the DT output samples at the end
of :
(4)
(5)
The step response of this filter is shown in Fig. 3(b). In this
example, and are 1 pF and is 0.5 mS.
Fig. 4 shows top-level behavioral models of the IIR1 filters.
In the voltage-sampling structure of Fig. 4(a), the sampler first
TOHIDIAN et al.: ANALYSIS AND DESIGN OF A HIGH-ORDER DISCRETE-TIME PASSIVE IIR LOW-PASS FILTER 2577
Fig. 4. Top-level block diagram model of (a) voltage sampling, and (b) charge
sampling IIR1.
Fig. 5. (a) Wideband transfer function, and (b) Bode plot frequency response
of IIR1 ( pF, pF, mS, GHz, and
500 MS/s).
samples the continuous-time (CT) analog input voltage
at and converts it into a DT analog voltage. Then, this signal
is fed to a 1st-order LPF with half-a-cycle delay and the
output comes out every cycle at . DC voltage gain of this filter
is unity. Based on the Nyquist sampling theory, sampling of a
CT signal folds frequencies around (for )
into around dc, where is the sampling frequency. As depicted
in Fig. 5(a), we observe the folding image frequencies at ,
, and so on. Fig. 5(b) shows the transfer function, which has
a roll-off of 20 dB/dec.
A behavioral model of the charge-sampling IIR1 is depicted
in Fig. 4(b). Integrating the gm-cell current in the time window,
as described in (3), forms a CT sinc-type antialiasing filter prior
to sampling [2], [20]–[22]. The transfer function of this win-
dowed integration (WI) from the input voltage to the output
charge is
(6)
This sinc-shape filter has notch frequencies at
. Assuming ideal clock waveforms, is
thesameas . In the next step, the sampler converts
the CT signal to a DT signal and, at the end, a 1st-order DT
LPF performs the main filtering. As shown in Fig. 5(a), notch
frequencies of the antialiasing filter are on top of the folding
image frequencies, thus offering some protection. DC voltage
gain is calculated by multiplying the dc gain of the antialiasing
filter by the dc gain of the DT filter:
(7)
In this equation, is an equivalent DT resistance of the
sampling capacitor.
B. Second-Order Filter
As shown in Fig. 6(a), a 2nd-order DT low-pass filter (IIR2)
can be synthesized by adding a second history capacitor to the
charge sampling 1st-order LPF [1], [3], [7], [20]. The previously
analyzed charge sampling filter, IIR1, is indicated here within
the blue dotted box.
At the end of contains the output sample of the IIR1.
Then, by connecting to a second history capacitor at
, another 1st-order LPF is formed, whose structure is indi-
cated within the red dashed box in Fig. 6(a). Then at ,the
remaining history of is cleared by discharging it to ground.
This ensures proper operation of the first IIR1. The transfer
function of this filter is plotted in Fig. 6(b). The 2nd-order IIR
filter has a 2x steeper slope of 40 dB/dec compared to the IIR1
with 20 dB/dec.
III. PROPOSED HIGH-ORDER DT IIR LOW-PASS FILTER
Many applications require higher orders of filtering. The eas-
iest way to build a high-order filter is to cascade two or more
1st and/or 2nd order filters. A similar approach has been used
in [2] and [4], where two gm-cells and passive filters are cas-
caded. However, extending the IIR filter order using the con-
ventional approach carries two serious disadvantages: First, the
active buffers between the stages worsen both the noise and lin-
earity. Second, the increased reset-induced charge loss on each
stage of filter lowers signal-to-noise ratio. We propose a new
structure that does not suffer from these handicaps.
A. Charge Rotating DT Filter
Before introducing a new high-order filter, the IIR2 is re-
drawninFig.7(a). is placed at the center of the (as yet in-
complete) circle. In each cycle, is “rotating” clockwise and
is sequentially connecting to ,, and then ground.
To extend this idea, we add in Fig. 7(b) a few phase slots
between and the last reset phase, together with more history
capacitors. By moving to the next new phase, which
2578 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014
Fig. 6. (a) Second-order DT low-pass filter and (b) its frequency response
(pF, mS, GHz, and MS/s).
now holds the sample of the 2nd-order filter, shares its charge
with a third history capacitor . This charge sharing creates
another IIR1, cascaded with the previous IIR2. Hence, we now
have a 3rd-order filtering function on that can be read out
at the end of . We can continue doing so until the seventh
history capacitor (or arbitrarily higher), in order to make a
7th-order filter. In the last phase is finally reset. Since
the capacitor rotates charge between the history capacitors,
we call this structure a “charge rotating” DT filter. As shown at
the bottom of Fig. 7(c), required multiphase clock waveforms
to drive the switches can be generated from a reference clock.
Compared to the IIR2 structure in Fig. 6(a), the new charge
rotating (CR) structure preserves its gain and linearity even
at much higher filtering orders. The gain remains the same
simply because no additional charge loss occurs in the system.
In this filter structure, the switched-capacitor circuit is remark-
ably linear and so the gm-cell appears to be the bottleneck of
the linearity.
B. Step Response
To better understand the operation of the filter, its step re-
sponse is plotted in Fig. 8. At first, suppose all the capacitors
are empty. For simplicity, we choose pF. Also,
we suppose that the input charge packet pC arrives
every cycle at . A zoom-in of the step response is plotted in
Fig. 8(a). At , the input charge is transferred to and
that sets the 0.5 V potential on both capacitors. , which con-
tains a sample of the 1st-order filter at the end of ,isthen
Fig. 7. (a) The IIR2 is redrawn. (b) Charge rotating 7th-order filter with (c) its
clock waveforms. A closed switch is shown with a solid arrow, and an open
switch is shown with a dimmed dashed arrow.
connected to at . The result is 0.25 V on both capac-
itors. Next at ,, containing the sample of the 2nd-order
filter, is connected to and the result is 0.125 V. In this
way, transfers charge from one history capacitor to the next
until . Then, it gets reset at . As plotted in Fig. 8(b),
the outputs of higher-order stages are growing more slowly.
This is because their respective input samples have been accu-
mulated several times earlier, meaning slower but longer and
smoother integration.
C. Transfer Function
Considering that samples of the main output are
ready at the end of , we have (8), shown at the bottom of
TOHIDIAN et al.: ANALYSIS AND DESIGN OF A HIGH-ORDER DISCRETE-TIME PASSIVE IIR LOW-PASS FILTER 2579
Fig. 8. (a) A zoom-in and (b) the whole step response of the charge rotating
IIR7 ( pF, mS, GHz, and
125 MS/s).
the page. In these equations, each in the discrete-time ar-
gument means one phase delay. At is a function of its
value at previous cycle ( 1 delay) and a sample that comes
from the previous phase ( delay). Likewise, charge sharing
equations from to are derived. Converting all these equa-
tions into z-domain, we can derive the following general equa-
tion for different outputs:
(9)
for . In this equation, .
Normally, we prefer to have all the poles identical and so we
choose all the history capacitors of the same size
. Then the transfer function of the main output (i.e., )is
simplified to
(10)
From this equation, dc gain of from the input charge, ,is
. Then, by using (6), the overall dc gain of this filter from
the input voltage to its output is
(11)
In this equation, is the time period of the cycle, i.e., the
8 phases. Also, is an equivalent dc resistance of the
sampling capacitor. This filterhasthesamedcgainastheIIR2
filter in (7).
For frequencies much lower than , we can use bilinear
transform to obtain the continuous-time transfer function of
the filter:
(12)
This equation is similar to a transfer function of an RC LPF,
i.e., . Poles of this equation are all located at
. It indicates that bandwidth of this filter only de-
pends on the ratio of capacitors and the sampling frequency, thus
making it much less sensitive to PVT variations. This salient
feature eliminates any need of calibration, which is necessary
for other filter types [12]–[17].
Transfer functions at the outputs of different orders are shown
in Fig. 9. The slope of the 7th-order output transfer function
reaches a maximum of 140 dB/dec for far-out frequencies.
D. Equalization of the Transfer Function
In many applications, the wanted signal could be accompa-
nied by a strong interferer. Analog-intensive receivers tradi-
tionally use continuous-time (CT) Butterworth or Chebyshev
type of filters with complex conjugate poles to select the wanted
channel out of adjacent channels while filtering out interferers
and blockers. In this way, most of the filtering is done in the CT
.
.
.(8)
2580 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014
Fig. 9. Bode plot frequency response of the CR IIR7 ( pF, 9pF,
0.125 mS, GHz, and 125 MS/s).
analog domain, and a low dynamic range ADC can be used af-
terwards. However, digitally intensive DT receivers distribute
the channel select filtering between the pre-ADC analog filter
and post-ADC digital filter. In [1]–[7], 2nd/3rd/6th-order real-
pole analog filters are used before the ADC, and the rest of the
filtering is done in digital domain with minimum power con-
sumption. Considering a 3 dB BW, the transfer function of real-
pole filters exhibits a gradual and smooth transition region be-
tween the flat pass-band into the sharp roll-off (see Fig. 10(b)).
Therefore, the real-pole filters are used mostly to filter far-out
interferers/blockers, while they have a moderate selectivity be-
tween wanted and adjacent channels.
The proposed DT CR filter could be converted at the system
level to a sharp high selectivity filter (e.g., Butterworth) with
digital assistance in the form of post-emphasis equalizer. The
idea is to “pull in” the 3 dB cutoff frequency transition region of
the analog filter to well within the channel and digitally compen-
sate for the extra droop at the channel edges. The gradual roll-off
region of the analog filter is masked by flattening it out in dig-
ital domain such that only the sharp roll-off remains. Fig. 10(a)
shows the concept. The digital equalizer can be an all-pass IIR
filter with 0 dB gain and a small peaking at a certain frequency,
thus of insignificant incremental area and power penalty, espe-
cially in scaled CMOS. Transfer function of this filter is easily
calculated by dividing the targeted total transfer function by the
transfer function of the analog CR filter. In practice, its transfer
function is merged with the existing digital part of the channel
select filtering, sample-rate decimation, VGA, offset cancella-
tion, I/Q mismatch compensation and demodulation [1], [3], [7].
An example is shown in Fig. 10(b). The equalizer is designed
to map the 7th-order real-pole transfer function of the CR filter
to a 5th-order Butterworth filter. The goal of this mapping is
to flatten the passband of the overall transfer function, while
keeping it unchanged or better for far-out frequencies. To maxi-
mally reduce power consumption, the digital equalizer operates
in this example at a decimated rate of 10 MS/s while the analog
CR filter runs at 800 MS/s. Note that the CR filter also serves as
an effective anti-aliasing filter for the decimation.
The overall transfer function (including the analog filter and
the digital equalizer), has a higher 3-dB bandwidth
than the real-pole analog filter itself .Consequently,
the input signal undergoes some attenuation by the analog filter
inside the overall passband, which is compensated by the small
peaking of the digital equalizer. While the signal experiences an
overall flat transfer function within the passband, the peaking
Fig. 10. (a) Proposed system for digital equalization of the filter transfer func-
tion. (b) An example of equalizing transfer function of a 7th-order real-poles
DT CR filter and comparison with a 5th-order Butterworth. (c) An example im-
plementation of a receiver utilizing a 6th-order charge rotating real-pole filter at
the baseband [6].
increases noise at the transition region frequencies of both the
analog filter and the ADC to some extent. To be able to com-
pare the overall filter with a stand-alone CT analog filter, we
consider that the overall filter transfer function is lumped be-
fore the ADC, but with a gain loss caused by the analog filter.
This loss is equal to the RMS averaged value of transfer func-
tion of the digital equalizer within .
Table I summarizes the analog gain loss for three different
digital equalizers that map the 7th-order real-pole IIR filter
to the 5th- to 7th-order Butterworth filters with a target 3-dB
of 1 MHz. Due to large over-sampling ratio, the
reported gain losses remain almost the same in case
and are scaled proportionally. Depending on the ap-
plication, the order of the analog filter and the mapped transfer
function should be chosen in a way that provides enough
analog stopband attenuation and minimizes gain loss. In case
when the ideal Butterworth filter characteristic is desired for
the proposed real-pole filter, it might be necessary to increase
the ADC dynamic range to compensate for the filter’s droop.
For example, the ADC could require 0.8 to 1.8 extra ENOB,
when the transfer function is mapped to the 5th- to 7th-order
Butterworth, respectively.
TOHIDIAN et al.: ANALYSIS AND DESIGN OF A HIGH-ORDER DISCRETE-TIME PASSIVE IIR LOW-PASS FILTER 2581
TAB L E I
MAPPING OF THE 7TH-ORDER REAL-POLE IIR FILTER TO THE OVERALL
(I.E., ANALOG AND DIGITAL)5TH-TO 7TH-ORDER BUTTERWORTH FILTER OF
1MHZ3DBBANDWIDTH
System functionality of the proposed charge rotating filter
has been verified in a discrete-time superheterodyne receiver
[6], where the identical 6th-order version is employed as the
first baseband channel selection filter. The simplified receiver
structure is shown in Fig. 10(c). Thanks to the low noise char-
acteristic of this filter, the total receiver has achieved a noise
figure of only 3.2 dB, in addition to a good linearity of
7 dBm that is by no means limited by the high linearity of the
baseband filter.
E. Sampling Rate Increase
Sampling rate of the Fig. 7(b) CR filter is one sample per
cycle, with each cycle comprising 8 phases. Therefore, the sam-
pling frequency is . By increasing the sampling rate,
the frequency folding would be pushed higher, thus making it
less of a concern. Also, the filter can achieve a wider bandwidth.
Operation of the CR IIR7 filter as shown in Fig. 7(b) can be
considered as 8 different stages in series. As new data arrives at
, it is sequentially processed at each stage until . Only then
the next data sample arrives. As history capacitors are
holding the data between different stages, we are able to readily
increase the data rate by pipelining.
Suppose that instead of only one , we have now 8 sam-
pling capacitors, each of them connected to one of the “history”
nodes. Then, by going to the next phase, all of them are moving
to the next node in the clockwise direction. At each new phase
of this pipeline structure, a new data comes into ,a
new data is transferred from to ,from to and
so on until , and one sampling capacitor is reset to ground.
Therefore, a new data comes in and a new data comes out at
each phase (instead of each cycle). In this way, functionality of
the filter has not changed while its sampling rate has increased
by8times . Schematic of this full-rate CR IIR7 filter
is shown in Fig. 11. For each sampling capacitor and its rotation
network, a separate switch bank is used.
The pipeline SC structure has the same charge sharing,
transfer function and gain equations as (8)–(11), but with
replacing each 1/8 delay with a unit delay and considering the
new .
In this filter, if there is a mismatch between different ,
it would slightly shift the pole locations. Since these capaci-
tors have typically a large value and are of the same type, they
are very well matched, thus removing the matching concern.
However, if the mismatch exists between the different in
the pipeline structure, it could alias some amount of signal from
harmonics of inside the passband. However, any signal
Fig. 11. Full-rate CR IIR7 filter using pipelining .
around the harmonics is filtered before the aliasing. In practice,
this non-ideal effect is too small to be observed.
F. N o i s e
Output noise of the charge rotating 7th-order DT filter con-
tains two main contributors: noise of the input gm-cell and noise
of the passive switched-capacitor network. In a process similar
to Fig. 4(a), noise of the gm-cell is shaped by the anti-aliasing
filter, sampled and then shaped by the filter transfer function.
Higher order filtering leads to more noise filtering outside the
passband.
Although it is beyond the scope of this paper, it can be shown
through hand calculations, and verified through noise simula-
tions, that the in-band noise of the proposed passive switched-
capacitor circuit is for ,andremains
the same irrespective of the filtering order. Consequently, one
can arbitrarily increase the filtering order without increasing its
output noise, which is a key advantage over the conventional fil-
ters, where each order increase implies more noise (e.g., more
resistors and opamps in an active-RC filter).
G. Robustness to PVT Variations
Active-RC and Gm-C filters are quite sensitive to PVT varia-
tions because of poor matching between different types of ele-
ments (i.e., resistor, capacitor and gm-cell). However, switched-
capacitor filters are quite robust to PVT variations. Transfer
function and BW of SC filters are set by capacitor ratio, which
are normally implemented of thesamedevicetype(e.g.,MOS,
MiM, or MoM capacitor). Active-SC filters are very robust to
PVT, especially when parasitic capacitance cancellation tech-
niques (e.g., correlated double sampling) are used.
In the proposed passive SC filter, the effective is provided
by MoM type of capacitor and also parasitic capacitance of 8
MOS switches connected to it (see Fig. 11). In this design, 8%
to 26% of is the MOS parasitic capacitance, depending on a
value selection code. On the other hand, has also some
switches to select its value. In this design, MOS parasitic capac-
itance connected to ranges from 0.5% to 20%, depending
on the selection code. Being subject to the PVT variation,
MoM part of the effective and track each other very
well. Also, their common percentage part of the remaining MOS
parasitic capacitance matches well (they are of the same type).
2582 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014
Fig. 12. Implementation of the full-rate CR IIR7. The circuit has been implemented differentially while it has been shown single-ended here for simplicity.
The only part that could be affected by PVT variation is the dif-
ference between the MOS parasitic capacitance percentages of
and . Depending on the selected and codes, this
difference is limited to a few percent of the whole capacitance.
In this way, PVT variation effect is reduced, but still somewhat
higher than an active-SC filter.
IV. DESIGN AND IMPLEMENTATION
The proposed high-order charge-rotating DT filter consists of
a gm-cell, switches, capacitors and a clock waveform generator
circuit. Therefore, it is amenable to the digital deep nanoscale
CMOS technology. If we implement this filter in a finer process,
area of the capacitors, switches and the waveform generator re-
duces while preserving or improving the performance according
to Moore’s law of scaling.
A. Design of the 7th-Order Charge Rotating DT Filter
The final design is implemented differentially while, for the
sake of simplicity, it is shown single-ended in Fig. 12. The
designed filter is software-controlled to operate in one of the two
modes: 1) charge-sampling or 2) voltage-sampling. Although in
the charge-sampling mode we have an active gm-cell, the fil-
tering network is fully passive, making the overall filter semi-
passive. In the voltage-sampling mode, the gm-cell is bypassed
and disconnected from the power supply, resulting in a fully
passive filter. Also, is disconnected via “Mode Control”
Fig. 13. Inverter-based pseudo-differential gm-cell.
to prevent loading the input. The removal of lowers the fil-
tering order by one to 6th.1In this mode, the input voltage (in-
stead of the input charge) is directly sampled by capacitors.
The simple inverter-based gm-cell (Fig. 13) makes the
filter amenable to process scaling. In this pseudo-differential
gm-cell, a bias voltage comes from a diode-connected
NMOS and mirrors a bias current into the gm-cell. Also, a
feedback circuit sets the common-mode output voltage to
by adjusting . Coupling capacitors and bias
resistors set a lower limit in frequency response. By using
large and , this limit is pulled down to a few kHz,
which is acceptable for most applications. As the gm-cell, a
simple invertor is used to be amenable to scaling and provide
1The 7th order of the filter in voltage-sampling mode can be kept by replacing
GND with a history capacitor at . However, we did not do this in the current
implementation.
TOHIDIAN et al.: ANALYSIS AND DESIGN OF A HIGH-ORDER DISCRETE-TIME PASSIVE IIR LOW-PASS FILTER 2583
Fig. 14. (a) Waveform generator circuit with (b) its output buffer.
a good linearity. By properly sizing NMOS and PMOS tran-
sistors, their nonlinearities could be canceled out perfectly for
square-law transistors [23]. However, in nanoscale CMOS, a
partial cancellation is carried out. We have used transistors
with a large channel length to make their behavior closer to
the square-law model. Moreover, a low resistance load by the
SC circuit allows a high IIP3.
The differential history capacitors range from
0.25 to 64 pF digitally selectable via 8 bits. For both his-
tory and sampling capacitors, we used MOM capacitors to
have a very good matching. This minimizes variations due to
PVT. Differential value of the sampling capacitors range
from 0.4 to 2.2 pF digitally selectable by 4 bits. Instead of
implementing differentially, we implement each as two
single-ended capacitors. Then we can set the common-mode
voltage of the filter by terminating to instead of
ground. To adjust the filter bandwidth, we keep fixed and
change . In this way, both the gain and linearity of the circuit
do not change. Also, if the sampling frequency is changed,
we change inversely to keep the bandwidth and the gain
constant.
AsshowninFig.12,thefilter’s switches are implemented
with transmission gates. We have chosen equal NMOS and
PMOS sizes to reduce charge injection and cancel out clock
feedthrough by at least an order of magnitude [24], [25], and
at the same time having a lower on-resistance .Tohave
alow ,low- transistors are chosen. These transistors
should be sized carefully to have a low enough for fast
settling on the sampling capacitors.
The waveform generator shown in Fig. 14(a), is a digital logic
block. It consists of eight D-flip-flops (DFFs). At power-on,
the DFFs are set/reset to “10000000”. Then, at each successive
clock cycle, the code is rotated one step. In this way, all the
required phases are generated from a reference clock. Outputs
of the DFFs are fed to buffer cells before driving the switches
(Fig. 14(b)). The buffer is able to drive the switches with sharp
rising and falling edges. The sizes of the NMOS and PMOS
transistors in the buffer are skewed to ensure non-overlapping
between consecutive phases.
Fig. 15. Chip micrograph of the full-rate CR IIR7 implemented in TSMC
65 nm CMOS. Die size is 1.2 1.27 mm.
B. Implementation
The filter has been implemented in TSMC 1P7M 65 nm
CMOS process. It operates at a 1.2 V power supply. The
gm-cell drains 250 A. The waveform generator unit and its
buffers clocked at a reference frequency of 800 MHz con-
sume 1.40 mA. The latter current consumption is proportional
to .Thefilter has been verified to work properly up to
1GS/s.
As shown in Fig. 12, an analog multiplexer is added to allow
monitoring different outputs (orders) of the filter as well as the
internal on-chip input of the filter. After the multiplexer, an
output buffer isolates the chip internals from the outside. Fig. 15
shows a chip micrograph of the implemented filter.
V. M EASUREMENT RESULTS
To verify the proposed filter, a single-ended input signal is
converted to differential with a wideband transformer, termi-
nated with a 50 resistor on the PCB and then fed to the chip.
2584 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014
TAB L E I I
PERFORMANCE SUMMARY AND COMPARISON WITH THE STATE -OF-THE-ART
Differential output of the chip with zero-order-hold is converted
back to a single-ended signal with another transformer. Table II
summarizes the filter performance in its two operational modes,
including the effects of the suggested digital equalizer, and com-
pares with recent state-of-the-art filters.
The transfer function of the filter has been evaluated using an
HP8753E network analyzer. To lower the measurement noise
floor, a wideband RF amplifier (HP8347A) was used. Fig. 16(a)
plots the measured frequency response of the filter in the charge-
sampling mode at the 7th-order output for different bandwidth
settings. The 3 dB bandwidth is programmable from 400 kHz
to 30 MHz. By applying a digital equalizer to map the transfer
function to a 5th-order Butterworth, the overall 3 dB bandwidth
would be tunable from 0.82 to 61 MHz. As an example, the
overall transfer function including the equalizer is plotted with
the black dashed line in Fig. 16(a). A maximum 100 dB of
stop-band rejection is measured for the narrowest bandwidth
setting. Depicted in Fig. 16(b) is the measured transfer func-
tion of the filter in the charge-sampling mode, but now for dif-
ferent outputs (orders). In this measurement, the 400 kHz analog
bandwidth setting is used. The measured 7th-order output is also
compared with the ideal mathematical transfer function shown
by the black dashed line, indicating a very good agreement with
theory. The transfer function of the filter in the voltage-sampling
mode is similar to that shown in Fig. 16 except that the filtering
order is 6th.
To evaluate the linearity of the filter, a two-tone signal is fed
to the filter and its output is evaluated by an Agilent E4446A
spectrum analyzer. For this test, the analog bandwidth is set to
about 9 MHz. Fig. 17 shows the measured 2nd- and 3rd-order in-
termodulation products versus the input power for both charge-
sampling and voltage-sampling modes. Measured IIP2 and IIP3
(with respect to 50 )are 55 dBm and 21 dBm in charge-
sampling mode, and 61 dBm and 24 dBm in voltage-sam-
pling mode. In the charge-sampling mode, where the linearity is
limited by the gm-cell, IIP3 might be lowered by a few dBs in
practice, caused by PVT variations. As listed in Table II, IIP3/
IIP2 in the charge-sampling mode is among the best. Thanks
to the fully passive operation, the filter in the voltage-sampling
mode has an exceptionally high IIP3/IIP2.
To be able to fairly compare the 1 dB compression point
of our filter in its two operational modes to other filters with
TOHIDIAN et al.: ANALYSIS AND DESIGN OF A HIGH-ORDER DISCRETE-TIME PASSIVE IIR LOW-PASS FILTER 2585
Fig. 16. Measured transfer function of the CR IIR7 for (a) the 7th-order output
with different BW settings, and (b) for different orders in 400 kHz BW setting.
The filter is in charge-sampling mode clocked at 800 MHz.
various gains, we compare the output compression point as
. The measured output com-
pression point of the filter in the charge-sampling mode is
10 dBm. In the voltage-sampling mode, this value goes to
13 dBm. These are outstanding values compared to the other
works listed in Table II.
The noise of the filter is evaluated by the spectrum analyzer.
For this measurement, the input of the filter is grounded. A
two-step experiment is carried out: 1) measuring the total output
noise (including noise of the filter and output buffer), 2) dis-
abling the filter and measuring the noise of only the output
buffer. Then, since the noise of the buffer and the filter are un-
correlated, the filter noise is calculated by subtracting the total
noise power spectral density (PSD) and the buffer noise PSD.
Fig. 18(a) shows the measured input-referred noise (IRN)
spectral density of the filter in the charge-sampling mode for
the 9 MHz setting ( 0.75 pF, 2.35 pF).
The slope below 1 MHz is due to the flicker and bias noise
of the gm-cell. Noise between 1 MHz and 20 MHz is mainly
the thermal noise of the gm-cell shaped by the filter transfer
function, and the rest is dominantly noise of the switched-ca-
pacitor circuit. The averaged spot noise over the bandwidth is
4.57 nV/ Hz. Integrated noise, , from 50 kHz to 9 MHz is
13.6 , which increases to 16.4 for the entire fre-
quency range. This gives a 71 dB spurious-free dynamic range
(SFDR) as defined in [26]. As measured by a single-tone test,
Fig. 17. In-band IIP2 and IIP3 measurement of the CR IIR7 filter in (a) charge-
sampling and (b) voltage-sampling modes.
Fig. 18. Measured input-referred noise of the filter in (a) charge-sampling and
(b) voltage-sampling mode.
a3.5 dBm input signal (422 mV peak-to-peak differential)
creates 40 dB 3rd-harmonic distortion (HD3) at the output,
2586 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014
giving an 81 dB dynamic range (1% HD3 DR). By applying
the digital equalizer to map the analog transfer function to a
5th-order Butterworth, the equivalent IRN of the total filter in-
creases to 4.72 nV/ Hz, resulting in 68 dB SFDR for 18 MHz
.
Measured input-referred noise of the filter in the voltage-
sampling mode for the 3.1 MHz (0.75 pF,
8.25 pF) is illustrated in Fig. 18(b). In this mode, the
whole noise spectrum is due to the switched-capacitor network.
The spot IRN averaged over the bandwidth is 4.97 nV/ Hz.
The integrated IRN over the bandwidth is 8.6 and rises
to 22.2 for the entire frequency range. This results in
75 dB SFDR. As measured, a single tone input signal as large
as 8.8 dBm (1.75 V peak-to-peak differential) creates 1% HD3
in this mode. This results in 97 dB dynamic range. By map-
ping the 6th-order real-pole transfer function of this filter to a
4th-orther Butterworth using the equalizer, the overall IRN of
the filter rises to 7.27 nV/ Hz giving 71 dB SFDR for 5.4 MHz
.
Measured clock feedthrough at the output of this filter is less
than 110 dBm at 100 MHz. This very low value
avoids any noise and spur problems caused by the clock signal.
VI. CONCLUSION
In this paper, a high-order discrete-time (DT) charge rotating
(CR) IIR filter structure is proposed and experimentally verified.
The implemented 7th-order charge-sampling/6th-order voltage-
sampling DT filter is elaborated in detail. The order of this filter
is easily extendable to even higher orders. Using a pipelining
techniques, sample rate of the filter is increased up to 1 GS/s.
The CR filter is process-scalable according to Moore’s law and
friendly to digital nanoscale CMOS technology. Transfer func-
tion of this filter is precise and robust to PVT variations. Even
though the CR filter features real poles, modern system appli-
cations, such as wireless receivers, could expend digital post-
processing to equalize the droop at the pass-band edge of the
transfer function. Its state-of-the-art performance includes: very
low power consumption, the lowest input-referred noise, very
wide tuning range and excellent linearity.
ACKNOWLEDGMENT
The authors would like to thank Reza Lotfi,S.Amir-Reza
Ahmadi-Mehr, Masoud Babaie, S. Morteza Alavi, and Wanghua
Wu for helpful discussions.
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TOHIDIAN et al.: ANALYSIS AND DESIGN OF A HIGH-ORDER DISCRETE-TIME PASSIVE IIR LOW-PASS FILTER 2587
Massoud Tohidian (S’08) received the B.S. and
M.S. degrees in electrical engineering (with honors)
from Ferdowsi University of Mashhad and the
University of Tehran, Iran, in 2007 and 2010, re-
spectively. He is currently pursuing the Ph.D. degree
at Delft University of Technology, The Netherlands.
He was a researcher in IMEP-LAHC Laboratory,
Grenoble, France, in 2009–2010. He was a consultant
at M4S/Hisilicon, Leuven, Belgium, in 2013–2014,
designing a 28 nm SAW-less receiver chip for mobile
phones. His research interest includes analog and RF
integrated circuits and systems for wireless communications. He holds seven
patents and patent applications in the field of RF-CMOS design.
Iman Madadi (S’08) received the B.S.E.E. degree
from K. N. Toosi University of Technology, Tehran,
Iran, in 2007, and the M.S.E.E. degree from the Uni-
versity of Tehran, Tehran, Iran, in 2010. He is cur-
rently working toward the Ph.D. at Delft University
of Technology, The Netherlands.
He was a consultant at M4S/Hisilicon, Leuven,
Belgium, in 2013–2014, designing a 28 nm
SAW-less receiver chip for mobile phones. His
research interests include analog and RF IC design
for wireless communications. He holds six patents
and patent applications in the field of RF-CMOS design.
Robert Bogdan Staszewski (F’09) received the
B.S.E.E. (summa cum laude), M.S.E.E., and Ph.D.
degrees from the University of Texas at Dallas, TX,
USA, in 1991, 1992, and 2002, respectively.
From 1991 to 1995 he was with Alcatel Network
Systems in Richardson, TX, USA, working on
SONET cross-connect systems for fiber optics
communications. He joined Texas Instruments,
Dallas, TX, USA, in 1995, where he was elected
Distinguished Member of Technical Staff. Between
1995 and 1999, he was engaged in advanced CMOS
read channel development for hard disk drives. In 1999, he co-started a Digital
RF Processor (DRP™) group within Texas Instruments with a mission to invent
new digitally intensive approaches to traditional RF functions for integrated
radios in deeply-scaled CMOS processes. He was appointed a CTO of the
DRP group between 2007 and 2009. In July 2009 he joined Delft University
of Technology, The Netherlands, where he is a Professor. He has authored
and co-authored one book, three book chapters, 170 journal and conference
publications, and holds 130 issued US patents. His research interests include
nanoscale CMOS architectures and circuits for frequency synthesizers, trans-
mitters, and receivers.
Prof. Staszewski has been a TPC member of ISSCC, RFIC, ESSCIRC, and
RFIT. He is an IEEE Fellow and a recipient of IEEE Circuits and Systems In-
dustrial Pioneer Award.
