No full-text available
To read the full-text of this research,
you can request a copy directly from the authors.
Discrete and switching functions. With a foreword by Raymond T. Yeh
... Symmetric Boolean functions are a relatively large class of Boolean functions (there are 2 n+1 out of the total of 2 2 n functions) which are very important in engineering practice, since many computing, control, and communications circuits are described by symmetric functions [1]. In general, symmetric functions can be compactly represented irrespectively to the data structure selected, as for instance , different functional expressions, cubes, decision diagrams, etc. ...
... Proof of (1) =⇒ F 11 represents the complement of the truth vector F 11 , i.e., it is the vector containing all elements of F 11 respectively complemented. Formally, F 11 = F 11 ⊕ [1], where [1] ...
... Proof of (1) =⇒ F 11 represents the complement of the truth vector F 11 , i.e., it is the vector containing all elements of F 11 respectively complemented. Formally, F 11 = F 11 ⊕ [1], where [1] ...
Different forms of symmetry based on cofactors of Boolean functions are characterized in the Reed Muller spectral domain. Furthermore it is shown, that if the arguments of the function are reordered, the permutation that is needed on the truth vector applies also on the spectrum of the function.
... Logical functions and especially the two-valued ones have important roles in our everyday life, so it is easy to understand that they are widely investigated. A scope of the investigations is the representations of these functions and the transforms from one representation to another ([3] [4] [5] [7]). Another area of the examinations is the search of special classes of the set of the functions. ...
... (8) A (n) = (1) if n = 0 A (n−1) 0 (n−1) A (n−1) A (n−1) if n ∈ N (see for instance in [4] ...
In this article we apply the notion of the modified conjunctive normal form of a Boolean function which is equal to the canonical conjunc- tive normal form of the complement of the dual of the same Boolean func- tion. In the article a linear algebraic transform is given between the mod- ified conjunctive normal form and the Zhegalkin polynomial of a Boolean function and then the notion of the conjunctively polynomial-like Boolean functions as the functions having the same series of the coecients in their modified conjunctive normal forms and in their Zhegalkin polynomials is introduced. In this article disjunction and logical sum, conjunction and logical product, exclusive or and modulo two sum, as well as complementation and negation are used in the same sense and they are denoted respectively by +, · (or simply without any operation sign), ' and . The elements of the field with two elements and the elements of the Boolean algebra with two elements are denoted by the same signs, namely by 0 and 1; N0 denotes the non-negative integers, and N the positive ones.
... This normal form is widely called Reed-Muller expansion [4], [3]. The basic decomposition of this normal form, however, was given by Davio [2]. Using Table 1: Boolean Operations a b a b a ∧ b a ∨ b a ⊙ b a ⊕ b ...
... This normal form is widely called Reed-Muller expansion [4], [3]. The basic decomposition of this normal form, however, was given by Davio [2]. Using the positive and the negative Davio decomposition, two fixed polarity and 2 k − 2 mixed polarity Reed-Muller normal forms can be specified. ...
Normal forms of Boolean functions allow to check whether two given Boolean expressions describe the same Boolean function. The disjunctive normal form (DNF) as well as the conjunctive normal form (CNF) are widely used. Sometimes an algebraic normal form is taken into account in order to compare or to evaluate given Boolean functions. The basic property of each normal form is the unique representation of the given Boolean function. The aim of this paper is to study whether there are other normal forms of Boolean functions which allow a more detailed exploration of properties of Boolean Functions. In order to do this we extend the theory of Boolean normal forms in several directions.
... However, the same term was frequently used to denote polynomial expansions of Boolean functions based on Walsh transform known also under the name of orthogonal Walsh series expansion [10, 11] or abstract Fourier transform expansion [7]. As there is a direct relation between polynomial expansions of Boolean functions based on Reed–Muller, Arithmetic, Haar and Walsh functions [5, 7,12131415, it is quite understandable to use this term for Arithmetic expansions as well. To differentiate between Arithmetic and Reed–Muller transforms and expansions, the Russian authors use the names " polynomial Arithmetical " and " polynomial logical " transforms and expansions for the former and latter, accordingly. ...
... Various classes and relations between introduced eight classes of LITA transforms are also discussed. Similarly to known polynomial expansions based on binary and multiple-valued logic [7, 10, 13, 23, 24, 31, 34, 41, 44, 47, 49, 50], the new expansions can have applications in spectral representations of ternary logic functions as well as calculation of their stochastic behavior. They can also be the bases of new ternary word decision diagrams in a manner similar to the ones developed in [30]. ...
New classes of Linearly Independent Ternary Arithmetic (LITA) transforms being the bases of ternary arithmetic polynomial expansions are introduced here. Recursive equations defining the LITA transforms and the corresponding butterfly diagrams are shown. Various properties and relations between introduced classes of new transforms are discussed. Computational costs to calculate LITA transforms and applications of corresponding polynomial expansions in logic design are also discussed.
... The name hazard-free has different meanings in the literature. Our definition is taken from [DDT78]. In Figure 1b we see a hazardfree circuit for the multiplexer function. ...
The problem of constructing hazard-free Boolean circuits dates back to the 1940s and is an important problem in circuit design. Our main lower-bound result unconditionally shows the existence of functions whose circuit complexity is polynomially bounded while every hazard-free implementation is provably of exponential size. Previous lower bounds on the hazard-free complexity were only valid for depth 2 circuits. The same proof method yields that every subcubic implementation of Boolean matrix multiplication must have hazards. These results follow from a crucial structural insight: Hazard-free complexity is a natural generalization of monotone complexity to all (not necessarily monotone) Boolean functions. Thus, we can apply known monotone complexity lower bounds to find lower bounds on the hazard-free complexity. We also lift these methods from the monotone setting to prove exponential hazard-free complexity lower bounds for non-monotone functions.
As our main upper-bound result we show how to efficiently convert a Boolean circuit into a bounded-bit hazard-free circuit with only a polynomially large blow-up in the number of gates. Previously, the best known method yielded exponentially large circuits in the worst case, so our algorithm gives an exponential improvement.
As a side result we establish the NP-completeness of several hazard detection problems.
... The name hazard-free has different meanings in the literature. Our definition is taken from [DDT78]. In Figure 1b we see a hazard-free circuit for the multiplexer function. ...
The problem of constructing hazard-free Boolean circuits dates back to the 1940s and is an important problem in circuit design. Our main lower-bound result unconditionally shows the existence of functions whose circuit complexity is polynomially bounded while every hazard-free implementation is provably of exponential size. Previous lower bounds on the hazard-free complexity were only valid for depth 2 circuits. The same proof method yields that every subcubic implementation of Boolean matrix multiplication must have hazards.
These results follow from a crucial structural insight: Hazard-free complexity is a natural generalization of monotone complexity to all (not necessarily monotone) Boolean functions. Thus, we can apply known monotone complexity lower bounds to find lower bounds on the hazard-free complexity. We also lift these methods from the monotone setting to prove exponential hazard-free complexity lower bounds for non-monotone functions.
As our main upper-bound result, we show how to efficiently convert a Boolean circuit into a bounded-bit hazard-free circuit with only a polynomially large blow-up in the number of gates. Previously, the best known method yielded exponentially large circuits in the worst case, so our algorithm gives an exponential improvement.
As a side result, we establish the NP-completeness of several hazard detection problems.
... A BDD is a graphical form of a Boolean function [1] that is efficiency for the representation and analysis of a Boolean function of large dimension. The second tool is the Logical Differential Calculus [2, 10, 33]. Mathematical methods of Logical Differential Calculus permit to investigate the influence of a variable value change to the Boolean function value. ...
System availability evaluation includes different aspects of system behaviour and one of them is the importance analysis. This analysis supposes the estimation of system component influence to system availability. There are different mathematical approaches to the development of this analysis. The structure function based approach is one of them. In this case system is presented in form of structure function that is defined the correlation of system availability and its components states. Structure function enables one to represent mathematically a system of any complexity. But computational complexity of structure function based methods is time consuming for large-scale system. Decision of this problem for the calculation of importance measures can be realized based on application of two mathematical approaches. One of them is Direct Partial Boolean Derivative. New equations for calculating the importance measures are obtained in terms of these derivatives. Other approach is Binary Decision Diagram (BDD), which supports efficient manipulation of Boolean algebra. In this paper new algorithms for calculating of importance measures by Direct Partial Boolean Derivative based on BDD are proposed. The experimental results of comparison these algorithms with other show the efficiency of new algorithms for calculating Direct Partial Boolean Derivative and importance measures. © 2015 Polish Academy of Sciences Branch Lublin. All rights reserved.
... FPRM expression are a subset of MPRM expressions. MPRM expressions are unique [2] . Thus, only one representation exists for the PPRM or NPRM or indeed any MPRM of f (x 1 , x 2 , ..., x n ). ...
In this paper, we use the transeunt triangle in an e-cient algorithm to flnd the mini- mum mixed polarity Reed-Muller expression of a given function. This algorithm runs in O(n3) time and uses O(n3) storage space. We demonstrate this algorithm on benchmark functions, and we extend it to multi-output functions.
... [8,[12][13][14][15][16][17][18][19][20][27][28][29][30]37,38,48,57], it is convenient to represent the discrete Haar functions in terms of switching variables as is shown in the following example. Example 2. For n ¼ 3, the relationships between discrete Haar functions and switching variables ordered in the descending value of indices can be expressed as follows: In this case, we can consider the fixed-polarity Haar expressions, in the same way as the fixedpolarity Reed-Muller [11], arithmetic [18,21], and Walsh [12] expressions have been considered. Example 3. ...
This paper is a brief survey of basic definitions of the Haar wavelet transform. Different generalizations of this transform are also presented. Sign version of the transform is shown. Efficient symbolic calculation of Haar spectrum is discussed. Some applications of Haar wavelet transform are also mentioned.
... The matrix notation for the Boolean difference with respect to a variable x i of the Boolean function f given by the truthvector F = [f (0) f (1) . Fundamentals of the Boolean differential calculus have been developed in [5], [8], [22]. In a number of publications, the usefulness of differential models has been shown [9], [13], [14], [17]. ...
The paper revisits the well-known spectral trans- forms of a Boolean function, emphasizing on the fact that Reed- Muller, arithmetic and Walsh spectra can be calculated through boolean difference, and arithmetical and Walsh analogs of it. This techniques is called Taylor technique, by analogy with Taylor series which coefficients are differences, or differentials. The algorithms are perfectly implementable on parallel-pipelining processors in VLSI technology. This paper argues that Taylor based algorithms can also be implemented on nanoscale circuits.
... This normal form is widely called Reed-Muller expansion [4], [5]. The basic decomposition of this normal form, however, was given by Davio [2] . Using orthogonality and Boolean Differential Calculus [15], an extended theory of Boolean normal forms [17] was developed. ...
Traditionally Sum-Of-Products (SOPs) have been studied as expressions of Boolean functions. It has been shown by Sasao in [7] that Exclusive-or-Sum-Of-Products (ESOPs) are more compact representations of Boolean functions than SOPs. The problem to identify an exact minimal ESOP of a Boolean function is despite of some partial results still unsolved. Our new results rely on recently detected properties of Boolean functions and extend the set of Boolean functions for which an exact minimal ESOP can be constructed.
... There are some interesting and useful results. For instance, when the number of inputs of a switching circuit is small, the Quine-McCluskey procedure is widely used for designing two-stage network[13]. When a large number of inputs is involved, decomposition chart method to multi-level minimization was proposed by Ashenhurstis [1], and was later further discussed and developed by Curtis [12] and Roth and Karp [20]. ...
The decomposition of logical mappings, including disjoint and non-disjoint cases, is con-sidered. First, we consider the Boolean functions, then the results are extended to multi-valued logical functions and further to mix-valued logical mappings, which contain multi-input and multi-output map-ping as its particular case. Using semi-tensor product, straightforward verifiable necessary and sufficient conditions are provided for each case. The constructive prodf provide algorithms for constructing the decompositions. Finally, the general result is applied to convert a dynamic-static Boolean network into its normal form. Examples for each cases are provided to illustrate the corresponding results.
... By using a subset of spectral coefficients, each value may be calculated quickly and the overall number of computations is no longer exponential. It has been shown that all 2 n spectral coefficients are required to uniquely represent a Boolean function when the Walsh family of transformation matrices are employed [Karpovsky 1976; Davio et al. 1978]. Thus, a method that uses a subset of coefficients must necessarily employ heuristics , since an exact solution cannot be obtained. ...
A prototype system developed to convert a behavioral representation of a Boolean function in OBDD form into an initial structural representation is described and experimental results are given. The system produces a multilevel circuit using heuristic rules based on properties of a subset of spectral coefficients. Since the behavioral description is in OBDD form, efficient methods are used to quickly compute the small subset of spectral coefficients needed for the application of the heuristics. The heuristics guide subsequent decompositions of the OBDD, resulting in an iterative construction of the structural form. At each stage of the translation, the form of the decomposition is chosen in order to achieve optimization goals.
... Decomposition is a major method that is used for the synthesis of logic circuits [1, 2, 3, 4, 5, 6] . Various decomposition techniques have been developed to synthesize logic functions. ...
This part is a continuation of the first and second parts of my paper. In a previous work, symmetry indices have been related to regular logic circuits for the realization of logic functions. In this paper, a more general treatment that produces 3D regular lattice circuits using operations on symmetry indices is presented. A new decomposition called the Iterative Symmetry Indices Decomposition (ISID) is imple-mented for the 3D design of lattice circuits. The synthesis of regular two-dimensional circuits using ISID has been introduced previously, and the synthesis of area-specific circuits using ISID has been demonstrated. The new multiple-valued ISID algorithm can have several applications such as: (1) multi-stage decompositions of multiple-valued logic functions for various lattice circuit layout optimizations, and (2) the new method is useful for the synthesis of ternary functions using three-dimensional regular lattice circuits whenever volume-specific layout constraints have to be satisfied.
The common gate library for the synthesis of reversible circuits consists of mixed-polarity multiple-control Toffoli gates or single target gates. Such gates offer a convenient representation to model the functionality of a reversible circuit but are not universal for quantum operations. Many aspects, particularly those considering fault tolerance and error correction properties, cannot be considered effectively at this abstraction level. Consequently, after deriving and optimizing a reversible circuit for a given function as it is explained in the previous chapter, the next step consists of mapping the circuit into a quantum circuit. For this purpose, the following steps are usually applied: (1) Performing circuit transformation such that the circuit consists only of NCT gates. (2) Mapping each 2-control Toffoli gate to an optimum quantum circuit composed of gates from a given library. Many algorithms have been proposed to accomplish the first step, i.e., to map an MPMCT circuit to an NCT circuit. In the following section we review the different mapping strategies for MPMCT or ST based circuits. Then, in Sect. 4.2 we introduce an enhanced mapping approach for the ST based circuits. Later, in Sect. 4.3 we propose an efficient mapping methodology targeting the Clifford + T library based circuits in order to minimize their T-depth. Finally, we study the complexity of mapped circuits, i.e., reversible circuits based on the NCT gate library in Sect. 4.4.
In this chapter, we aim at reducing the quantum cost and studying the complexity analysis of circuits in the reversible level. This chapter is structured as follows. Section 3.1 reviews the related work. Then, in Sects. 3.2 and3.3, we give two approaches for the optimization of reversible circuits regarding the quantum cost metric. Section 3.4 describes a study for complexity analysis of reversible circuits and the chapter is concluded in Sect. 3.5.
After mapping a reversible circuit into a functionally equivalent quantum circuit, the resulting circuit is not optimal with respect to considered cost metrics due to the existing non-optimal synthesis as well as mapping approaches, particularly for large circuits. Moreover, physical developments for emerging technologies constantly lead to new constraints, e.g., the depth and the NNC. For that reason, post-mapping optimizations are applied to optimize the value of the cost metrics with respect to the used library. In particular, many existing optimization methods target the reduction of the quantum cost and the depth [83, 128] of quantum circuits. In the following section, related work is summarized. Afterwards, a depth optimization approach is given in Sect. 5.2. Then, in Sect. 5.3 an algorithm for reducing the quantum cost is explained. Finally a study of the complexity of quantum implementations is given in Sect. 5.4.
To keep the book self-contained, this chapter briefly introduces the basics on reversible logic, quantum circuits, and other required concepts. The chapter consists of seven parts: the first section introduces the basic definitions and notations of Boolean functions while the second section reviews existing Boolean decomposition. The third and the fourth sections give an overview of exclusive sum of products and Boolean satisfiability, respectively. The fifth section provides a summary on the principles of reversible logic required later in this book. Similarly, the sixth section gives an introduction on quantum computation and quantum circuits. The later section details the different metrics used as a quality-measure of reversible and quantum realizations. Finally, decision diagrams are reviewed.
The bi-decomposition is a very powerful method to find an optimal multiple-level circuit structure that realizes a logic function. So far, the required simplification of the decomposition functions was realized in the strong bi-decomposition by reducing the number of variables. The completeness of this decomposition method was reached by the weak bi-decomposition. The drawback of the weak bi-decomposition is that different path lengths occur because the number of variables is only decreased for one of the two decomposition functions. In this paper, the method of bi-decomposition is extended by the vectorial bi-decomposition which utilized for the first time simpler decomposition functions which depend on all variables as the given function. It will be shown that vectorial bi-decompositions exist for functions for which no strong bi-decomposition is possible. Using the vectorial bi-decomposition together with the strong bi-decomposition, circuit structures can be found which have short delays and a unique path length.
The Boolean Differential Calculus is a valuable supplement of the Boolean Algebra and the switching theory. This calculus is based upon the Boolean Algebra and explores the changing behavior of Boolean functions. The definitions of derivative and differential operations of the Boolean Differential Calculus extends the aspects of the problems to solve. Important new solutions, not only in circuit design, could be found in this way by utilizing the Boolean Differential Calculus. This paper gives a compact introduction into the Boolean Differential Calculus for both single Boolean functions and lattices of them. Definitions, interpretations, and theorems provide the basic knowledge. Together with the given selected applications, this paper should motivate the reader to apply the Boolean Differential Calculus to solve further tasks. Index Terms—Boolean Differential Calculus, derivative operations , differential of a Boolean variable, differential operations, lattice of Boolean functions, applications.
System availability evaluation, sensitivity analysis, importance measures, and optimal design are important issues that have become research topics for reliability engineering. There are different mathematical approaches to the development of these topics. The structure function based approach is one of them. Structure function enables one to analyse a system of any complexity. But computational complexity of structure function based methods is time consuming for large-scale networks. We propose to use two mathematical approaches for decision to this problem for system importance analysis. The first of them is Direct Partial Boolean Derivative. New equations for calculating the importance measures are developed in terms of these derivatives. The second is Binary Decision Diagram (BDD), that supports efficient manipulation of Boolean algebra. Two algorithms for calculating Direct Partial Boolean Derivative based on BDD of structure function are proposed in this paper. The experimental results show the efficiency of new algorithms for calculating Direct Partial Boolean Derivative and importance measures.
There is recently an increased interest in logic synthesis using EXOR gates. The paper introduces the fundamental concept of OrthogonaI Ezpansion, which generalizes the ring form of the Shannon expansion to the logic with multiple-valued (mv) inputs. Based on this concept we are able to define a family of canonical tree circuits. Such circuits can be considered for binary and multiple-valued input cases. They can he multi-level (trees and DAGs) or flattened to two-level AND-EXOR circuits. Input decoders similar to those used in Sum of Products (SOP) PLAs are used in realizations of multiple-valued input functions. In the case of the binary logic the family of flattened AND-EXOR circuits includes several forms discussed by Davio and Green. For the case of the logic with multiple-valued inputs, the family of the flattened my AND-EXOR circuits includes three expansions known from literature and two new expansions.
We present Ordered Kronecker Functional Decision Diagrams (OKFDDs), a graph-based data structure for the representation and manipulation of Boolean functions. OKFDDs are a generalization of Ordered Binary Decision Diagrams and Ordered Functional Decision Diagrams and as such provide a more compact representation of the functions than either of the two decision diagrams. We review basic properties of OKFDDs and study methods for their efficient representation and manipulation. These algorithms are integrated in our OKFDD package PUMA whose implementation is briefly discussed. Finally we point out some applications of OKFDDs, demonstrate the efficiency of our approach by some experiments and discuss a promising extension of the concept to also allow representation and manipulation of word-level functions.
This paper is devoted to a study of differential calculus for generalised pseudo-Boolean functions with finite domain and antidomain P with a ring structure which may be infinite. A completely new definition is given of partial derivatives of generalised pseudo-Boolean functions . Further are given some properties of these partial derivatives and a new Taylor expansion.M. Davio, J.P. Deschamps, A. Thayse, Belgian mathematicians, have studied the differential calculus for discrete functions with finite domain and antidomain which is a totally ordered lattice 0<1<⋯<m−1 with a structure of a ring of integers modulo m. If P is finite, then generalised pseudo-Boolean functions are discrete functions, but the partial derivatives of generalised pseudo-Boolean functions are different from the partial derivatives of discrete functions which were studied by the Belgian mathematicians.
The cellular grain architectures of new Field Programmable Gate Arrays (FPGAs) require s p e-cial logic synthesis tools. Therefore, this paper ad-dresses multilevel logic synthesis methods based o n o r -thogonal expansions for such kind of architectures. First, the concepts of the Binary Decision Diagrams (BDDs), their derivatives, and the Functional De-cision Diagrams (FDDs), which are applied t o t h e technology mapping to Field Programmable Gate Ar-rays (FPGAs), are generalized h e r e to the Kronecker Functional Decision Diagram (KFDD) with negated edges. Three other new types of functional decision diagrams are also introduced: If-Then-Else KFDDs, Mixed KFDDs, and Permuted KFDDs. The intro-duced KFDD is based o n t h r ee orthogonal (Davio) expansions and is created h e r e also for multi-output incompletely speciied B o olean functions. Next, the KFDD creating algorithm being a basis of heuristic mapping program to ATMEL 6000 cellular FPGAs is also presented. Besides this application, our algorithm was adopted f o r t e chnology mapping to Multiplexer-Based (MB) and Table-Look-Up (TLU) based a r chi-tectures.
The field of binary Logics has two main areas of application, the Digital Design of Circuits (related to Electrical Engineering) and Propositional Logics (related to Mathematics, Artificial Intelligence, Complexity etc.). In both cases it is quite possible to teach the theoretical foundations and to do some exercises, but in both cases the examples that can be done in class and by hand are far away from examples that are relevant for practical problems. Therefore a software package called XBOOLE Monitor will be made available (downloadable, without additional fees), and the exercises given in Logic Functions and Equations can be solved by using this software package - in this way it is possible to solve a lot of relevant problems and to study the solutions based on this software. The whole approach is based on the single and unique concept of Boolean Equations and Ternary Vectors as the basic data structure which makes it also easy to follow these ideas very easily, because the wide range of problems and solutions will be based on these two concepts.
Boolean differential equation is a logic equation containing Boolean differences of Boolean functions. We formulate the solution in terms of matrix notations and consider two methods. The focus of the first method is that the initial Boolean differential equation is represented by a system of logic equations in Reed–Muller canonical form, then it is solved by discrete orthogonal transform. The computational complexity of the first method (22n+3n in terms of logic operations) is reduced to sorting of 2n elements and combinatorics forming of 22n−1 solutions, where n is the number of variables in the equation.
The bi-decomposition of multi-valued logical (MVL) functions, including disjoint and non-disjoint cases, is considered. Using a semi-tensor product, an MVL function can be expressed in its algebraic form. Based on this form, straightforward verifiable necessary and sufficient conditions are provided for each case, respectively. The constructive proofs also lead to constructing corresponding decompositions. Using these results, the implicit function theorem (IFT) of kk-valued functions, as a special bi-decomposition, is obtained. Finally, as an application, the normalization of dynamic–algebraic (D–A) Boolean networks is investigated using IFT of kk-valued functions.
The problem of solving (arbitrary) equations over arbitrary (finite) sets has been studied in the literature [1–3, 5, 7, 9, 10, 15, 17, 19]. After determining one general solution in [15]. Presšić determined in [17] all general reproductive solutions of a finite equation, supposing that particular solutions are known. In this paper we determine all general solutions (including all general reproductive solutions) of a finite equation without the above supposition. We also describe all general solutions of Boolean equations in Boolean algebra B2.
Considers the realization of switching functions by programs composed of certain conditional transfers (binary programs). Methods exist for optimizing binary trees, i.e. binary programs without reconvergent instructions. This paper studies methods for optimizing binary simple programs (programs with possible reconvergent instructions, but where a variable may be tested only once during a computation) and binary programs. The hardware implementations of these programs involve either multiplexers or demultiplexers and OR-gates.
In this paper we report recent results concerning local versions of monotonicity for Boolean and pseudo-Boolean functions: say that a pseudo-Boolean (Boolean) function is p-locally monotone if each of its partial derivatives keeps the same sign on tuples which differ on less than p positions. As it turns out, this parameterized notion provides a hierarchy of monotonic ties for pseudo-Boolean (Boolean) functions. Local monotonic ties are tightly related to lattice counterparts of classical partial derivatives via the notion of permutable derivatives. More precisely, p-locally monotone functions have p-permutable lattice derivatives and, in the case of symmetric functions, these two notions coincide. We provide further results relating these two notions, and present a classification of p-locally monotone functions, as well as of functions having p-permutable derivatives, in terms of certain forbidden "sections", i.e., functions which can be obtained by substituting variables for constants. This description is made explicit in the special case when p=2.
A new method for the efficient evaluation of the arithmetic and Reed-Muller spectra of the logic product, logic sum, EXOR sum and negation of Boolean functions is proposed in this article. The proposed method shows the advantages in calculation of composite arithmetic and Reed-Muller spectra for Boolean functions over conventional method both in computation and time complexities
The known methods for solving Boolean equations are procedures which give the formulas of general (reproductive) solutions of a given Boolean equation using a certain number of steps. In this paper we immediately give the formulas of the general reproductive solutions of a given Boolean equation.
Theorems relating the most important concepts of switching theory to a new kind of difference operator are stated. This difference operator is then used as a unifying concept to solve, by means of a new type of algorithm, several problems arising in logical design.
This paper develops a method based on the Euclide's algorithm for expanding a discrete function in terms of the successive powers of a given integer. We obtain as a particular case of this algorithm a new method for obtaining the binary expansion of a pseudo-Boolean function.
Different forms of symmetry based on cofactors of Boolean functions are characterized in the Reed Muller spectral domain. Furthermore it is shown, that if the arguments of the function are reordered, the permutation that is needed on the truth vector applies also on the spectrum of the function.
An AND‐EXOR expression (exclusive‐or sum‐of‐products expression: ESOP) is obtained by EXORing arbitrary product terms. First, some properties are shown of minimum ESOPs which are useful for the minimization of ESOPs. Second, a catalog of minimum ESOPs for the representative functions of 4‐variable NP‐equivalence classes is presented. Minimality is defined as first minimizing the number of the product terms and then the number of the literals in the ESOP. Minimum ESOPs are obtained by an exhaustive method. The average number of products to realize the 4‐variable functions by AND‐OR sum‐of‐products expressions is 4.13 and 3.66 by ESOPs.
Minimum ESOPs with four variables or less are obtained easily by the table look‐up of the catalog. The catalog is useful for the minimization and the complexity analysis of ESOPs with five or more variables.
For m-variables logic functions, an orthonormal system of order n is defined as an n-tuple of m-vari-ables logic functions where one and only one of the m-variables logic function equals 1. Any given logic function can be expressed as a sum of products between these n-tuple of functions and appropriate coefficients for these functions. This form is known as an orthonormal expansion. This paper deals with the fact that the orthonormal system of order n divides the input space into n disjoint subspaces. We show that this property, along with appropriate restrictions on the expansions, enables us to design four level circuits where all of the single stuck-at faults are testable. Since the circuits based on the expansions include partial circuits for the orthonormal systems, these can be activated one by one. This is the key property that guarantees the testability of s-a-0 faults. On the other hand, when a test for a s-a-1 fault should make an element of the orthonormal system equal to 0, this input can make one and only one of the other elements equal to 1. This is key to guaranteeing the testability of s-a-1 faults. Expansions are carried out with appropriate restrictions considering these properties. Where there exists a coefficient that is covered by all of the other coefficients, a corresponding element is eliminated. This elimination, which can be regarded as a generalized absorption law for Boolean functions, guarantees the existence of the solution for any given set of logic functions. The number of tests for the circuit is proportional to the number of prime implicants in the expansions. These tests are generated as a byproduct during the expansions.
To perform a mixed mode analysis with the electrical and gate levels in the waveform relaxation context, an initial steady state of the analysed circuit must be computed prior to transient analysis. By using Boolean algebra and discrete relaxation, we propose various algorithms to compute a stable state or a stable total state of a logic synchronous sequential system with master-slave flip-flops. Furthermore, a dynamic ordering of the logic gates which improves the convergence of the computation of a stable total state is presented. We show that a stable state can be calculated within only two iterations.
This paper presents a new methodology for the computation of the Reed-Muller spectral co-eecients of a function of any xed polarity using its OBDD representation. By using past results that al-low the computations to be performed using real arith-metic, an eecient technique may be developed in the real domain with the resulting coeecients obtained by using a simple mapping relation to the GF(2) domain. These results mathematically justify the OBDD based approach developed in this work. This result is novel since it relies on the use of OBDDs and the concept of a Boolean function output probability to compute the coeecients. This approach is also very general in that it allows other types of coeecients (such as the Walsh) to be computed as well as the Reed-Muller forms with a single OBDD operation. A small exam-ple of this technique is given to illustrate the approach followed by some experimental results.
This paper addresses the interconnect problem for the representation of logic networks in spatial dimensions. Interest in spatial interconnects is motivated by the advent of nanotechnologies and by consequent attempts to evaluate and explore the appropriate nanoscale architectures. It have been shown in our previous study that a 3D logic network with target topology can be designed by replacing each elementary logic block in a network by its 3D model. In this paper, we study the problem of the partitioning of these 3D blocks with respect to the constraints of logic function interconnects and hypercube-like topology. We found that decomposition techniques provide flexibility in choosing switching functions for assembling the decomposed sub-networks.
Antes do final do primeiro semestre de 1995, estarão disponíveis para comercialização no mercado mundial amostras de pelo menos quatro microprocessadores de 64 bits. Estes circuitos integrados (CIs) possuem entre 3,8 e 9,3 milhões de transistores. Além disto, trabalham com uma freqüência de relógio máxima entre 133 e 300 MHz e executam instruções a uma taxa máxima que varia de 532 a 1200MIPS (Milhões de Instruções Por Segundo) [GEP 95]. Tais dados são impressionantes, especialmente se atentarmos para o fato de que a tecnologia de integração de circuitos surgiu em meados da década de 60, e que os primeiros microprocessadores não continham mais do que algumas centenas de transistores. Eles trabalhavam com freqüência de relógio não superior a 1MHz, alcançavam uma taxa máxima de execução de instruções que era uma fração de MIPS e somente estavam disponíveis no mercado a partir de 1974 [DeM 94]. Figuras de mérito similares são encontradas ao estudarmos a evolução do estado da arte em CIs de memória e em CIs específicos para uma dada aplicação, no mesmo período de tempo. A mera existência dos microprocessadores de 64 bits nos coloca diante da questão de como é possível viabilizar a construção de sistemas digitais de tal porte. A dúvida é a mesma, caso imaginemos o sistema digital distribuído em um conjunto de componentes dispostos sobre uma ou mais placas de circuito impresso. Mesmo se abstrairmos do fato de se tratar de um sistema eletrônico e pensarmos em construir um sistema cuja complexidade exija a interconexão de cerca de dez milhões de componentes, a tarefa se revela díficil de ser apreendida globalmente. A resposta à questão não é nem simples, nem única. Visando entender o problema, podemos inicialmente particionar o conjunto de tarefas necessárias para a construção de um sistema digital complexo em dois blocos. Em um dos blocos agrupamos todas as tarefas que envolvem manipulação direta de elementos do mundo físico, tais como a difusão de impurezas em regiões de um substrato semicondutor para a criação de transistores, ou a solda de pinos de CIs em determinadas posições de uma placa de circuito impresso. Denominamos este bloco de tarefas de processo de fabricação 1 . No segundo bloco, agrupamos todas as tarefas de manipulação de modelos abstratos capazes de representar o sistema que queremos implementar, tais como a simulação de um diagrama de interconexão de portas lógicas, ou a minimização de equações Booleanas que representem a funcionalidade de um módulo do sistema. Chamamos este bloco de processo de projeto.
We start from the geometrical-logical extension of Aristotle’s square in [6,15] and [14], and study them from both syntactic and semantic points of view. Recall that Aristotle’s square under its modal form has the following four vertices: A is □α, E is \(\square\neg\alpha\), I is \(\neg\square\neg\alpha\) and O is \(\square\neg\alpha\), where α is a logical formula and □ is a modality which can be defined axiomatically within a particular logic known as S5 (classical or intuitionistic, depending on whether \(\neg\) is involutive or not) modal logic.
[3] has proposed extensions which can be interpreted respectively within paraconsistent and paracomplete logical frameworks. [15] has shown that these extensions are subfigures of a tetraicosahedron whose vertices are actually obtained by closure of \(\{\alpha,\square\alpha\}\) by the logical operations \(\{\neg,\wedge,\vee\}\), under the assumption of classical S5 modal logic. We pursue these researches on the geometrical-logical extensions of Aristotle’s square: first we list all modal squares of opposition. We show that if the vertices of that geometrical figure are logical formulae and if the sub-alternation edges are interpreted as logical implication relations, then the underlying logic is none other than classical logic. Then we consider a higher-order extension introduced by [14], and we show that the same tetraicosahedron plays a key role when additional modal operators are introduced. Finally we discuss the relation between the logic underlying these extensions and the resulting geometrical-logical figures.
This paper describes how succinct rules, which reduce the size of decision tables, can be found by employing multiple-valued logic (MVL). Two multiple-valued algebras are described, one based on level detection, and the other on literal functions. Then a decision table which had also been reduced in size using rough set theory, is now reduced using both algebras and it is seen that all three approaches lead to reductions of comparable simplicity. The new methods require coding the values of each attribute as integers. Then an MVL function that maps the coding of the condition attributes to the coding of the decision attribute is found. As the coded table is sparse only some of the basis functions for each algebra are required. Then a simple approach requiring the reduction of a matrix to row echelon form is used to finding all suitable MVL functions. By decomposing a function in terms of its variables a complete set of rules can be found. The MVL function encodes the data in a very compact form and its decomposition into subfunctions reveals a good way to slice up the table into subtables. The structure of the subfunctions can then be used to simplify each subtable until compact sets of rules emerge. Alternatively, rules can be found by substitution into the MVL function. Encoding a decision table using MVL makes the data easy to manipulate and can uncover relationships that may not become apparent when using other methods.
Theoretical results due to V. Malyugin on linearization of arithmetical models of logical functions are interpreted and refined from the viewpoint of modern techniques of logical design of integral circuits and nearest neighbor technologies.
In this paper, we investigate the following problem: give a quasi-Boolean function Ψ(x
1, …, x
n
) = (a ∧ C) ∨ (a
1 ∧ C
1) ∨ … ∨ (a
p
∧ C
p
), the term (a ∧ C) can be deleted from Ψ(x
1, …, x
n
)? i.e., (a ∧ C) ∨ (a
1 ∧ C
1) ∨ … ∨ (a
p
∧ C
p
) = (a
1 ∧ C
1) ∨ … ∨ (a
p
∧ C
p
)? When a = 1: we divide our discussion into two cases. (1) ℑ1(Ψ,C) = ø, C can not be deleted; ℑ1(Ψ,C) ≠ ø, if S
i
0 ≠ ø (1 ≤ i ≤ q), then C can not be deleted, otherwise C can be deleted. When a = m: we prove the following results: (m∧C)∨(a
1∧C
1)∨…∨(a
p
∧C
p
) = (a
1∧C
1)∨…∨(a
p
∧C
p
) ⇔ (m ∧ C) ∨ C
1 ∨ … ∨C
p
= C
1 ∨ … ∨C
p
. Two possible cases are listed as follows, (1) ℑ2(Ψ,C) = ø, the term (m∧C) can not be deleted; (2) ℑ2(Ψ,C) ≠ ø, if (∃i
0) such that S¢i0 S'_{i_0 } = ø, then (m∧C) can be deleted, otherwise ((m∧C)∨C
1∨…∨C
q
)(v
1, …, v
n
) = (C
1 ∨ … ∨ C
q
)(v
1, …, v
n
)(∀(v
1, …, v
n
) ∈ L
3
n
) ⇔ (C
1′ ∨ … ∨ C
q
′)(u
1, …, u
q
) = 1(∀(u
1, …, u
q
) ∈ B
2
n
).
KeywordsLattice–Boolean function–Quasi-Boolean algebra–Quasi-Boolean function
We consider the problem of enumerating the prime implicants of a given discrete function as a basic task of circuit theory. First, we count PI's for random Boolean functions. Then we use the well known lattice differentiation as a tool for finding implicants. The concept of a peak admits to characterize prime implicants, at least those with no improper domains. The improper case can be reduced to a lower dimensional problem. Since the peak test is local, a parallel algorithm is available. The time and space complexity turns out to be low measured in the input size.
By investigating some families of elementary order-2 matrices, new
transforms of real vectors are introduced. When used for Boolean
function transformations these transforms are one-to-one mappings in a
binary/ternary vector space. The concept of different polarities of
considered arithmetic and adding transforms is introduced. The links of
arithmetic and adding transforms with classical logic design are
discussed
In this paper we propose a practical framework to utilize quantum computers in the future. To the best of our knowledge, this is the first paper to show a concrete usage of quantum computation in general programming. In our framework, we can utilize a quantum computer as a coprocessor to speed-up some parts of a program that runs on a classical computer. To do so, we propose several new ideas and techniques, such as a practical method to design a large quantum circuits for search problems and an efficient quantum comparator.
ResearchGate has not been able to resolve any references for this publication.