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COMPARATOR DESIGN USING FULL ADDER
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In this paper designing of comparator is done with the help of Full adder which is an important part of ALU and basically a basic functional unit of the DSP & microprocessors. In today’s world of technology it has become very essential to develop such new design techniques which must reduce the power or area consumption. So here comparator are developed using various styles of full adder with the help of DSCH and Microwind tool with 120 and 70 nm technology.
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... Figure 1 depicts the basic 1-bit comparator. It is useful in control applications where the binary integers representing the monitored physical element are compared to the reference values [26][27]. ...
The Internet of Things (IoT) applies the sensors and microcontrollers and links them through the internet. The eventual objective of low-power devices for Internet of Things is to lesser the overall system power and to extend battery life. For the development of energy efficient IoT devices, novel adiabatic techniques are proposed. By improving the performance of the comparator, one can improvise the whole system performance. The efficacy of computing devices depends on the performance of arithmetic circuits, including comparator. This paper proposes 1-bit comparator design using adiabatic techniques such as DC-DB PFAL (Direct current diode-based positive feedback adiabatic logic) and MPFAL (Modify positive feedback adiabatic logic) which are well-suited with an extensive range of applications (e.g. IoT sensors and an inbuilt analog to digital converter). For performance analysis, the results are compared together along with the other adiabatic and non adiabatic designs already reported in the literature. This paper proposes a way to decrease the dissipation of power and transistor count in binary circuits as it is one of the primary concerns. From the results, it is found that the design using DC-DB PFAL logic shows an improvement in power-delay-product of 69%, 94% and 90% compared to MPFAL, PFAL and ECRL techniques respectively.
... A 2-bit magnitude comparator developed by [11] shows 9.791μW of power dissipation with 30 transistors using the GDI technique. 2-bit comparators using Full adder logic as seen in [12] and [5] provide high performance in terms of power consumption of only 9.341μW and 0.818μW covering 326.2µm 2 and 290.8µm 2 area, respectively. These techniques include two complete adders, two inverters at one input, two AND gates at comparator output, and one XOR gate at output. ...
In Very Large-Scale Integration (VLSI) systems, a magnitude comparator (MC) is a component of Arithmetic Logic Unit (ALU) used to make binary decisions. Recent technologies demand the use of power-efficient methodologies as well as techniques that require a lesser number of transistors. In this paper, a magnitude comparator is developed using full adder design logic. Full adders are basic components of the ALU which is the logical and arithmetical unit of the microprocessors and Digital Signal Processing (DSP). This design consumes less power and area when compared to other logic styles in the literature. The proposed comparator has been designed using DSCH 3.5 and simulations are done on Microwind 3.5 via 0.12 μ technologies. This comparator shows a power consumption of 31.746μW using 36 transistors. The proposed design exhibits a full adder logic-based comparator with less power consumption and transistor count as compared to those in recent literature.
... % 1-bit comparator (MUX 6T) 65nm 154 29.46 6 0.176 proposed comparator 90nm 230 34.36 8 0.274 130nm 300 75.82 9 0.682 180nm 1428 97.68 12 1.172 Direct logic based comparator ( Chandrahash and Veena, 2014) 120nm 326.2 8.03 9.341-87.68 4-bit comparator design (TG) ( Anjali and Pranshu, 2014) 120nm 1320.3 77.271-bit Hybrid comparator ( Anjali et al., 2013) 120nm 329.3 8.89Hybrid 2-bit comparator ( Rachana et al., 2016) 90nm7458 99.5 1336 99.9 PTL logic comparator 45nm 140( Aggarwal and Kaur, 2015) 90nm 296.7 22.48 In MUX 6T comparator (1-bit) the current flow of the carriers is regulated. ...
This paper presents an implementation of comparator (1-bit) circuit using a MUX-6T based adder cell. MUX-6T full adder cell is designed with a combination of multiplexing control input and Boolean identities. The proposed comparator design features higher computing speed and lower energy consumption due to the efficient MUX-6T adder cell. The design adopts multiplexing technique with control input to alleviate the threshold voltage loss problem which is commonly encountered in Pass Transistor Logic (PTL) design. The proposed design successfully embeds the buffering circuit in the full adder design which helps the cell to operate at lower supply voltage compared with the other related existing designs. It also enhances the speed of the cascaded operation significantly while maintaining the performance edge in energy consumption. In the proposed design, the transistor count is minimized. For performance comparison, the proposed MUX-6T comparator (1-bit) is compared with four existing full adders based comparators using BSIM4 model parameters. The simulations are performed for 65nm process models indicate that the proposed design has lowest energy consumption along with the performance edge in both speed and energy consumption. The variants namely area and power of the proposed comparator is also compared with the published author designs to validate its suitability for low power and high speed mobile communication applications.
An efficient VLSI architecture for minimized sorting network (Vasanth sorting) in rank ordering application to remove salt and pepper noise is proposed. The basic operation in salt and pepper noise removal is rank ordering. In this work, a novel 2D sorting technique referred to as Vasanth sorting is proposed for a fixed 3 × 3 window. Vasanth sorting requires only 25 comparators to sort 9 elements of the window. A parallel architecture is developed for Vasanth sorting with 25 comparators. The processing element of the parallel architecture is an 8-bit data comparator (Two cell comparator). The performance of the proposed sorting technique is compared with the different sorting technique which is targeted for XCV1000-5bg560 on XILINX 7.1i and xc7v2000t-2flg1925 Xilinx 14.7 project manager respectively with Modelsim 10.4a for simulation and XST compiler tool for synthesis using VHDL. It was found that the parallel architecture developed for Vasanth sorting requires the only ¼ of the area in FPGA when compared to existing sorting techniques. The combinational delay of the proposed architecture was also twice as less like their counterparts. The power consumption of the logic was 7mw. Hence the above performances make Vasanth sorting a better choice compared to existing techniques for rank ordering.
In this paper a new design of cascaded comparator is described. Comparator is the basic building block of many arithmetic and logical units used in microprocessors and DSP. In the world of new emerging technology it has become essential to develop various new design concepts to reduce the power consumption and chip area. In this paper a semi-custom design of cascaded comparator has been presented and compared with the auto-generated layout on CMOS 90nm foundry technology. The proposed semi-custom design of cascaded comparator has showed an improvement of 35.65 % of total area as compared to auto-generated layout.
A comparator for the LHCb readout chip, the Beetle, has been designed in a 0.25µm CMOS technology and is sent for fabrication. To improve threshold uniformity, each comparator has a 3 bits DAC. The comparator can handle positive and negative input signals. A polarity signal changes the polarity of the threshold level and makes the output signal always active high. The output signal is latched by a 40MHz clock and is selectable between time-over-threshold mode (in 25ns bins) and one pulse mode (25ns). Simulation results will be discussed in section II.
Low-power wide-dynamic-range systems are extremely hard to build. The biological cochlea is one of the most awesome examples of such a system: It can sense sounds over 12 orders of magnitude in intensity, with an estimated power dissipation of only a few tens of microwatts. In this paper, we describe an analog electronic cochlea that processes sounds over 6 orders of magnitude in intensity, and that dissipates 0.5 mW. This 117-stage, 100 Hz to 10 KHz cochlea has the widest dynamic range of any artificial cochlea built to date. The wide dynamic range is attained through the use of a wide-linear-range transconductance amplifier, of a low-noise filter topology, of dynamic gain control (AGC) at each cochlear stage, and of an architecture that we refer to as overlapping cochlear cascades. The operation of the cochlea is made robust through the use of automatic offset-compensation circuitry. A BICMOS circuit approach helps us to attain nearly scale-invariant behavior and good matching at all frequencies. The synthesis and analysis of our artificial cochlea yields insight into why the human cochlea uses an active traveling-wave mechanism to sense sounds, instead of using bandpass filters. The low power, wide dynamic range, and biological realism make our cochlea well suited as a front ender cochlear implants.
An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technol- ogy used to implement the digital circuits, the circuit style and topology, the architecture for implement- ing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture based voltage scaling strategy, which uses parallelism and pipelining, to trade-off sili- con area and power reduction. Since energy is only consumed when capacitance is being switched, power can be reduced by minimizing this capacitance through operation reduction, choice of number representation, exploitation of signal correlations, re-synchronization to minimize glitching, logic design, circuit design and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full- motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1V supply and con- sumes less than 5mW.
CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for CMOS circuits. Appropriate for electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low-power design techniques, design for manufacturability and design for testability. This book provides rigorous treatment of basic design concepts with detailed examples. It typically addresses both the computer-aided analysis issues and the design issues for most of the circuit examples. Numerous SPICE simulation results are also provided for illustration of basic concepts. Through rigorous analysis of CMOS circuits in this text, students will be able to learn the fundamentals of CMOS VLSI design, which is the driving force behind the development of advanced computer hardware.Table of contents1 Introduction2 Fabrication of MOSFETS3 MOS Transistor4 Modeling of MOS Transistors Using SPICE5 MOS Inverters: Static Characteristics6 MOS Inverters: Switching Characteristics and Interconnect Effects7 Combinational MOS Logic Circuits8 Sequential MOS Logic Circuits9 Dynamic Logic Circuits10 Semiconductor Memories11 Low-Power CMOS Logic Circuits12 BiCMOS Logic Circuits13 Chip Input and Output (I/O) Circuits14 Design for Manufacturability15 Design for Testability
The dynamic range of operation of a system is measured by the ratio of the intensities of the largest and smallest inputs
to the system. Typically, the dynamic range is quoted in the logarithmic units of decibel (dB), with 10dB corresponding to
1 order of magnitude. The largest input that a system can handle is limited by nonlinearities that cause appreciable distortion
or failure at the output(s). The smallest input that a system can handle is limited by the system’s input-referred noise floor.
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