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On-Chip Integrated Cell-Level Power Manangement
Architecture with MPPT for PV Solar System
Ahmed Shawky, Fatma Helmy,
and Mohamed Orabi, Senior Member, IEEE,
APEARC, Aswan University,
Aswan 81542, Egypt, orabi@ieee.org
Jaber Abu Qahouq, Senior Member, IEEE,
and Zhigang Dang
Department of Electrical and Computer Engineering,
The University of Alabama, Tuscaloosa, Alabama 35487, USA
Abstract—This paper presents the design of an on-chip
integrated power management architecture with Maximum
Power Point Tracking (MPPT) for Photovoltaic (PV) solar
system. The system is developed in order to extract higher
power for PV system under partial shading and other
mismatching conditions. The MPPT circuit is implemented in
0.35µm Complementary Metal–Oxide–Semiconductor (CMOS)
technology. The on-chip system utilizes a high-efficiency
synchronous DC-DC boost power converter and analog Ripple
Correlation Control (RCC) circuit for MPPT control. The
2400µm×5000µm developed Integrated Circuit (IC) is connected
to a solar cell with 0.5V nominal output voltage and 5A output
current. A peak efficiency of 92% is achieved. The design of the
power stage and analog RCC MPPT algorithm circuit are
presented and examined in this paper.
I. INTRODUCTION
Solar PV energy is being increasingly utilized in civil
and industry applications [1–4]. Since the output power of a
PV panel varies with temperature and solar irradiance level, a
major challenge is to ensure maximum output power from PV
panels under all conditions.
Maximum power point tracking controllers are used to
ensure that PV panels operate under their highest efficiency
level, or close to it. Examples of commonly discussed MPPT
techniques are conventional Perturb and Observe (P&O)
algorithm [5-8], Incremental Conductance (IncCond) [9-12]
algorithm, open-circuit voltage (Voc) based technique, and
short-circuit (Isc) current based technique [13, 14]. However,
these conventional MPPT techniques alone fail to track the
Maximum Power Point(s) (MPPss) under multiple output
power peaks which results from partial shading conditions
and other mismatching conditions [15, 18-20, 26].
Distributed MPPT (DMPPT) methods have been
developed in order to improve the MPP tracking efficiency in
large PV power systems. They operate in order to extract
larger amount of power when the system’s PV solar panels
are not subject to uniform operating conditions [16-20, 26].
Figure 1 shows a block diagram of conventional MPPT
architecture with array-level distributed MPPT. The DMPPT
architecture is able to reduce the partial shading effect as the
MPPT distribution level moves into cell level [18, 19].
Assigning a power converter and a controller circuit to
each single PV solar cell results in cost and size increase. The
design should also target achieving low circuit power
consumption. In this paper, an on-chip integrated MPPT
controller with integrated power stage is presented in order to
track the MPP of a single PV solar cell in a cell-level
distributed MPPT architecture. The system implementation
and operation boundary conditions under variable loads and
irradiation levels are evaluated. Then, the desired operational
regions are defined. The IC design is discussed and the
physical layout of the IC is developed. The operation of the
system when connecting multiple cells in series is also
presented.
Figure. 1 Block Diagram of conventional PV system with array-level
distributed MPPT architecture for a.
II. SYSTEM CONFIGURATION
In the cell-level distributed PV solar system
configuration of this paper, the output of each single PV solar
cell is attached to a MPPT integrated IC, as illustrated in Fig.
2 [18-22]. The dark gray square named “MPPT” includes an
on-chip integrated DC-DC synchronous boost power
converter and the MPPT controller as illustrated in Fig. 3,
forming a cell-level MPPT integrated module. The
synchronous boost converter is used to increase the output
voltage of the integrated module. Ripple Correlation Control
(RCC) algorithm is used in the integrated module for
extracting the MPP [23]. In order to create a PV panel or
system that is immune to partial shading and other
mismatching effects, the outputs of several MPPT ICs
(modules) are connected in series to form a sub-string of PV
solar cells and the sub-strings are connected in parallel to
form a panel system as illustrated in Fig. 4. Using this
technique, the MPP will be tracked for each cell, and
therefore even if one or more cells are partially shaded or has
mismatches with the other cells, they will not affect the
output power of the other MPPT ICs in the system.
The RCC MPPT algorithm depends mainly on the
system ripples [23]. Figure 5 shows the concept of the ripple
correlation control algorithm. The integrated circuit design
based on the RCC concept is presented in the next section.
Figure 2. Single cell- attached to MPPT IC Structure.
Figure 3. Schematic illustration of a single PV solar cell attached to MPPT
IC.
Figure 4. Illustration of PV solar panel with proposed MPPT control ICs and
modules.
The concept of the RCC algorithm is that the solar cell
voltage and current are continuously sensed. Since the power
converter introduces voltage and current ripples, the slope of
change in cell voltage and cell current are obtained to
yield the change in cell power . If the signs of and
are the same, the power converter (boost) duty cycle should
be increased, called region-1. If the signs of and are
opposite, the power converter (boost) duty cycle should be
decreased, called region-2. By changing the duty cycles of the
boost converter, the solar cell operating point is moved
towards its MPP.
Yes
No
Figure 5. The RCC MPPT algorithm flowchart [23].
The synchronous boost converter circuit shown in Fig. 6
operates around the maximum power point using RCC MPPT
control circuit. MN2 is used as a synchronous switch in order
to increase the system efficiency. The block diagram of the
RCC control circuit is shown in Fig. 7. A current sensor
circuit is used to sense the inductor current and produce a
voltage signal
corresponds to the inductor current. The
cell voltage is then multiplied by the voltage signal to
produce a voltage signal which indicates the output power of
the cell.
Figure 6. Synchronous DC-DC boost power converter circuit.
Figure 7. The block diagram of the RCC MPPT circuit.
The power signal
and the voltage signal are
applied to two differentiator circuits, Differentiator (1) and
Differentiator (2) as shown in Fig. 7. The output of these two
blocks is compared using XOR circuit in order to identify the
location of the operating region on the P-V curve. When the
output signals of the two differentiators and are in
phase, the system operates in region-2, the left side of the
MPP and the output of the XOR is logic 0. This output is
applied to an integrator circuit. The duty cycle is generated by
using the PWM block which is fed to the switches through
the gate drive block. It is worth noting that duty cycle
decreases in region-1 mode as the MPP is reached, and vice
versus.
III. DESIGN OF THE PROPOSED POWER MANAGEMENT
ARCHITECTURE WITH MPPT IC
The power management IC consists of a synchronous
boost power converter circuit (except for the power inductor
which is connected externally to the chip) and a controller
circuit which performs the MPPT for a single solar cell. The
circuits are designed and simulated in HSPICE Simulator
using 0.35µm CMOS technology libraries. The following
subsections describe the important blocks of the proposed
MPPT power management IC for distributed PV solar system
at the cell-level.
A. Synchronous DC-DC Boost Power Converter
As discussed earlier, in cell-level PV MPPT
configuration, size and cost are two important factors.
Therefore, synchronous boost is integrated on the same
MPPT chip in order to take an advantage of the relatively low
voltage of the solar cell. The designed integrated synchronous
boost converter is optimized for 0.5V input voltage which is
equal to the maximum open circuit voltage of the cell, 1.2 A
output current and 500kHz switching frequency. Other
parameters of the proposed boost circuit are shown in Table.
1. The design utilizes two NFETs for lower condition losses.
Low input capacitor value is selected based on the required
input voltage ripple for the RCC control. It is worth noting
that the input voltage is an important design factor for the
RCC control to assure high tacking efficiency for the MPP
especially with low irradiation conditions
TABLE. 1: SYNCHRONOUS BOOST CONVERTER
PARAMETERS
parameter value parasitic
Power Inductor 400 1.5
Main FET ( N channel 6.39
Synch FET ( N channel 6.39
Input Capacitor 1
μ
1
Output Capacitor 50
μ
2
Figure 8. Current sensor circuit diagram.
B. Current sensor circuit
The current sensor circuit is designed based on reference
[24] and is shown in Fig. 8. The transistors and are
the power MOSFETs of the boost converter. The gates of
transistors and are connected together. During the
ON time period of transistor , the inductor current passes
through . The two transistors and are matched and
biased in the saturation region. The currents through and
are small and equal to which forces the voltage
of to be the same as the voltage of and therefore
and voltages have the same value. and have the
same gate and drain voltages which forces the current that
passes through to be proportional to the current that
passes through , which is the inductor current. This
current is mirrored by to and produces a voltage signal
that represents the inductor current during the on time
of . This voltage charges when is turned on. When
is off, the inductor current passes through the load and
the voltage on drops to zero. In order to produce a
continuous sensed voltage that represents the inductor current
during the complete switching period, is turned off and the
capacitor is discharged to by a constant current (the
current source in Fig. 8).
C. Multiplier circuit
The multiplier circuit is designed based on reference [25]
and is shown in Fig. 9. It is used to multiply the cell voltage
signal and the output signal of the current sensor circuit,
which represent the cell current, to produce a signal that
represents the power of the cell. The multiplier output can be
calculated from (1).
(1)
where,
and
are the input signals of the multiplier,
is
the aspect ratio of transistors , , and shown
in Fig. 9.
D. Differentiator circuit
The differentiator circuit, which is illustrated in Fig. 10,
differentiates its input signal to indicate whether the input
signal is increasing or decreasing. Fig. 11 shows the CMOS
operational amplifier that has been used in the differentiator
circuit. . An internal bias circuit (a voltage divider circuit) is
used to ensure that the operation of the differentiator is not
dependent on the value of the input signal. A capacitor is
used at the input of the differentiator in order to block the DC
component of the input signal. There are two differentiators
in the controller circuit of the proposed MPPT IC/power
module. The first differentiator circuit is used to differentiate
the cell voltage signal. The second differentiator circuit is
used to differentiate the output signal of the multiplier circuit,
which indicates the cell power. When the slope of the input
signal is negative, the output signal is logic 0. When the slope
of the input signal is positive, the output signal is logic 1.
These signals are fed into XOR block.
E. Integrator circuit
The integrator circuit is used in order to obtain the
average voltage of the XOR output signal (convert the digital
value to an analog value), which represents the desired duty
cycle of the synchronous boost converter. The output of the
integrator is fed to the PWM generator in order to generate
the control signal to the switches. A simple low pass filter
circuit, as illustrated in Fig. 12, can perform the integration
function. The circuit consists of a 1MΩ resistor and 70pF
capacitor. The input to the integrator is the logic output of the
XOR circuit. If the XOR circuit output signal is logic 1, the
integrator circuit output increases and therefore the duty cycle
increases. The duty cycle change rate depends on the gain of
the integrator circuit. This gain can be calculated from (2).
. (2)
F. Pulse width modulator (PWM)
A pulse width modulator circuit consists of a sawtooth
generator circuit and a comparator circuit as shown in Fig.
13. The DC voltage, which is the integrator output voltage, is
compared to a generated sawtooth signal in order to generate
the desired pulse width to control the switches of the power
converter.
The sawtooth generator circuit consists of two comparators,
one RS latch, and wide range current mode circuit (CM) as
shown in Fig. 14. Comp1 is shown in Fig. 15. The circuit
schematic of Comp 2 is shown in Fig. 16. The reason for
using different comparators is that the input signals of Comp
1 is high so the input stage of the comparator is chosen
NMOS differential amplifier. The input signals of Comp 2 is
low so the input stage of the comparator is chosen PMOS
differential amplifier. The current mode circuit converts the
input voltage signal into current signal to charges the
capacitor. The capacitor is charged with a constant current
until an upper voltage limit VH is reached, and discharges
with discharge current until a lower voltage limit VL is
reached and a new cycle begins. The output signal limits are
set with two comparators. The two comparators output
signals should toggle when the output signal exceeds the
upper and the lower voltage limits and .
Figure 9. Multiplier circuit diagram.
Figure10. Differentiator circuit diagram.
Figure 11. Operational amplifier circuit diagram used in the
differentiator circuit.
Figure 12. The integrator circuit diagram.
Figure 13. PWM circuit diagram.
Figure 14. The conventional sawtooth generator circuit.
G. Gate drive circuit
The output of the PWM is applied to a gate drive circuit,
which produces signals that drive the power transistors and
ensure that they will not be turned on at the same time
(provides synchronous switches dead-time). The gate drive
circuit, as shown in Fig. 17, consists of a NOR gate, an AND
gate, two buffers, and a bootstrap circuit. The output signal of
the gate drive circuit is used to drive transistors and
in the synchronous boost converter circuit as illustrated in Fig.
6. The source of the transistor is not connected to ground
(is floating), and therefore it requires a gate voltage signal
which is higher than in order to operate in the saturation
region. The gates of transistors and are connected
together. When the gate voltage of transistor is logic 1,
transistor is turned on and transistors and are
turned off. During this time period, the capacitor charges up to
and the output voltage at Q1 is logic 0. When the gate
voltage of transistor is logic 0, transistor is turned
off and transistors and are turned on. The output
voltage at Q1 is the sum of the capacitor voltage, , and the
output voltage of the boost converter. During this time period,
the voltage at Q1 that is applied to the gate of transistor is
high enough to turn on the transistor .
H. The Layout of the Power Management MPPT IC
The physical layout of full chip is shown in Fig. 18. The
total size of the full-chip is 2400µm×5000µm.
IV. MPP CONVERGENCE REGION OF OPERATION
The MPPT controller senses the voltage and the current
of the PV solar cell in order to track the MPP of the cell by
adjusting the value of the duty cycle. When the load current
changes, the controller adjusts the duty cycle of the power
converter in order to maintain the operation at the MPP. The
MPPT controller should converge to the MPP of the cell
under varying conditions such a load and irradiance level
variations. The duty cycle possible range limits the range of
load variation and irradiance variation under which the
operation can be maintained at the MPP. This implies that
there is a related region of operation under which the system
can converge to the MPP. The convergence region of
operation is studied in this paper. The load current range has
been identified under which the MPPT controller is able to
converge to the MPP for different irradiance conditions.
In the synchronous boost power converter, the input
current is higher than the output current. Increasing the load
current makes the duty cycle at the MPP decreases, until the
PV fails to deliver the required input current especially at low
irradiation levels. At this point, the input current is very close
to the load current. Fig. 19 illustrates the required duty cycle
at the MPP for each load current and at different irradiation
levels. It is clear that the duty cycle at the MPP, D, decreases
as the load current increases or the irradiation level decreases.
As the designed system should be capable of extracting the
MPP under all different irradiation levels, lower load current
should be chosen so under all irradiation levels, the system
converge and the duty cycle at MPP exists. For example, at
2.5A load, the converged duty cycle at MPP can support only
irradiation levels of 800w/m2 and above. However, if we use
1A load, the system can support irradiation levels of
300W/m2 and above. This discussion clarifies the limitation
for the load current range as a factor of irradiance levels
operation. Another very important design factor is the
tracking efficiency. Tracking efficiency is the ratio of the
actual system extracted input power (Vcell times Icell) to the
defined maximum power of the cell at specified irradiation
level (obtained from cell PV curve). The total system
efficiency is the multiplication of the tracking efficiency and
the converter efficiency. So it can be defined as the ratio of
the total system output power (Vo times load current) to the
defined maximum power of the cell at specified irradiation
level. Fig. 20 shows the relationship between the total system
efficiency as a function of the load current. From this study,
1.2A load current is defined as the optimum load under all
irradiation levels to achieve the system convergence and keep
high system efficiency.
Figure 15. Comparator circuit used in the sawtooth generator circuit.
Figure 16. Comparator circuit used in the sawtooth generator circuit.
Figure 17. The gate drive circuit.
Figure 19. Duty cycle verses load current at differen
t
Figure 20. Total system efficiency at different irradiati
o
current.
V. DESIGN RESULTS
The designed power management IC is t
e
load current and fed from 2W PV cell with
0
voltage/6A short circuit current.
First the system has been examined
irradiation levels to confirm the develop
e
algorism. Fig. 21 shows the simulation re
s
voltage, cell current and output voltage f
o
irradiation levels, 1000, 800 and 400W/m
2
.
I
system reach steady state after transient
voltage records 0.36368V and output volta
g
1.2A. These values match the cell maximu
m
Figure 18. Physical Layout of Full-Chip.
t
irradiatio
n
levels.
o
n levels versus load
e
sted under 1.2A
0
.5V open circuit
under different
e
d MPP control
s
ults for the cell
o
r three different
I
t is clear that the
period and cell
g
e of 1.4231V at
m
operating point.
As the irradiation level decreases, t
h
voltage also decrease and therefo
decreases. Fig. 22 shows the input
synchronous boost converter at th
e
levels. The recorded results confir
m
the integrated controller. This ass
u
track the MPP at each level.
Figure 21. Simulation results of
p
ower ma
n
irradiation levels ( 1000,8
0
Figure 22. Input power and output power
u
1000W/m
2
1000W/m
2
h
e cell voltage and output
re the extracted power
a
nd output power of the
e
same tested irradiation
m
the proper operation of
u
res that the system can
n
agement IC under different
0
0 400/
).
u
nder different irradiations.
800W/m
2
400W/m
2
800W/m
2
400W/m
2
Also, to confirm the control theory, two
t
the first test, the system is forced to operate
cycle value than the MPP duty cycle. Fig.
2
p
ower, cell voltage, and cell current for tha
t
that the cell power and the cell voltage are i
n
forced duty cycle is shown in the
b
ottom tr
a
If the system is forced with a duty cycle hig
h
one, the cell power and the cell voltage ar
e
shown in Fig. 24. Fig 25 shows the cell
current and the cell power at maxim
u
operation.
Fig. 26 shows the MPPT IC tracking
converter circuit efficiency, and the e
f
complete power management IC at 1.2A. It
that there is the system is tracking the true
point correctly as the tracking efficiency
especially at higher irradiation levels. The
p
the boost power converter is record to be
9
and above 90% at the irradiation range of in
t
the total system efficiency records about 93
%
in the figure.
Figure 23. Cell power, cell voltage, cell current and dut
y
power management IC when forced with smaller duty
duty cycle.
Figure 24. Cell power, cell voltage, cell current and dut
y
power management IC when forced with higher duty
c
duty cycle.
t
ests are done. In
at a smaller duty
2
3 shows the cell
t
point. It is clear
n
-phase. Also the
a
ce of the figure.
h
er than the MPP
e
out-of-phase as
voltage, the cell
u
m power point
efficiency, boost
f
ficiency of the
can be observed
maximum power
is almost unity
p
eak efficiency of
9
5% at 750W/m
2
n
teres
t
. Therefore,
%
peak as shown
y
cycle waveforms of
cycle than the MPP
y
cycle waveforms of
c
ycle than the MPP
Figure 25. Cell voltage, current and power w
a
IC.
Figure 26. Tracking efficiency, converter an
d
1.2A.
Figure 27. Input and output power of the thre
e
different irradiation co
n
As a validation for the propose
d
level power management architectur
e
connected in series. Each cell has its
MPPT IC. Each cell exposed to d
i
The solar irradiance levels of the c
e
W/m
2
and 400 W/m
2
respectivel
y
simulation results for the input po
w
this system. Each module with a c
e
MPP without being affected by t
h
Therefore, the total system can deli
v
a
veforms of power management
d
full system efficiency at load
e
cells connected in series under
n
ditions.
d
o
n
-chip integrated cell-
e
, three different cells are
own power management
i
fferent irradiation level.
e
lls are 1000 W/m
2
, 750
y
. Fig. 27 shows the
w
er and output power for
e
ll has extracted its own
h
e in series connection.
v
er the maximum power.
This is the main advantages of the proposed on chip power
management IC for every cell.
VI. CONCLUSION
In this paper, on-chip integrated power management
architecture with maximum power point tracking system is
proposed. The main advantage of the proposed system that it
introduce the freedom for every PV cell to operate at its
maximum power point without any restriction or limitation
from the system. Also, tracking the MPP of each cell in a PV
system solves the issue of partial shading effects. Using the
proposed system, the shaded cells can produce their own
maximum power without affecting the illuminated cells. The
detailed design of the proposed power management IC,
implementation, conversions study, stability study and the
chip layout have been presented in the paper. In conclusion, a
silicon solution of 2400µm×5000µm developed Integrated
Circuit (IC) innovative solution has been introduced for
power management with MPPT IC.
ACKNOWLEDGMENT
This work is funded in part by U.S. Department of
Agriculture (USDA) under USDA Project # 58-3148-0-204
and the Egyptian Science and Technology Development
Funds (STDF) under STDF project # 1954. Any opinions,
findings, and conclusions or recommendations expressed in
this material are those of the author(s) and do not necessarily
reflect the views of the funding agencies.
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