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Design of high performance 64 bit MAC unit

Authors:
P. Jagadeesh at VIT University
P. Jagadeesh
Ravi Siddhhan at VIT University
Ravi Siddhhan
H. M. Kittur at VIT University
H. M. Kittur
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Abstract and Figures

A design of high performance 64 bit Multiplier-and-Accumulator (MAC) is implemented in this paper. MAC unit performs important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using modified Wallace multiplier and the adder is done with carry save adder. The total design is coded with verilog-HDL and the synthesis is done using Cadence RTL complier using typical libraries of TSMC 0.18um technology. The total MAC unit operates at 217 MHz. The total power dissipation is 177.732 mW.
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All content in this area was uploaded by Ravi Siddhhan on Mar 25, 2015
Content may be subject to copyright.

Design ofHigh Performance 64 bit C Unit
  
Professor, SENSE
Tech VLSI nd year
VIT Universi
Vellore,India
Assistant Professor (senior), SENSE
VIT Universi T Universi
Vellore,India
kittur@vit.ac.in
pj agadeesh89@gmail.com
Vellore,India
msravi@vit.ac.in
 -      
   
  
      
    
        
   
     
      
         

-    
 
 
       
    
   
 
     
      
     
  
   
     
      
 
      
  

      
      
     
       
       
    
        
        
      
  

        
      
      

 




       
  
      
       
       
 


    
        
     
     
      
       
      
   
    
        
         
        
          


         

 
         

      
 
         
  
         
  
         
  
 

 



    

      
    
     
 
    
  
        
      
       
          
    
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     

        
         
       


 
         
        
        
         
   
  
        
     
        
        
 
           

          
     

       
         
        
        
       
        
  
  

  
         

=  
= 


        
    



 

     
     
       
        

 
      

 
         
     
      
 
       
        
        

        













 



 
 
 


 
 


 
 
 
 

 






    
    
    

 


  
   

    










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
     
  
  


    

  

    
  

    
  

    

 

    
 

    
 

    

 

    
 

    
 

          
     

 
     
  

        
       
        









 

 

 
          
        
        


 

        
  
,
     
     
       
   

         
      

     
  

  
  
  
    
    
    
    
    
    
    
    
    
         
 

       
   
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
       
    
       
  
      
       

   
    
   
 
   
        

  
  
  
  


       
   
         
       
          
      
          
     
     
      


      
  
       
  
          
      
 
          
     
       
    
       

      
       
     

 
  
  
       
      
     

       
  
         
    
       
 
        
        
     
   
        
      
        
 
... MAC's simple operation is to multiply two variables (X i and Y i ) and add the product to the last cycle's output. Therefore, the MAC architecture includes the key operational blocks of a multiplier, adder, and register/accumulator [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. The multiplier multiplies the two input operands; the adder attaches the multiplier's output to the previous cycle's result, and the register or accumulator preserves the final addition output. ...
... In recent years, different researchers have done several works [2][3][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. Reference [22] proposes a high throughput MAC architecture that promises the optimized area in 2007. ...
... Reference [23] in 2012 suggests a novel multiplier architecture. Reference [12] proposes a novel architecture based on a transformed "Wallace tree multiplier" in 2013. The architecture is 64-bit compatible. ...
An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation
Article
Full-text available
In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8×8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between −7.96872 to +7.96872. The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as “block enabling” and “clock gating” are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.
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... In recent years, researchers have developed different MAC architectures [9][10][11][12][13][14][15][16][17]. For example, a high-speed MAC architecture that promises with an optimized area is proposed in 2007 by Abdelgawad et al. [9]. ...
... In 2012, Deepak et al. [14] proposed a novel architecture for the multiplier. In 2013, Jagadees et al. proposed a novel architecture using a modified Wallace tree multiplier [15]. The implementation is done for 64 bits. ...
... There are several architectures explained in the past by various designers. However, the architectures described in [9][10][11][12][13][15][16][17] (90% of them in the literature) are designed either in Verilog or VHDL. ...
Application of ameliorated Harris Hawks optimizer for designing of low-power signed floating-point MAC architecture
Article
Full-text available
  • Jul 2021
  • NEURAL COMPUT APPL
Recently established Harris Hawks optimization (HHO) has natural behaviour for finding an optimum solution in global search space without getting trapped in previous convergence. However, the exploitation phase of the current Harris Hawks optimizer algorithm is poor. In the present research, an improved version of the Harris Hawks optimization algorithm, which combined HHO with Particle Swarm Optimization and named as ameliorated Harris Hawks optimizer algorithm, has been proposed to find the solution of various optimization problems such as nonlinear, non-convex and highly constrained engineering design problem. In the proposed research, the exploitation phase of the existing HHO algorithm is improved using a particle swarm optimization algorithm and its performance tested for CEC2005, CECE2017 and CEC2018 benchmark problems. Also, discrete algorithms such as FFT algorithms, convolution and image processing algorithm use multiply and accumulate (MAC) unit as a critical component. The efficiency of a MAC is mainly dependent upon the speed of operation, power dissipation and chip area along with the complexity level of the circuit. In this research paper, a power-efficient signed floating-point MAC (SFMAC) is proposed using universal compressor-based multiplier (UCM). Instead of having a complex design architecture, a simple multiplexer-based circuit is used to achieve signed floating output. The 8 × 8 SFMAC can take 8-bit mantissa and 3-bit exponent. And therefore, the input to the SFMAC can be in the range of − (7.96875)10 to + (7.96875)10. The design and implementation of the proposed architecture is done on the Cadence Spectre tool in GPDK 90 nm and TSMC 130 nm technologies. The analysis has proved that the proposed SFMAC architecture has consumed the least power than the recent MAC architectures available in the literature.
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... To measure the performance characteristics, CADENCE tool RTL compiler can also be used [5] but in this case, it is done by using Xilinx tool 14.3 [1]. On an overall analysis of performances observed in different scenarios and different combinations of multipliers and adders, this paper would show how Vedic multiplier and carry look ahead adder MAC unit performs better than other combinations in terms of delay. ...
... [5] : Architecture of MAC unit ...
Analysis of Low-Delay in 64-bit Vedic multiplier based MAC unit
Conference Paper
  • Jan 2023
Delay becomes crucial part in any of the considered condition to build any integrated circuit. As delay indirectly dictates speed which means less delay, speedier working environment of circuits and vice versa which is why it is considered as main option along with other side options of parameters like power, area etc. In any processors, its speed depends upon its internal units. So, to meet the standards, A high speed MAC unit is developed and the details regarding it are explained in this paper. This MAC unit performs operations like multiplications, addition and many more required to the application. To implement this model, we write a Verilog code for total unit along with individual units and use Xilinx tool and model sim simulator. The results here show how much delay is reduced compared to other models of MAC unit. The proposed system can be implemented in FPGA Spartan 3 XC3S 200 TQ-144.
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... The algorithm of the Baugh-Wooley Multiplier is given in Fig. 4. In this Baugh-Wooley algorithm, three steps are to be considered. [6] Step 1: The MSB of the first N-1 column partial product will be negated. ...
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... Multiplication and addition are two basic functions that require additional hardware resources and computational time compared to other functional blocks. The speed of the processor is determined by the multiplier and adder blocks [3]. Recently researchers have been working on fast, power, and area-efficient multiplier, adder blocks. ...
A Novel Approach to Develop Low Power MACs for 2D Image Filtering
Article
Full-text available
  • Feb 2021
In emerging technologies, a vital role is played by ASIC designs in processor operations. There is a necessity to develop such a processor composed of low power blocks. This paper discusses the design exploration of the fixed-point multiply-accumulate unit to achieve high-speed and low power consumption. A 2D image convolution process is developed by stacking and combining several MAC blocks. The developed MAC comprises a sequential multiplier, controller, and optimized adder units. The entering image pixels and kernel pixels are checked for similarity and accordingly isolated by the controller unit, thereby saving power by eliminating the redundant multiplications. A novel idea of reducing the additions in image filtering operations is incorporated in the design. The performance of the proposed MAC showed a 28% power reduction compared to the conventional approaches.
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... Therefore, the practical applicability of such architecture needs to be further tested. Most of the architectures explained in the Table 2 The operation of the 16-bit 4:1 MUX based on the two select lines Table 4 that the performance of [6,26,27] have a significantly higher static as well as average power (in mW) than proposed SFMAC architecture. The delay of the unsigned fixed-point architecture in [27] is lesser than the proposed architecture because the operating frequency of the said architecture is much larger than the proposed SFMAC architecture. ...
A MUX based signed-floating-point MAC architecture using UCM algorithm
Article
Full-text available
  • Jul 2020
Digital system algorithms such as FFT algorithms, convolution, image processing algorithm, etc. deploy Multiply and Accumulate (MAC) unit as an evaluative component. The efficiency of a MAC typically relies on the speed of operation, power dissipation, and chip area along with the complexity level of the circuit. In this research paper, a power-delay-efficient signed-floating-point MAC (SFMAC) is proposed using Universal Compressor based Multiplier (UCM). Instead of having a complex design architecture, a simple multiplexer-based circuit is used to achieve a signed-floating output. The 8£8 SFMAC can take 8-bit mantissa and 3-bit exponent and therefore, the input to the SFMAC can be in the range of-(7.96875) 10 to +(7.96875) 10. The design and implementation of the proposed architecture is executed on the Cadence Spectre tool in GPDK 90 nm and TSMC 130 nm CMOS, which proves as power and delay efficient.
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Area, Delay and Power Comparison of Adder Topologies
Article
Full-text available
  • Mar 2012
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
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ASIC implementation of modified faster carry save adder
Article
  • May 2010
Digital Adders are the core block of DSP processors. The final carry propagation adder (CPA) structure of many adders constitutes high carry propagation delay and this delay reduces the overall performance of the DSP processor. This paper proposes a simple and efficient approach to reduce the maximum delay of carry propagation in the final stage. Based on this approach a 16, 32 and 64-bit adder architecture has been developed and compared with conventional fast adder architectures. This work identifies the performance of proposed designs in terms of delay-area-power through custom design and layout in 0.18um CMOS process technology. The result analysis shows that the proposed architectures have better performance in reduction of carry propagation delay than contemporary architectures.
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A comparison of Dadda and Wallace multiplier delays
Article
  • Dec 2003
  • Proceedings of SPIE
The two well-known fast multipliers are those presented by Wallace and Dadda. Both consist of three stages. In the first stage, the partial product matrix is formed. In the second stage, this partial product matrix is reduced to a height of two. In the final stage, these two rows are combined using a carry propagating adder. In the Wallace method, the partial products are reduced as soon as possible. In contrast, Dadda's method does the minimum reduction necessary at each level to perform the reduction in the same number of levels as required by a Wallace multiplier. It is generally assumed that, for a given size, the Wallace multiplier and the Dadda multiplier exhibit similar delay. This is because each uses the same number of pseudo adder levels to perform the partial product reduction. Although the Wallace multiplier uses a slightly smaller carry propagating adder, usually this provides no significant speed advantage. A closer examination of the delays within these two multipliers reveals this assumption to be incorrect. This paper presents a detailed analysis for several sizes of Wallace and Dadda multipliers. These results indicate that despite the presence of the larger carry propagating adder, Dadda's design yields a slightly faster multiplier.
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On Parallel Digital Multipliers
Article
  • Oct 1976
Various schemes of parallel digital multipliers based on parallel counters (used to reduce to two numbers, whose sum equals the product, the set of summands equivalent to the product) are reviewed and compared. It is also suggested that parallel counters could be implemented using available fast ROMs. Such counters allow the implementation of parallel multipliers having a total delay of 100 ns or even less.
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Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
Article
  • Mar 2011
Two's complement multipliers are important for a wide range of applications. In this paper, we present a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of the partial product generation stage. This reduction may allow for a faster compression of the partial product array and regular layouts. This technique is of particular interest in all multiplier designs, but especially in short bit-width two's complement multipliers for high-performance embedded cores. The proposed method is general and can be extended to higher radix encodings, as well as to any size square and m times n rectangular multipliers. We evaluated the proposed approach by comparison with some other possible solutions; the results based on a rough theoretical analysis and on logic synthesis showed its efficiency in terms of both area and delay.
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Design and VLSI Implementation of Pipelined Multiply Accumulate Unit
Conference Paper
  • Jan 2010
In the majority of the Digital signal processing (DSP) applications, the critical operations usually involve many multiplications and /or accumulations. So, for real time signal processing applications, high throughput multiplier -accumulator (MAC) is always a key element to achieve a high-performance digital signal processing application. In the last few years, the main consideration of MAC design is to enhance its speed. This is because speed and throughput rate are always the concerns of digital signal processing systems. However due to the increase of portable electronic products, low power designs also become another major consideration. This is because, the limited battery energy of these portable products restricts the power consumption of the system. Therefore the main motivation is to investigate various pipelined MAC architectures and circuit and the design techniques which are suitable for the implementation of high through put signal processing algorithms. The goal of this project was to design and VLSI implementation of pipelined MAC for high-speed DSP applications at 180nm technology. For designing the pipelined MAC, various architectures of multipliers and one bit full adders are considered. The static and dynamic one bit full adder was implemented as the basic block. For checking the functionality of the whole system, spice code is written using the HSPICE by defining all the blocks in the circuit as the sub circuits. Then a schematic capture is done using schematic composer from virtuoso starting from bottom level to top level. Finally the layout for the complete MAC is done using virtuoso.
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