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A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension
Abstract
Signal processing in ultra-wide bandwidths is one of the key challenges in the design of multi-Gb/s wireless transceivers at mm-Waves, where channels covering 57GHz to 66GHz are specified. Further considering spreads due to process variations and the stringent reference phase noise to ensure signal integrity calls for an ultra-wide tuning range and low-noise on-chip oscillator. Meeting this target is even more challenging when adopting an ultra-scaled CMOS technology node where key passive components suffer from a reduced quality factor (Q) [1]. In a 32nm node the thickness of metals closer to the substrate is half that in a 65nm process leading, for example, to MOM capacitors with roughly half Q. The penalty is only marginally compensated by the higher transistor ft, improved only by ~20%. Various techniques exploiting alternative tuning implementations have been published recently. Magnetic tuning methods where the equivalent tank inductance is varied through reflection of the secondary coil impedance of a transformer demonstrate outstanding tuning ranges but at the cost of a severe trade-off with tank Q and poor noise FOMs [2,3]. A bank of capacitors switched in and out in an LC tank is the most popular tuning approach [4-6]. However the quality factor is severely degraded, when large ranges are involved. In this work, the switched-capacitor tank of the VCO shown in Fig. 20.3.1 is centered around two different resonance frequencies by splitting the inductor through the switch Msw. In particular, an up-shift is produced when the switch is off due to its parasitic capacitance. The frequency range is significantly increased without compromising tank Q leading to large tuning range and high FOM simultaneously. Prototypes of the VCO have been realized in 32nm CMOS showing the following performances: 31.6% frequency tuning range, minimum phase noise of -118dBc/Hz at 10MHz offset from 40GHz with 9.8mW power dissipation. Despite being realized in a- ultra-scaled 32nm standard digital CMOS process without RF thick metal options, the oscillator shows state-of-the-art performances.
... The most common way of expanding the tuning range is introducing a switched inductor, which is used for coarse tuning, whereas the varactor is used for fine tuning of VCO frequencies [5,6,7,8,9,10]. In [5], variable inductor (VID) using a tunable resistor as the transformer load has a nonlinear tuning-curve with large effective K VCO . Studies report that the transformer-based or NMOS switched VID exhibits lower Q compared with the conventional inductor, which degrades the PN performance of the VCO, especially when the switch is located on the direct path of the signal [10]. ...
A dual-mode wide tuning range voltage-controlled oscillator (VCO) based on switchable weakly coupled cores is presented in this paper. The dual-mode operation is achieved when the two switched VCO cores are under ON and OFF states. A weakly coupled transformer with small coupling coefficient of the two-coupled LC tanks of two VCO cores is used to ensure that the VCO works at desired frequency under both modes. The results show that large coupling coefficient between the LC tank of two VCOs and LC tank of buffer enhances the quality factor of the VCO’s LC tank at lower resonant frequency under both modes. Fabricated in a 55 nm CMOS process, the VCO covers the frequency tuning range from 22.3 to 27.1 GHz and from 31.2 to 36.6 GHz when the switched VCO is under ON or OFF state, respectively. The dual-mode VCO achieves a phase noise of -127.6 dBc/Hz at 10 MHz offset for 22.3 GHz carrier frequency.
... For 6G, it is necessary to improve the data rates by multiplexing the modulation method more complexly, and furthermore, to broaden bandwidth by using millimeter waves, so, it needs incredibly low-phase noise characteristics even in the millimeter wave. However, in the millimeter wave range, the phase noise of the voltage-controlled oscillator is getting worse due to the degradation of the Q-factor of the varactor [1] thus it is considered difficult to achieve such a low phase noise and the wide frequency tuning range in the fundamental frequency, such as 28 GHz [2,3,4,5,6,7,8,9,10,11,12,13]. Therefore, the combination of a lower frequency oscillator with extremely low phase noise and a multiplier with low noise contribution is one of the candidates. ...
This paper presents ultra-wideband 18.2-42.0 GHz LC injection-locked frequency doubler (ILFD) with transformer inputs. To expand the locking range, the proposed ILFD incorporates the transformer connected to the source of the gain-cell transistor to obtain high linearity of the input circuitry, moreover, the input matching frequency shifts from the free-run frequency of the oscillator. The measured maximum locking range exhibited 79.1% from 18.2 GHz to 42.0 GHz output at 0 dBm input power and the locked phase noise at 1MHz offset from 28 GHz carrier frequency was −112.1 dBc/Hz under 1.7 mW power consumption. Also, the lowest locked phase noise at 1 MHz offset from the carrier was −122.8 dBc/Hz under 21.2 mW power consumption, and it was only 2.2 dB degraded from the theoretical value. The process technology used in this work was TSMC-180nm CMOS.
... Several techniques have been proposed to reduce the C-DAC routing parasitics and hence extend the TR at mm-Wave frequencies. In [7] and [8], switched inductors are used to minimize the size of the C-DAC array, at the expense of switching losses, design complexity, and footprint. Frequency multiplication can also be used to reduce the routing parasitic inductance by operating the VCO core at lower frequency, but this has the drawback of increased power consumption [9]. ...
This article presents a detailed analysis of the impact of the tank feedline on tuning range (TR) and phase noise (PN) in millimeter-wave
LC
voltage-controlled oscillators (VCOs). A robust extended TR design, with low PN and small die area, is later proposed, analyzed, and experimentally validated. A new interconnect approach for the coarse tuning capacitor bank is used to significantly reduce the
LC
tank routing capacitance and resistance, thus improving the TR and PN of the VCO. As a proof of concept, a 26.8-GHz VCO with a 5-bit digitally switched-capacitor bank [capacitor digital-to-analog converter (C-DAC)] is implemented using a folded feedline routing structure in a digital 45-nm CMOS silicon-on-insulator (SOI) technology. Compared to a conventional layout structure, the proposed interconnect technique yields a wider TR and lower losses while significantly improving the linearity of the C-DAC. The fabricated VCO yields a TR of 33%, covering the extended 5G frequency band with a sufficient margin from 22.4 to 31.2 GHz, with a minimum overlap of 40%. Moreover, it achieves a PN of −105.5 and −97.2 dBc/Hz at a 1-MHz offset at the low and high bands, respectively, while dissipating 6 mW from a 1.0-V supply, corresponding to an average FOM
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub>
of −192.6 dBc/Hz.
... There are different techniques such as, coupling two LC sections [10,11], and using voltagecontrolled oscillator with a transformer as an inductance [12]. Therefore, the design of low noise oscillator and low power consumption with high frequency is significant [13][14][15][16][17]. ...
A varactor-less cross-coupled voltage-controlled oscillator based on triple frequency is presented in this paper, which is optimized for a low phase noise and low power at the high frequency. The VCO consists a voltage to current, a triple frequency, and a mixer with band-pass filter. The varactor-less VCO adjusts the frequency with the current and voltage of transconductance cell. A network RF–CF–RF is applied to filter out the noise of current source at 2 ω0. The proposed circuit was simulated in a 0.18 µm CMOS RF technology with a 1.5 V supply voltage. The designed VCO demonstrates an oscillation frequency range from 11.59 to 13.96 GHz with the triple frequency from 35.8 to 40.3 GHz. The simulated VCO presents a phase noise of −110.1 dBc/Hz at 1 MHz offset from a 40.3 GHz carrier frequency. The total figure of merit (FOMT) is −193.113 and −190.83 dBc/Hz with a DC power of 11.32 and 19.56 mW for VCO and total structure, respectively. The layout of the VCO occupies an area of 695.10 µm × 627.80 µm.
... The EM simulation results show an equivalent differential inductor value of 190 pH with Q-factor of 22.5 at frequency of 40 GHz. Comparing this Q value with that of the original varactor (4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14), shown in Fig. 5, reveals the significant role of varactor's Q-factor on the overall resonator's Q-factor. Thus, the improvement of varactors is reasonable in the above frequency. ...
Varactors are key devices in the design of voltage controlled oscillators (VCOs), as their quality factor (Q-factor) at the millimeter-wave frequency range limits the overall LC tank Q-factor. This paper presents a new circuit-level structure, called Q-enhanced varactor (QEV), composed of two MIMCAPs (Metal-Insulator-Metal capacitors) and a varactor. Depending on Q-factors and the values of the MIMCAPs, the Q-factor in QEV can be improved more than two times. The QEV parameters are analyzed and a design procedure for QEV is proposed. Also, a QEV with two times Q–factor improvement is employed in the design of a 40GHz LC-VCO, illustrating more than 6dB enhancement in the oscillator figure of merit (FOM).
... This limits the phase noise performance of oscillators operating at this frequency range. Also, in ultrascaled technology nodes, it is even more challenging to achieve a high quality factor, due to reduced thickness of the metal layers [8,9]. Thereby, the proposed VCO circuit topology, which enhances the effective Q of the LC tank, shows a potential for achieving a high spectral purity at the mm-wave frequency range. ...
The design of a wide tuning range LC-Voltage controlled oscillators (VCOs) in CMOS technology presents certain challenges, including the low-quality factor that is associated with passive elements and the considerable impact of routing parasitics. The challenges necessitate an innovative approach to the methodology employed in designing VCOs. This paper presents a design methodology of an extended wide TR LC-VCO utilizing a folded feedline layout-based parasitic reduction technique. Furthermore, the technique being proposed relaxes the required \({g}_{m}\) for the oscillation startup condition, thereby diminishing power consumption and phase noise.KeywordsFigure-of-merit (FOM)phase noiseLC voltage-controlled oscillator (LC-VCO)wide tuning rangefolded feedline
Oscillators are found in all radar and communication systems, as a signal source for up- or down-conversion and as a generator of carrier frequency. This chapter describes the theory and circuit design techniques for generating undamped, periodic, and stable, steady-state RF oscillations at a specific or tunable frequency.
The rapid development of wireless communications, software-defined radios, and ultrawideband (UWB) engenders an ever-increasing demand for clock generators that fully covers multiple frequency bands
[1]
,
[2]
,
[3]
. As the “heartbeat” that pumps clock generators, such as phase-locked loops (PLLs), microwave oscillators with wideband frequency tuning range (TR) are thus attracting a great deal of research interest.
All RF circuits use a frequency generating circuit to get the required periodic base signal. The signal is commonly created with a local oscillator (LO) combined in a phase-locked loop (PLL), and the LO signal will be used for downconversion in receivers or upconversion in transmitters. The LO signal will therefore need to satisfy some requirements: (1) the LO signal needs to be pure and has a low phase noise, (2) the LO circuit needs to be able to drive the following circuits, and (3) the frequency needs to be tunable within an acceptable range. This chapter will go over the basics of a voltage-controlled oscillator and the challenges of using a deeply scaled technology at mm-wave frequencies. Two design examples in 16 nm FinFET are given: a fundamental oscillator operating at 150 GHz and a harmonic oscillator operating at 40 GHz with a 3rd harmonic output at 120 GHz.
This paper presents an E-band frequency quadrupler in 40-nm CMOS technology. The circuit employs two push–push frequency doublers and two single-stage neutralized amplifiers. The pseudo-differential class-B biased cascode topology is adopted for the frequency doubler, which improves the reverse isolation and the conversion gain. Neutralization technique is applied to increase the stability and the power gain of the amplifiers simultaneously. The stacked transformers are used for single-ended-to-differential transformation as well as output bandpass filtering. The output bandpass filter enhances the 4th-harmonic output power, while rejecting the undesired harmonics, especially the 2nd harmonic. The core chip is 0.23 mm ² in size and consumes 34 mW. The measured 4th harmonic achieves a maximum output power of 1.7 dBm with a peak conversion gain of 3.4 dB at 76 GHz. The fundamental and 2nd-harmonic suppressions of over 45 and 20 dB are achieved for the spectrum from 74 to 82 GHz, respectively.
In this paper, an ultra-low-power octave-tuning voltage-controlled oscillator (VCO) integrated circuit (IC) is proposed, using a novel varactor with a single control voltage. The novel varactor including VCO-gain (
${K} _{\mathrm{ VCO}}$
) improving structure consists of two parallel-connected inversion-mode MOS (I-MOS) -based varactors with shifted bias and an NMOSFET operating as a variable resistor. This novel varactor is able to give a large capacitance variation with a single analog control voltage. The proposed wideband VCO IC implementing this novel varactor is designed, fabricated, and evaluated fully on-wafer in 40-nm CMOS SOI technology. The proposed wideband VCO IC has exhibited a completely continuous measured tuning range (TR) of 67.9% from 3.2 to 6.49 GHz. The measured dc power consumption is from 0.35 to 1.36 mW throughout the whole TR under a supply voltage of 0.36 V. This is an extremely low dc power consumption among the reported sub-10-GHz octave-tuning VCO ICs so far. The measured peak figure-of-merit including TR (FoMT) of the proposed VCO IC is 210.4 dBc/Hz with a carrier frequency of 6.49 GHz.
This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.
A transformer-based voltage-controlled oscillator for a W-band frequency-modulated continuous-wave (FMCW) automotive radar application is presented. The design challenges imposed by the millimeter-wave frequency operation were faced through a circuit and layout co-design approach, supported by extensive electromagnetic simulations and accurate analysis of both the start-up condition and the tank quality factor. The oscillator was implemented in a 28-nm fully depleted silicon-on-insulator (SOI) complementary metal–oxide–semiconductor (CMOS) technology. It provided a 37 GHz oscillation frequency with a variation of around 4 GHz, thus achieving a tuning range of 11%. Moreover, a 77 GHz output signal was also delivered, which was extracted as a second harmonic from the input-pair common-mode node. The circuit exhibited low phase noises, whose average performances were −97 dBc/Hz and −121 dBc/Hz at 1 MHz and 10 MHz offset frequencies, respectively. It delivered a 77-GHz output power of −10.5 dBm and dissipated 26 mW with a 1 V power supply. The silicon area occupation was 300 × 135 µm.
This paper presents a wide-tuning range dual-mode millimeter wave (mm-wave) voltage controlled oscillator (VCO) incorporating high quality-factor (Q) transformer-based variable inductors. A high Q switched inductor with two different values is proposed by constructing the load of a transformer of a high Q fixed capacitor in series with a lossless switch structure that does not add any loss to the LC-tank as implemented by changing the signals mode across the capacitor. By choosing a proper center frequency for each mode and sufficient frequency overlap, a wide frequency tuning range (FTR) mm-wave VCO can be designed. It provides almost twice higher tuning range while keeping phase noise (PN) nearly the same as the two-mode VCO designed with two standalone inductors. Fabricated in a 65 nm CMOS process, the VCO demonstrates the measured FTR of 22.8% from 64.88 to 81.6 GHz range. The measured peak PN at 10 MHz offset is -114.63 dBc/Hz and the maximum and minimum corresponding figures of merit FOM and FOMT are -173.9 to -181.84 dB and -181.07 to -189 dB, respectively. The VCO cores consume 10.2 mA current from 1 V power supply, and the occupied area is 0.146 x0.205 mm².
This article presents design techniques to facilitate the use of the driving point impedance (Z
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub>
) of one-port transformer-coupled resonators as wideband loads of millimeter-wave amplifier stages for a 28-GHz receiver front end. While the use of both the Z
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub>
of a one-port and the transimpedance (Z
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub>
) of a two-port coupled resonator is considered to achieve a wideband response, it is shown that under conditions of low magnetic coupling and constrained network quality factor, the use of Z
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub>
can result in a higher gain-bandwidth product of low-noise amplifier (LNA) amplifier stages. The effect of the complex zero in the Z
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub>
response on the in-band gain ripple is shown to be alleviated merely by lowering the quality factor of the transformer's secondary coil; this strongly motivates the use of compact, nested-inductor transformer layouts. Implemented in a 65-nm CMOS process, a three-stage LNA (with Z
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub>
wideband loads in two stages) achieves a 24.4-32.3-GHz bandwidth (27.9 % fractional bandwidth), a peak S
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub>
of 24.4 dB (20.4 dB), a minimum noise figure (NF) of 4 dB (4.6 dB), and an input-referred P1dB of -23 dBm (-22 dBm) while consuming 22-mW (9.9 mW) power from a 1.1-V (0.85 V) supply. The use of compact transformers limits the LNA's footprint to only 0.12 mm2. A 26.5-32.5-GHz quadrature receiver prototype employing the LNA achieves a 29.5-dB peak conversion gain, a 5.3-dB minimum NF, and a -26-dBm inputreferred P1dB while consuming 33 mW from a 1.1-V supply.
A switched coupled transmission line (SCTL) method with high Q and flexible structure is proposed for mm-wave VCO to improve tuning range (TR), meanwhile maintaining low phase noise, low power dissipation and zero additional area. This TR extension method is also proved effective in a switched coupled coplanar waveguide (SCCPW) VCO. Fabricated in 45 nm SOI CMOS, the SCTL-VCO achieves 38.74% TR from 39.46 to 58.42 GHz, increased by 29.2% compared to the reference TL-VCO. The SCCPW-VCO achieves 38.83% TR from 38.69 to 57.33 GHz, increased by 31.9% compared to the reference CPW-VCO. The measured phase noise of SCTL-VCO and SCCPW-VCO over the entire frequency tuning range is from \(-\) 106 to \(-\) 116.8 and \(-\) 106.1 to \(-\) 116 dBc/Hz at 10 MHz offset, while the corresponding FOM\(_T\) is from \(-\) 181.7 to \(-\) 192.5 and \(-\) 181.6 to \(-\) 191.5 dBc/Hz, respectively. Each VCO dissipates 8.6–10.8 mW from 0.7 V power supply.
This paper presents a millimeter-wave wide tuning range voltage-controlled oscillator (VCO) incorporating two switchable decoupled VCO cores. When the first core is switched on producing the low frequency band (LFB) signal and the second core is off, the inductors of the second core are reused to create additional buffers that pass the LFB signal to the output buffers. The generated high frequency band (HFB) signals by the second core when turned on, are directly fed to the output buffers. Producing the outputs of both VCO cores across same terminals without utilizing active/passive combiners and coupled inductors will enhance the phase noise performance of the VCO, increase its output power, and reduce the chip size. Fabricated in a 65-nm CMOS process, the VCO achieves a measured wide tuning range of 26.2% from 54.1 to 70.4 GHz while consuming 7.4-11.2-mA current from 1-V power supply. The peak measured phase noise at 10-MHz offset is -116.3 dBc/Hz and the corresponding FOMT and FOM varies from -180.96 to -191.86 dB and -172.6 to -183.5 dB, respectively. The VCO core area occupies only 0.1 x 0.395 μm².
This paper describes a mode-switching quad-core-coupled millimeter-wave (mm-wave) voltage-controlled oscillator (VCO), using a single-center-tapped (SCT) switched inductor for extension of the frequency tuning range (FTR) and improvement of the phase noise (PN). The switches not only serve for in-phase coupling among the VCO cores but also can modify the equivalent tank inductance suitable for coarse frequency tuning. The frequency gaps between the multi-resonant frequencies are controlled by the common-mode (CM) inductance that is precisely set by the lithography fabrication. Together with the tiny varactors for fine frequency tuning, a wide and continuous FTR can be achieved. It is analytically shown that tiny switches (i.e., small parasitic capacitance) for mode selection are adequate to avoid bimodal oscillation, synchronize the VCO cores against resonance frequency mismatches, and prevent PN degradation. A symmetrical layout of SCT switched inductor also aids the VCO to be immune to magnetic pulling. Prototyped in 65-nm CMOS, the VCO exhibits a 16.5% FTR from 42.9 to 50.6 GHz. The PN at 46.03 GHz is -113.1 dBc/Hz at 3-MHz offset, corresponding to a figure-of-merit (FoM) of 183.6 dBc/Hz. The die size is 0.039 mm
<sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
.
This paper describes a general technique for reducing oscillator phase noise in
LC
voltage-controlled oscillators (VCOs). Phase noise is reduced using a circuit topology that decouples the
LC
tank from the active devices using capacitive transformers, thereby achieving a higher amplitude of oscillation not limited by the transistor breakdown voltage. Moreover, the proposed VCO topology reduces active device noise injection into the tank by further improving phase noise. As proof of concept, two VCOs operating at 16–19 GHz and 31.8–39.6 GHz, respectively, are implemented in the Global Foundries (GF) 130-nm SiGe BiCMOS 8HP technology (
$f_{T}/f_{\text {MAX}}$
of 200/280 GHz). The lower frequency VCO achieves a phase noise of −110 dBc/Hz at a 1-MHz offset from a 17-GHz carrier while the higher frequency VCO achieves a phase noise of −103.2 dBc/Hz at a 1-MHz offset from a 36-GHz carrier. The higher frequency VCO was also implemented in a second, more advanced GF 130-nm SiGe BiCMOS 8XP technology (
$f_{T}/f_{\text {MAX}}$
of 260/320 GHz), yielding a further average phase noise improvement of 1.9 dB over the 8HP version.
An E-band direct-conversion subharmonic receiver (SHRX) is designed exploring a coupled-rotary-travelingwave-oscillator-based (coupled-RTWO-based) architecture. Distributed oscillators are leveraged to generate N = 8 differential phases at f
<sub xmlns:xlink="http://www.w3.org/1999/xlink">LO</sub>
= f
<sub xmlns:xlink="http://www.w3.org/1999/xlink">RF</sub>
/4. Current-mode passive mixers (MXs) are adopted to enable <;1-V supply operation and greatly simplify the layout. An inductively degenerated neutralized common source (DCS) low-noise amplifier (LNA) is embedded in a fourthorder transformer-based matching network to allow broadband impedance scaling and high reverse isolation. Implemented in a 28-nm bulk CMOS technology without ultra-thick top metal option, the realized prototype outperforms prior reported CMOS designs in terms of phase noise, figure of merit (FOM), and tuning range. The SHRX front end achieves 8.3-dB noise figure (NF), 12.5 GHz -3-dB RF bandwidth (BW), and -25-dBm ICP
<sub xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub>
, while consuming <;100 mW.
A rotated-phase-tuning (RPT) technique is proposed for millimeter-wave (mmW)
LC
-based oscillators. Without using varactors, the oscillation frequency is tuned by phase interpolation to vary the phase of the current flowing into the
LC
tank. Interestingly, the intrinsic delay of transistors is leveraged to rotate the phases for interpolation and thus to optimize the oscillator’s performance in terms of frequency tuning range and phase noise. Two E-band RPT oscillator prototypes are designed and implemented in a 65-nm CMOS process. The first one with four-phase output measures oscillation frequency from 67.8 to 81.4 GHz and phase noise of −108 to −113 dBc/Hz at 10-MHz offset, while consuming 13 to 25 mW from a 1-V supply. With similar power consumption, the second prototype featuring eight-phase output operates from 74.8 to 79 GHz and achieves phase noise of −116 to −118 dBc/Hz at 10-MHz offset. The four-phase and eight-phase oscillators occupy small core areas of 0.02 and 0.06 mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
, respectively.
We present a continuously tunable 52-to-67 GHz push–push dual-core voltage-controlled oscillator (VCO) in a 40 nm bulk complementary metal–oxide–semiconductor (CMOS) technology. The circuit is suitable for 60 GHz frequency-modulated-continuous-wave radar applications requiring a continuously tunable ultra-wide modulation bandwidth. The LC-tank inductor is used to couple the two VCO cores. The fundamental frequency of the VCO can be tuned from 26 to 33.5 GHz, which corresponds to a frequency tuning range of 25%. The second harmonic is extracted in a non-invasive way using a transformer. The primary side acts simultaneously as a second harmonic filter. The VCO achieves in measurement a low phase noise of −91.8 dBc/Hz at 1 MHz offset at 62 GHz and an output power of −20 dBm. The VCO including buffers dissipates in the dual-core operation mode 60 mA from a single 1.1 V supply and consumes a chip area of 0.58 mm ² .
The phase noise (PN) at the output of the phase locked loop (PLL) sets a fundamental limit to the maximum spectral efficiency that the whole system can achieve. As discussed in Chap. 1, the bit error rate against SNR requirements in an AWGN environment shown in Fig. 1.7 changes drastically when a practical PN profile is considered, see Fig. 1.16. Moreover, together with the tough PN requirements, a PLL should be able to synthesize the necessary LO signal over the whole band of operation.
CMOS technology scaling allows faster transistors at each node, making mm-Wave analog design possible. However, scaling does not provide only benefits. The lower break down voltage forces the scaling of the voltage power supply as well, posing severe limitations on linearity, device stacking and achievable signal-to-noise ratio. The back end of line (BEOL) metal stack gets thinner and closer to the substrate, making the effect of interconnection losses and parasitics dominant. Moreover, mm-Wave design is to some extend an upside down world when compared to RF design (in the low GHz range). At RF frequencies, capacitors show higher quality factor when compared to inductors. On-chip transmission lines are almost impossible to realize due to the large wavelength. At mm-Wave however the scenario is completely the opposite. Therefore, new design techniques are needed to face such technology constrains. This chapter deals with the basic blocks available to analog designers in deep-scaled CMOS. The active devices are the focus of Sect. 2.1. Passive devices are discussed in Sect. 2.2. The aim is to briefly recall the basic of operation with a strong focus on the major challenges that a designer faces at mm-Wave. The effect of scaling is also discussed, leading to simple design guidelines and establishing the foundation of the following chapters.
This chapter recalls filter basics and introduces design techniques to achieve gain-bandwidth enhancement and further approach the Bode-Fano limit. A strong focus is put on filter topologies that lead to relatively easy implementation with on-chip components and have shown state-of-the-art performance at mm-Wave.
This paper introduces a 2nd harmonic extraction technique and its implementation in a 46.4-58.1 GHz frequency synthesizer. The frequency doubling approach is based on tapping second harmonic signals at the VCO supply and tail nodes and amplifying them to provide a differential output. Since the amplifiers do not load the VCO outputs, the proposed technique does not affect either the tuning range or the frequency of the VCO. Moreover, a novel noise bypass technique is utilized to ensure that the amplifiers do not degrade the VCO phase noise. As a result, the frequency synthesizer achieves 22.4% tuning range (46.4-58.1 GHz) and phase noise below -118 dBc/Hz while consuming 66 mW from a 1 V supply. The stacked common gate amplifier can also be utilized for voltage regulation, providing a relatively constant FOM performance over a 2X power dissipation range. The synthesizer occupies 0.6 mm × 1 mm in IBM 32 nm SOI CMOS.
This paper discusses the design of on-chip transformer-based fourth order filters, suitable for mm-Wave highly sensitive broadband low-noise amplifiers (LNAs) and receivers (RXs) implemented in deep-scaled CMOS. Second order effects due to layout parasitics are analyzed and new design techniques are introduced to further enhance the gain-bandwidth product of this class of filters. The design and measurements of a broadband 28-nm bulk CMOS LNA and a sliding-IF RX tailored for E-band (i.e., 71-76-GHz and 81-86-GHz) point-to-point communication links are presented. Leveraging the proposed design methodologies, the E-band LNA achieves a figure of merit ≈10.5-dB better than state-of-the-art designs in the same band and comparable to LNAs at lower frequencies. The RX achieves 30.8-dB conversion gain with <;1-dB in-band ripple over a 27.5-GHz BW-3-dB while demonstrating a 7.3-dB minimum NF with less than 2-dB variation from 61.4 to 88.9-GHz. The worst cases in-band ICP
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-dB</sub>
and IIP3 are -30.7 and -23.8-dBm, respectively, from a 0.9-V power supply. This wideband state-of-the-art performance enables robust and low power multi-Gb/s wireless communication over short to medium distance over the complete E-band with wide margin.
A switched substrate-shield inductor (SSI) topology in bulk CMOS is proposed which minimizes parasitic capacitance and substrate losses, while tuned magnetically induced currents facilitate inductor tunability. The high frequency behavior of the induced current is analyzed, resulting in intuitive insights and design guidelines for a high-performance SSI. An SSI prototype in 65-nm bulk CMOS achieves 34% inductance tunability with a quality factor of >10.3. A voltage-controlled oscillator (VCO) using SSI achieves 40.3% tuning range, from 21 to 31.6 GHz, and a phase noise of -119.1 ± 3.7 dBc/Hz at 10-MHz offset frequencies. The VCO core consumes 4.3 ± 0.2 mW from a 1-V supply.
Integrated oscillators with octave frequency tuning range (FTR) are desirable for wireless transceivers supporting multiple frequency bands. In this paper, we describe a wide-FTR CMOS voltage-controlled oscillator (VCO) based on a novel area-efficient series resonator mode-switching scheme that preserves resonator quality factor Q across the entire octave tuning range. This allows the CMOS VCO to simultaneously achieving wide FTR, area efficiency, and low phase noise, demonstrating state-of-the-art figure of merit (FoM) for > 10-GHz octave-tuning range VCOs. We also analyze the relationship between Q and FTR across common resonator band-switching schemes, quantifying performance limits and highlighting the benefits of using mode-switching for wide-FTR VCOs. The proposed approach is demonstrated through a 6.4-14-GHz (74.6% FTR) VCO implemented in 65-nm CMOS that achieves 186-188-dB VCO FoM, demonstrating good FoM across the entire FTR. The scalability of this approach toward achieving even larger FTR is also demonstrated by a triple-mode 2.2-8.7-GHz (119% FTR) CMOS VCO. Area efficiency of the proposed mode-switching scheme is demonstrated by the state-of-the-art 197-dB FoM area achieved by the 14-GHz VCO.
In this paper, we propose a radio front end for future 5G mobile devices and present the design and verification of two fundamental voltage-controlled oscillators (VCO) working at potential 5G carrier frequencies. Based on two types of very small on-chip inductors with high quality factor, two LC-VCOs are fabricated and tested in a 130nm CMOS process. With a C-shaped on-chip inductor, VCO 1 achieves a frequency range from 25.23 to 27 GHz, while VCO 2 can be continuously tuned from 39.6 to 41.8 GHz by using a very small horseshoe-shaped on-chip inductor. The measured phase noise for VCO 1 and VCO 2 are −101.9 dBc/Hz and −94.8 dBc/Hz at 1 MHz frequency offset when working at 25.58 GHz and 41.81 GHz respectively, which correspond to FOM of −176.7 dBc/Hz and −172.1 dBc/Hz.
This paper reports a novel oscillator circuit topology based on a transformer-coupled π-network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root-locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed-form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer-coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright
Transceivers for wireless communications at millimeter-waves are becoming pervasive in several commercial fields. Taking advantage of a cut-off frequency of hundreds of GHz, CMOS technology is rapidly expanding from Radio Frequency to Millimeter-Waves, thus enabling low-cost compact solutions. The question we raise in this article is whether scaling is just providing advantages at mm-waves or not. We present experimental data of single devices, comparing 65 and 32 nm nodes in a wide-frequency range. In particular, switches used in VCOs for tank components tuning, MOM and AMOS capacitors, inductors. fT and fMAX increase though slower than in the past, ron*Coff, a figure of merit for switches, improves correspondingly. As a consequence, wide-band circuits benefit from scaling to 32 nm. As an example, a frequency divider-by-4, based on differential pairs used as dynamic latches, realized in both technology nodes and able to operate up to 108 GHz, is discussed. On the contrary, passive components do not improve and eventually degrade their performances. As a consequence, a conventional LC VCO, relying on tank quality factor, is not expected to improve. In this work we discuss a new topology for Voltage Controlled Oscillators, based on inductor splitting, showing low noise and wide tuning range in ultra-scaled nodes.
This paper presents an E-band quadrature voltage-controlled oscillator implemented in 28-nm CMOS. Two fundamental oscillators are coupled by means of gate-to-drain transformers to realize accurate quadrature phases and switched coupled inductors are added for tuning extension. Closed-form expressions of the oscillation frequency and the tuning extension design parameters are derived. The time-variant nature of the circuit noise to phase noise (PN) of the presented topology is investigated, resulting in simple design guidelines for optimal design. Based on the proposed techniques, the realized prototype is tunable over two bands of almost 5 GHz each separated in frequency, while occupying only 0.031 mm2. The peak measured PN at 10-MHz offset is −117.7 dBc/Hz from a 72.7-GHz carrier and −110 dBc/Hz from a 88.2-GHz carrier and varies less than 3.5 dB within each band.
A dual-band VCO (Voltage Controlled Oscillator) for automotive radar system is proposed by 65nm CMOS process. The proposed VCO is splitting inductor and NMOS cross-coupled differential LC type and includes output matching buffer. The output frequencies of VCO are 76.4∼77.1GHz and 78.5∼ 80GHz. These frequency bands are proper to long-range and short-range radar sensor system of automotive radar at W-band. The simulation results show the output power of-8.4dBm and the phase noise of-90.8dBc/Hz at 1MHz offset and-113.3dBc/Hz at 10MHz offset. The power consumption of the proposed VCO is 30mW at the supply voltage of 1.2V. The proposed VCO shows good figure of merit (FOM) of-176.6dBc/Hz.
A 28nm FDSOI CMOS low power VCO working at 40 GHz frequency is presented in this paper. The VCO core only consumes 6mW from a 1 V supply voltage. A wide tuning range of 18.5 % from 38.3 GHz to 46.1 GHz is reached with a tuning voltage from 0 to 1 V A phase noise higher than -120.5 dBc/Hz at 10 MHz offset has been observed after post-layout simulations. A variable inductance approach has been chosen in order to maintain a sufficiently low phase noise despite significant constraints caused by the advanced technology nodes and the large tuning range needed.
A magnetically-tuned multi-mode VCO featuring an ultra-wide frequency tuning range is presented. By changing the magnetic coupling coefficient between the primary and secondary coils in the transformer tank, the frequency tuning range of a dual-band VCO is greatly increased to continuously cover the whole E-band. Fabricated in a 65-nm CMOS process, the presented VCO measures a tuning range of 44.2% from 57.5 to 90.1 GHz while consuming 7mA to 9mA at 1.2V supply. The measured phase noises at 10MHz offset from carrier frequencies of 72.2, 80.5 and 90.1 GHz are -111.8, -108.9 and -105 dBc/Hz, respectively, which corresponds to a FOMT between -192.2 and -184.2dBc/Hz.
This work presents a 21.7-to-27.8GHz frequency synthesizer in a 45nm CMOS process that combines a tuning range of 24.8%, a residual phase modulation of 2.57°rms (with integrated phase noise from 100kHz to 100MHz), and a total power dissipation of 40mW. Combined with a frequency multiplier-by-two circuit and a divider-by-two circuit in a sliding-IF configuration, the PLL provides the four source frequencies required by the IEEE 802.15.3c 60GHz communication standard. In addition, the attained phase noise makes it suitable for microwave links with higher-order modulation schemes used as the back-bone for 3G/LTE base-station networks.
A wide-tuning CMOS quadrature VCO (QVCO) is presented that uses a transformer-coupled resonator that enables quadrature coupling and facilitates alternative tuning methods including mutual inductance switching, magnetic tuning, and dual resonance mode switching besides the conventional capacitor tuning. The QVCO, fabricated in 130nm CMOS, can generate quadrature signals in the frequency range of 11.56-18.1 GHz and 18.9-22 GHz. The phase noise was measured -107dBc/Hz at 1MHz offset from 13.3GHz. The QVCO consumes 20-29mW and the output buffers consume 21mW from a 1.2V supply.
With dramatically increased f<sub>t</sub> and f<sub>max</sub>, CMOS technologies have been widely applied in the design of millimeterwave circuits. To reduce the fabrication cost, digital CMOS processes may be used. Due to the lack of thick top metal and the reduced distance between the top metal and silicon substrates in a digital CMOS, the design of high-performance passives becomes very challenging, particularly in the millimeter-wave frequency regime. In this letter, passives with novel structures were fabricated in a 45-nm digital CMOS process. These passives, including transmission lines, spiral inductors, and metal-oxide-metal (MOM) capacitors, were designed and characterized up to 110 GHz. Their performance was compared with those fabricated using 180- and 90-nm RF CMOS processes. These passives achieved good performance in the millimeter-wave regime. A MOM capacitor has a self-resonant frequency higher than 110 GHz. An inductor achieves a quality factor of 24 at 70 GHz. These results show the feasibility of implementing the millimeterwave passives and systems in a 45-nm digital CMOS process.
A 34-40 GHz VCO fabricated in 65 nm digital CMOS technology is demonstrated in this paper. The VCO uses a combination of switched capacitors and varactors for tuning and has a maximum Kvco of 240 MHz/V. It exhibits a phase noise of better than -98 dBc/Hz @ 1-MHz offset across the band while consuming 12 mA from a 1.2-V supply, an FOM<sub>T</sub> of -182.1 dBc/Hz. A cascode buffer following the VCO consumes 11 mA to deliver 0 dBm LO signal to a 50Ω load.