ArticlePDF Available

Slew-rate-enhanced rail-to-rail buffer amplifier for TFT LCD data drivers

Wiley
Electronics Letters
Authors:
Jong-Seok Kim at Hanyang University
Jong-Seok Kim
J.Y. Lee
J.Y. Lee
J.Y. Lee
  • This person is not on ResearchGate, or hasn't claimed this research yet.
B.D. Choi
B.D. Choi
B.D. Choi
  • This person is not on ResearchGate, or hasn't claimed this research yet.
Download full-text PDF
Read full-text
Download citation

Abstract

A high-slew-rate low-power rail-to-rail buffer amplifier, which is suitable for thin film transistor liquid crystal display (TFT LCD) data driver applications, is proposed. Previous dynamic biasing approaches become ineffective as an output signal approaches VDD or VSS supplies. However, the proposed buffer amplifier with a dynamic biasing circuit enhances the slew rate throughout the entire rail-to-rail signal range. The buffer amplifier and the previous counterparts were fabricated in a 0.35 μm CMOS technology with 3.3 V supply voltage. Measurements show that the slew rate for rail-to-rail signal transition is enhanced from 0.80 V/μs of a previous counterpart to 2.75 V/μs.
Content uploaded by Jong-Seok Kim
Author content
All content in this area was uploaded by Jong-Seok Kim on Jan 12, 2016
Content may be subject to copyright.
Slew-rate-enhanced rail-to-rail buffer
amplifier for TFT LCD data drivers
J.S. Kim, J.Y. Lee and B.D. Choi
A high-slew-rate low-power rail-to-rail buffer amplifier, which is suit-
able for thin film transistor liquid crystal display (TFT LCD) data driver
applications, is proposed. Previous dynamic biasing approaches
become ineffective as an output signal approaches VDD or VSS
supplies. However, the proposed buffer amplifier with a dynamic
biasing circuit enhances the slew rate throughout the entire rail-to-rail
signal range. The buffer amplifier and the previous counterparts were
fabricated in a 0.35 mm CMOS technology with 3.3 V supply
voltage. Measurements show that the slew rate for rail-to-rail signal
transition is enhanced from 0.80 V/ms of a previous counterpart to
2.75 V/ms.
Introduction: Higher resolution and frame frequency are required on
thin film transistor liquid crystal displays (TFT LCDs) for natural
motion picture and three-dimensional displays. The frame frequency
should be elevated from typically 60 to 480 Hz [1]. Consequently, the
driving time for each row must be decreased inverse proportionally,
and TFT LCD data drivers should be equipped with high-slew-rate
buffer amplifiers to accommodate the need for decreased driving time.
In addition, data drivers should have the rail-to-rail input range to
cover the liquid crystal driving voltage and also have the push-pull
output stage to support N-dot polarity inversion driving for high
image quality and low power consumption [2]. The rail-to-rail folded-
cascode class-AB amplifier in [3] is widely used to meet these
requirements.
Several buffer amplifiers for TFT LCD data drivers have been pro-
posed to enhance the slew rate with minimal increase in the quiescent
current [4– 7].In[4], the buffer amplifier uses comparators to sense
the slewing conditions, but it does not support the push-pull operation.
In [5], an additional current path is inserted, but the circuit requires a
clock signal, which increases the circuit complexity and power con-
sumption. The dynamic biasing circuits in [6] and [7] detect the
slewing conditions and turn on the auxiliary current sources. The
enhancement of the slew rate, however, ceases when the output
voltage approaches VDD or VSS, which degrades the overall slew rate
for the rail-to-rail signal swings. In this Letter, we propose a buffer
amplifier for a TFT LCD data driver with a dynamic current biasing
circuit that enhances the slew rate in the entire rail-to-rail signal range.
Limitations in dynamic biasing for slew rate enhancement: Fig. 1
shows a high-slew-rate amplifier with the dynamic biasing circuit [6].
At steady state, where V
IP
and V
IN
have the same voltage, M11 and
M12 are put in the triode region by appropriately sizing M11 and
M12 to turn off M13 and M14. In the transition state, all of the tail
current, IP, flows either through M9 or M10, which puts either M11
or M12 in the saturation region and turns on the dynamic current
source composed of M13 and M14. This transitional increase in the
tail current enhances the slew rate of the core amplifier.
VDD
IP
VIN VIP VIN VOUT
IN
IADD
VIP
VB
M10
M9
M5
M3
M1 M2
M8
M4
M6
M11 M12 M13
dynamic biasin
g
circuit core amplifier
M14
M7
Fig. 1 Slew-rate-enhanced amplifier with dynamic biasing circuit in [6]
In [7], as shown in Fig. 2, the concept of the dynamic biasing circuit
in [6] is applied to the buffer amplifier in [3] which is well suited for
TFT LCDs. Both dynamic current sources formed with the pairs of
M27, M28 and M29, M30, respectively, are used to support push-pull
operation. However, this slew-rate enhancement technique does not
fully function throughout the entire rail-to-rail signal range. For
example, when the input voltage in Fig. 2 at V
IP
rises from 0.3 to
3.0 V with 3.3 V supply voltage, M23 and M24 act as a slew detector
and add an extra current for M1 and M2 by turning on M29.
However, as the output voltage approaches 3.0 V, M23 and M24 are
turned off and stop working as a slew detector. A similar problem is
also observed when the input voltage falls from 3.0 to 0.3 V. This behav-
iour is especially pronounced in a high-to-high signal transition, for
example, 2.9 to 3.1 V, because M23 and M24 are turned off for the
signal. Similarly, behaviour is observed for a low-to-low signal tran-
sition. High-to-high or low-to-low signal transitions are indispensable
for N-dot inversion driving for high-image-quality and low-power
TFT LCDs [2].
VDD
VBP3
IN2
IP2
VIP VIN
IN1
Cc
VBP1
VOUT
VBN1
VBP2
IP1
VIP
VBN2
Cc
IADD,N
IADD,P
VBN3
VIN
M21
M19
M23 M24 M4 M3
VDD
VSS
M25 M26 M29 M30
VSS
VDD
M20
M2 M1 M7 M8
M9
M5 M6
M17
M10
M11
M14
M13 M18
M16
M15
core amplifierdynamic biasing circuit
M22 M27 M28
Fig. 2 Slew-rate-enhanced amplifier with dynamic biasing circuit in [7]
Proposed rail-to-rail slew-rate enhancement: The slew-rate enhance-
ment limited in the previous circuits in Figs 1 and 2originates in the
fact that the rise slewing is detected by PMOS transistors and the fall
slewing by NMOS transistors. The approach we employ to resolve
this problem uses NMOS and PMOS transistors in the construction of
the rise and fall slew detectors, respectively. The proposed amplifier
with an improved dynamic biasing circuit is shown in Fig. 3, where
the pairs of M19, M20 and M31, M32 form the rise and fall slew
detectors.
VDD
VBP3
VIN VIP
IADD,N
VIN
IN1 VIP
IP1
VBN2
Cc
Cc
VBP1
VBP2
VOUT
VBN1
IADD,P
IN2
IP2
VBN3
M39 M40M21 M22 M23 M41 M42
M24
M20
VSS
VDD
M37 M38
M25 M26
M32
M31
M35
M33
M36 M34
M27 M28 M29 M30
M4 M3
VDD
VSS
M2 M1 M7
M5 M6
M8
M10 M17
M11
M14
M13
M9
M18
M16
M15
M12
M19
core amplifierdynamic biasing circuit
Fig. 3 Proposed buffer amplifier with slew-rate enhancement throughout
entire rail-to-rail signal range
The rise slew rate is enhanced as follows. At steady state, the dynamic
biasing circuit does not affect the core amplifier. Because V
IP
and V
IN
have the same voltage, which puts M27, M28, M39 and M40 in the
triode region by appropriately sizing them, M29, M30, M41 and M42
are turned off. However, when the circuit enters the slewing state on a
sufficiently large rising step input at V
IP
, almost all of the tail current,
I
N2
, flows through M20, which is copied by M24, then M28 enters
the saturation region. Thus, the drain voltage of M28 becomes suffi-
ciently high to turn on M29, which enhances the slew rate by adding
the tail current for M1 and M2. For a falling step input signal, the
slew-rate enhancement is achieved in the same manner. M31 and M32
operate as a slew detector and enhance the slew rate by adding the tail
current for M3 and M4.
While this dynamic current source is based on those in [6] and [7],a
critical advantage of this design is provided by the rise and fall slew
detectors that employ NMOS (M19 and M20) and PMOS (M31 and
M32) transistors, respectively. Thus, unlike previous designs, the slew
detectors remain turned on even when the signals approach VDD or
VSS, and the slew rate is enhanced throughout the entire rail-to-rail
signal range.
Experimental results: The proposed buffer amplifier was fabricated in a
0.35 mm CMOS technology with 3.3 V supply. The amplifiers in [3]
and [7] were also fabricated on the same wafer for comparison purposes.
Fig. 4 shows the measured output waveforms of the amplifiers with
200 pF load capacitance. In Fig. 4a, the slew rate of [7] is enhanced
ELECTRONICS LETTERS 19th July 2012 Vol. 48 No. 15
compared with that of [3], but it becomes ineffective when the rising
signal reaches approximately 1 V below the VDD or the falling signal
reaches approximately 1 V above the VSS. In the proposed circuit, the
slew rate is enhanced throughout almost the entire rail-to-rail signal
range. The impact of the proposed circuit is more remarkable in
Figs 4band c. When the signal transits near VDD or VSS, slew-rate
enhancement is not observed with the circuit in [7], but the proposed
circuit obviously enhances the slew rate. In Fig. 4a, the overall slew
rate from VSS to VDD of the proposed circuit is enhanced from
0.49 V/
m
sin[3] and 0.80 V/
m
sin[7] to 2.75 V/
m
s. The quiescent
current of the proposed circuit is negligibly increased compared to
that of [7]. The quiescent current of the folded-cascode amplifier in
[3] ranges from 4.0 to 4.6 mA depending on the input common mode
voltage, and those of [7] and the proposed circuit are 4.3 to 5.1 mA
and 4.7 to 5.8 mA, respectively.
3
proposed
proposed
proposed
0V
2.5V
0V
2.5V
3.3V proposed
[3]
[7]
proposed
[3]
[7]
proposed
[3]
[7]
[7]
[7]
[7] [3]
0.8V
[3]
[3]
2ms
2ms
2ms
500mV
500mV
500mV
2
1
VOUT, v
0
3
2
1
VOUT, v
0
3
2
1
VOUT, v
0
024
3.3V
6810
a
b
c
12 14 16 18
0V
0 2 4 6 8 10 12 14 16 18
0246810
time, ms
12
0V
14 16 18
Fig. 4 Measured output waveforms from fabricated buffer amplifiers
aFrom VSS to VDD
bNear VDD
cNear VSS
Conclusion: A slew-rate-enhanced rail-to-rail buffer amplifier, which is
suitable for TFT LCD data drivers, is proposed. Unlike previous
counterparts, the slew rate is enhanced throughout the entire rail-to-
rail signal range. The measured slew rate from VSS to VDD of the pro-
posed circuit is enhanced from 0.49 V/
m
sin[3] and 0.80 V/
m
sin[7] to
2.75 V/
m
s with 200 pF load capacitance. The increase in the quiescent
current is negligible.
Acknowledgment: This work was supported by a National Research
Foundation of Korea grant funded by the Korean Government (NRF-
2011-013-D00077)
#The Institution of Engineering and Technology 2012
31 March 2012
doi: 10.1049/el.2012.0438
One or more of the Figures in this Letter are available in colour online.
J.S. Kim, J.Y. Lee and B.D. Choi (Department of Electronic
Engineering, Hanyang University, 222 Wangshimniro, Seongdong-gu,
Seoul 133-791, Republic of Korea)
E-mail: bdchoi@hanyang.ac.kr
References
1 Kim, Y.M., Hahn, J., Kim, Y.H., Kim, J.H., Park, G.B., Min, S.W., and
Lee, B.G.: ‘A directional-view and sound system using a tracking
method’, IEEE Trans. Broadcast., 2011, 57, (2), pp. 454–461
2 Son, Y.S., Kim, J.H., Cho, H.H., Hong, J.P., Na, J.H., Kim, D.S., Han,
D.K., Hong, J.C., Jeon, Y.J., and Cho, G.H.: ‘A column driver with
low-power area-efficient push-pull buffer amplifiers for active-matrix
LCDs’. ISSCC Proc., San Francisco, CA, USA, 2007, pp. 142– 143
3 Hogervosrst, R., and Huijsing, J.H.: ‘Design of low-voltage, low-power
operational amplifier cells’ (Kluwer Academic, Dordrecht, The
Netherlands, 1996)
4 Lu, C.W., and Hsu, K.J.: ‘A high-speed low-power rail-to-rail column
driver for AMLCD application’, IEEE J. Solid-State Circuits, 2004,
39, (8), pp. 1313– 1320
5 Choi, Y.K., Lee, J.B., Park, S.J., Ku, Y.K., Kim, H.R., Kim, J.S., Kim,
B.N., and Kim, J.T.: ‘A lower power slew rate enhancement method
for the mobile TFT source driver amplifier’, SID Symp. Dig., 2005, 36,
(1), pp. 447–449
6 Klinke, R., Hosticka, B.J., and Pfleiderer, H.J.: ‘A very-high-slew-rate
CMOS operational amplifier’, IEEE J. Solid-State Circuits, 1989, 24,
(3), pp. 744–746
7 Choi, J.Y., Min, K.Y., and Yoo, C.S.: ‘High-speed and low-power analog
source driver for TFT-LCD using dynamic current biased operational
amplifier’, SID Symp. Dig., 2007, 38, (2), pp. 1647– 1650
ELECTRONICS LETTERS 19th July 2012 Vol. 48 No. 15
... Moreover, the dot inversion method typically requires explicit components such as polarity multiplexer switches to alternate the LC polarity, which can degrade the panel driving speed. Actually, in the FPD column driver, the time for panel driving is critical since it must not exceed the horizontal scanning pattern time [19][20][21][22][23][24][25][26]. ...
... To satisfy these requirements, class AB or B amplifiers [18][19][20][21][22][23][24][25][26] have been widely used as output buffer amplifiers in FPDs. In this case, there can be numerous issues concerning explicit switch on-resistance, high-slew-rate amplifier design, adaptive biasing circuit design, and the resulting overheads in terms of area and power consumption. ...
... Thus, the power consumption increases as the bias current increases to provide a higher slew-rate. The class AB amplifiers with various adaptive biasing schemes have been proposed to improve the slew-rate without having a large input bias current [21,22,26]. In [21,22], the settling time is reduced but the circuit for implementing the adaptive biasing requires so many transistors, resulting in increased power consumption and chip area. ...
High-Speed Column Driver IC Having Buffer Amplifier with Embedded Isolation Switch and Compact Adaptive Biasing for Flat-Panel Displays
Article
Full-text available
  • Sep 2021
A high-speed column driver IC with an area-efficient high-slew-rate buffer amplifier is proposed for use in a large-sized, high-resolution TFT-LCD panel application. In the proposed architecture, explicit isolation switches have been embedded into the buffer amplifier resulting in a fast settling response. The amplifier also has a structure that adjusts the tail current of the input stage using a very compact adaptive biasing. The proposed column driver IC, having the proposed buffer amplifier for driving a 55-inch 4K ultra-high-definition (UHD) TV panel, was fabricated in a 0.18-μm 1.8-V low-voltage, 1.2-μm 9-V medium-voltage, and 1.6-μm 18-V high-voltage CMOS process. The performance evaluation results indicated that 90% and 99.9% falling settling times were improved from 1.947 µs to 0.710 µs (63.5% improvement) and 4.131 µs to 2.406 µs (41.7% improvement), respectively. They also indicated that the layout size of the proposed buffer amplifier was reduced from 5580 μm2 to 4402 μm2 (21.1% reduction).
View
... A column driver of a FPD panel generally includes shift registers, input registers, data latches, level shifters, digital-to-analog converters (DACs) and output buffers with output switches [1][2][3][4][5][6][7][8][9][10]. FPD driving systems generally use analog [11][12][13][14][15][16][17][18][19] or digital driving methods [20,21]. As the display resolution increases, the resistance and capacitance loads of the output buffer increase, whereas the required settling time decreases. ...
... As the display resolution increases, the resistance and capacitance loads of the output buffer increase, whereas the required settling time decreases. The target settling time of the output buffer for the LCD column drivers should be shorter than the horizontal scanning time of the panel [11,12,[14][15][16][17][18][19]. Rail-to-rail class-A, AB or B amplifiers described in [11][12][13][14][15][16][17][18][19] have been generally used as buffer amplifiers of FPD column drivers. ...
... The target settling time of the output buffer for the LCD column drivers should be shorter than the horizontal scanning time of the panel [11,12,[14][15][16][17][18][19]. Rail-to-rail class-A, AB or B amplifiers described in [11][12][13][14][15][16][17][18][19] have been generally used as buffer amplifiers of FPD column drivers. The output buffer amplifier in [11] is used a rail-to-rail input stage and a dual-path push-pull output stage with both class-B and class-AB output sections combined together to improve slew rate. ...
High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications
Article
Full-text available
  • Nov 2020
A high-slew-rate, low-power, CMOS, rail-to-rail buffer amplifier for large flat-panel-display (FPD) applications is proposed. The major circuit of the output buffer is a rail-to-rail, folded-cascode, class-AB amplifier which can control the tail current source using a compact, novel, adaptive biasing scheme. The proposed output buffer amplifier enhances the slew rate throughout the entire rail-to-rail input signal range. To obtain a high slew rate and low power consumption without increasing the static current, the tail current source of the adaptive biasing generates extra current during the transition time of the output buffer amplifier. A column driver IC incorporating the proposed buffer amplifier was fabricated in a 1.6-μm 18-V CMOS technology, whose evaluation results indicated that the static current was reduced by up to 39.2% when providing an identical settling time. The proposed amplifier also achieved up to 49.1% (90% falling) and 19.9 % (99.9% falling) improvements in terms of settling time for almost the same static current drawn and active area occupied.
View
... [4][5][6] dedicating to I/Os between different voltage domains, for example, chip-to-chip I/Os between 0.9 and 1.8 V supply, limit the maximum speed of the drivers due to the introduction of extra loading by the feedback paths. To avoid the closed-loop SR detection and control, an open-loop SR control is preferred [7][8][9][10][11][12][13], which usually employs an independent PVT detector to control the SR of the driver without any extra loading at the output node. A SR output driver for the ultra direct memory access (UDMA100) is introduced in ref. [7]. ...
A CMOS slew‐rate controlled output driver with low process, voltage and temperature variations using a dual‐path signal‐superposition technique
Article
Full-text available
A dual‐path open‐loop slew‐rate (SR) controlled Complementary Metal Oxide Semiconductor (CMOS) driver is presented in this study. The proposed output driver incorporates a delay‐locked loop (DLL) to minimise the SR variations over process, voltage and temperature, generating delayed versions of transmitted signal by sampling the input data with adjacent phases of the clock from the DLL. A dual‐path open‐loop signal‐superposition technique is introduced to suppress the high‐frequency components of the output driver and thus improves the SR of the CMOS driver. The proposed CMOS output driver achieves a maximum SR of 1.00 and <0.35 V/ns variation operating at 500 Mbps over 32 corners. Both the conventional CMOS driver and the proposed SR controlled output driver were fabricated in a 0.18 μm CMOS process. The proposed driver occupies a compact area of 0.088 mm² and consumes 55.27 mW with a 1.8 V supply voltage. Measurement results show that the SR of the proposed output driver is <0.816 V/ns, corresponding to 62% reduction compared with that of a conventional output driver, and the total jitter is <0.16 unit interval.
View
... Researchers proposed output buffers with a floating current source structure, which are widely used in display drivers due to their low tail current and high stability [7][8][9]. However, the stability and slew rate constrain each other, and the high speed and low power cannot be achieved at the same time. ...
High-Speed Low-Power Rail-to-Rail Buffer using Dynamic-Current Feedback for OLED Source Driver Applications
Article
Full-text available
  • Jan 2022
  • ANALOG INTEGR CIRC S
In this work, we propose a rail-to-rail output buffer with low static-power and high speed for OLED display applications. To guarantee low static power consumption, low tail-current is designed in the buffer’s first stage and the output stage is cut off in the static operation. To improve the transient response, dynamic-current-bias technique is used, and it also improves the system stability by pushing away the non-dominant pole. Meanwhile, we balance the large-signal slew-rate and system stability with dual-output buffer structure. Placing compensation resistor across the dual outputs creates zero for suitable phase margin, while the real output still behaves with low ON resistance and keeps high slew rate. The proposed design has been verified by a 0.18 μm 1.8 V/5 V CMOS process, which shows that the buffer only draws 2.8-μA static current. Under a 1-nF capacitance load and a 5-V power supply, the buffer achieves 1.18-μs settling time, which is only 41% of the single-output-stage structure with the same chip size (52 μm ×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} 59 μm).
View
View
A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer
Article
  • Apr 2024
This article presents an area-efficient 10-bit source-driver IC (SD-IC) for mobile displays. Addressing the challenge of exponential die area growth associated with higher digital-to-analog converter (DAC) resolution dominating color depth, we propose a three-stage-cascading interpolation design solution. In the first stage, a two-output voltage selector selects adjacent voltages from the global resistor string. The proposed overlap-switch merging (OSM) technique reduces its size by two times compared to conventional two-output selectors. The second-stage interpolation employs a successive-approximation-register (SAR)-interpolating switched-capacitor (SI-SC) DAC, enhanced with bit-adaptive switch-size (BASS) modulation to minimize the switching errors. The proposed SI-SC DAC also features an intrinsic two-output design for further interpolation in the subsequent stage. In the last (third) stage, a super-class-AB operational transconductance amplifier (OTA)-based buffer amplifier performs accurate 1-bit true-dc interpolation with no overhead while driving the final output with a fast slew rate. The prototype chip was fabricated in a 180-nm 1.8/5-V CMOS process. The maximum differential nonlinearity (DNL) and integral nonlinearity (INL) were measured to be $-$ 0.37 and 1.17 LSB, respectively, in a 10-bit resolution. The maximum deviation of voltage outputs (DVOs) achieved was 15.5 mV. The proposed chip exhibits a source channel size of 2211 $\mu$ m $^{{2}}$ , which is the smallest reported to date, along with a competitive slew rate of 44 V/ $\mu$ s measured at $C_{\text{Load}}$ $=$ 100 pF.
View
An Area-Efficient 10-Bit Source-Driver IC With LSB-Stacked LV-to-HV-Amplify DAC for Mobile OLED Displays
Article
  • Nov 2023
This article presents an ultra-compact 10-bit source driver IC (SD-IC) developed for mobile organic light-emitting diode (OLED) displays. The proposed LSB-stacked low-voltage (LV)-to-high-voltage (HV)-amplify digital-to-analog converter (DAC) allows the area-consuming 8-bit voltage selector to be implemented with compact LV transistors (LV-MOS) as well as obtains an additional DAC resolution of 2-bit by dissipating little die area. By virtue of the LV-MOS voltage selector, level-shifters (L/S) can also be eliminated, further lowering the column channel size. In addition to its compactness, the proposed SD-IC merits a high uniformity attained from a mismatch-insensitive switched-capacitor (SC) 4 $\times$ -multiplier and a globally sampled 2-bit stack-up voltage. A technique to elaborately cancel the offset of the buffer amplifier is also included in this work. The prototype 600-channel SD-IC was fabricated in a 130-nm 1.5/5-V CMOS technology. The maximum differential nonlinearity (DNL) and integral nonlinearity (INL) were measured to be $-$ 0.39 and 0.9 LSB, respectively, with a 1-LSB voltage of 4.1 mV. An achieved deviation of voltage outputs (DVOs) was 4.82 mV, which is low enough to be comparable to the 1-LSB voltage. The proposed 10-bit channel size of 2688 $\mu\text{m}^2$ is a 65.2% reduction in comparison to conventional 8-bit SD-IC.
View
View
View
A rail-to-rail CMOS amplifier with improved current efficiency for MEMS geophone applications
Article
  • Jul 2021
  • AEU-INT J ELECTRON C
In this study, a two-stage rail-to-rail amplifier with improved current efficiency is presented for microelectric mechanical system (MEMS) geophone applications, when operating in the saturated region. With the proposed recycling current method in the input stage, the amplifier gains improved unity-gain bandwidth (GBW) and DC gain with little power consumption. Based on the SMIC 180 nm process, the simulation results demonstrate that the proposed amplifier achieves rail-to-rail input/output, 92 dB DC gain and 4.8 MHz GBW with 1.2 V supply voltage.
View
A Column Driver with Low-Power Area-Efficient Push-Pull Buffer Amplifiers for Active-Matrix LCDs
Conference Paper
Full-text available
  • Mar 2007
Push-pull buffer amplifiers are operated in a transient mode for column drivers suitable for vertical N-dot inversion of an active-matrix LCD (AMLCD) image. Each channel has a static current draw of 3.8 muA and an area of 4773 mum<sup>2</sup>. The functionality of the column driver with 720 outputs is fully evaluated on the AMLCD module. The chip size of 23.2mm<sup>2</sup> is achieved in a 0.35 mum 13.5V CMOS process.
View
P-46: A Low Power Slew Rate Enhancement Method For the Mobile TFT Source Driver Amplifier
Article
  • May 2005
To increase slew rate of the source driver amplifier more bias current is needed in general. But this means shorter battery life. A new slew rate enhancement method that switches the compensation capacitor is proposed. By using it several times higher slew rate can be obtained without increasing bias current.
View
56.5: High-Speed and Low-Power Analog Source Driver for TFT-LCD Using Dynamic Current Biased Operational Amplifier
Article
  • May 2007
This paper describes high-speed and low-power analog source driver built with operational amplifier (OPAMP) for driving large resistive and capacitive load of TFT-LCD panel. To obtain large slew-rate without increasing quiescent current, dynamic current biasing scheme is developed. The dynamic current bias circuit operates as auxiliary current source and supplies or sinks large amount of current only when the OPAMP is slewing. The analog source driver is implemented in a 0.35μm CMOS process, and for 20KΩ and 200pF data-line loading of 30-inch TFT-LCD panel, the settling time is 7.2μs and 6.4μs respectively for rising and falling while the quiescent current is only 5∼6.5μA.
View
View
Design of low-voltage low-power CMOS operational amplifier cells /
Book
  • Jan 1996
Thesis (doctoral)--Technische Universiteit Delft, 1996. Includes bibliographical references.
View
View
Low-power low-voltage VLSI operational amplifier cells
Conference Paper
  • Feb 1996
VLSI operational amplifier cells that approach the physical limitations of bandwidth, gain and power consumption are here described. To this purpose several HF compensation architectures are presented, such as parallel, Miller, multipath nested Miller, and multipath hybrid nested Miller
View
A high-speed low-power rail-to-rail column driver for AMLCD application
Article
  • Sep 2004
A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-μm CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 μs and 1.4 μs for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 μA for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.
View
A Very-High-Slew-Rate Cmos Operational Amplifier
Article
  • Jul 1989
The amplifier uses a circuit to inject an extra bias current into a conventional source-coupled CMOS differential input stage in the presence of large differential input signals. This measure substantially increases the slew rate of an operational amplifier for a given quiescent current. The performance of the amplifier is compared to a conventional operational amplifier when used in a sample-and-hold circuit. The maximum operating clock frequency of the sample-and-hold increases from 290 kHz to 1 MHz with a hold capacitor of 1 nF. The amplifier has been fabricated in a 5-μm CMOS process and dissipates a static power of 7.5 mW
View
A column driver with low-power area-efficient push-pull buffer amplifiers for active-matrix LCDs
  • Jan 2007
  • 142-143
  • Y S Son
  • J H Kim
  • H H Cho
  • J P Hong
  • J H Na
  • D S Kim
  • D K Han
  • J C Hong
  • Y J Jeon
  • G H Cho
Son, Y.S., Kim, J.H., Cho, H.H., Hong, J.P., Na, J.H., Kim, D.S., Han, D.K., Hong, J.C., Jeon, Y.J., and Cho, G.H.: 'A column driver with low-power area-efficient push-pull buffer amplifiers for active-matrix LCDs'. ISSCC Proc., San Francisco, CA, USA, 2007, pp. 142-143