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Hindawi Publishing Corporation
International Journal of Microwave Science and Technology
Volume 2011, Article ID 452348, 16 pages
doi:10.1155/2011/452348
Research Article
Scalable RFCMOS Model for 90 nm Technology
Ah Fatt Tong,1We i Meng L i m, 1Choon Beng Sia,2
Xiaopeng Yu,3Wanlan Yang,1andKiatSengYeo
1
1School of EEE, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798
2Cascade Microtech Inc., Singapore Science Park II, Singapore 117586
3Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
Correspondence should be addressed to Wei Meng Lim, wmlim@ntu.edu.sg
Received 30 May 2011; Revised 8 September 2011; Accepted 12 September 2011
Academic Editor: Mattia Borgarino
Copyright © 2011 Ah Fatt Tong et al. This is an open access article distributed under the Creative Commons Attribution License,
which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
This paper presents the formation of the parasitic components that exist in the RF MOSFET structure during its high-frequency
operation. The parasitic components are extracted from the transistor’s S-parameter measurement, and its geometry dependence
is studied with respect to its layout structure. Physical geometry equations are proposed to represent these parasitic components,
and by implementing them into the RF model, a scalable RFCMOS model, that is, valid up to 49.85 GHz is demonstrated. A new
verification technique is proposed to verify the quality of the developed scalable RFCMOS model. The proposed technique can
shorten the verification time of the scalable RFCMOS model and ensure that the coded scalable model file is error-free and thus
more reliable to use.
1. Introduction
The relentless scaling down of CMOS technologies has
greatly improved the RF performance of MOSFET. It has
been reported that for a technology node of 90 nm, high ftof
209 GHz and fmax of 248 GHz are achieved [1]. Furthermore,
the scaling down of the transistor has brought about lower
NFmin, and it is now comparable to the reported SiGe
BJT process [1,2]. The improved RFCMOS performance
coupled with its lower cost has motivated circuit designers to
integrate digital, mixed-signal, and RF transceiver blocks into
a single chip [3–7]. However, for these RF chips to operate at
higher-frequency region, the circuit design specifications will
become more stringent, and this will require accurate and
scalable RFCMOS models that can be simulated accurately at
high-frequency region. Furthermore, by employing scalable
RF CMOS model into the process design kit (PDK), the
circuit design environment is improved, and this can help
circuit designers in their circuit optimization and shorten the
design cycle and time to market of these RF chips.
Most of the RF models developed today are based on the
macromodelling approach. In this approach, subcircuit com-
ponents are added to the transistor’s core model to model
the RF parasitic of MOSFET structure [8,9], and the core
model used is usually the commercially available models
such as BSIM3v3 [10] and BSIM4 [11]. The subcircuit com-
ponents are extracted from the measured S-parameters of
the transistor, but the extracted values of these RF com-
ponents can differ when different extraction technique is
used. All the existing RF parameter extraction technique
is based on the transistor’s small-signal equivalent circuit
analysis. Therefore, to characterize an RF MOSFET, all its
RF parasitic elements must be included into the small-signal
equivalent circuit. Although it has been demonstrated that
including the subcircuit components into the core model
can accurately simulate for the transistor’s RF characteristics,
such developed model is normal for discrete transistor sizes.
In order to generate a geometry-scalable RFCMOS model,
the extracted subcircuit component values must be studied
for its geometry dependency and by formulating equations
to capture their physical effects at high-frequency region,
and a physical scalable RFCMOS model can be generated.
Presently, some publications are reported for the scalable RF
MOSFET modelling [12–14], but these publications [12,14]
do not show all the geometry-scalable equations of the
subcircuit components. In [13], the formulated equations
2 International Journal of Microwave Science and Technology
Gate
(node 2)
Rgate
Rd
Cgd ext
Cgs ext
Rsub3
Rsub1
Djsb
Djsb perim
Rsub2
Djdb
Djdb perim
Drain
(node 1)
Source
(node 3)
Body
(node 4)
Body
(node 4)
Csd
BS IM
core
Csubg
Rsubg
Rs
Figure 1: RF equivalent subcircuit model.
for the subcircuit components were empirical and have no
physical meaning, and furthermore, only one device size of
ftand fmax plot is presented.
In this paper, the geometry dependencies of the RF sub-
circuit components were studied, and the formulation of
these RF components was done based on their physi-
cal effects and the geometry of the layout structure. The
scalable transistor’s RF characteristics with respect to the lay-
out geometry, biasing, and frequency will be demonstrated
with good accuracy between the measured and simulated
results. Presently, there is no standard technique proposed
for quantifying the quality of a developed scalable RF model.
Hence, a new technique is proposed in this paper to help
modelling engineers to verify and check the developed scal-
able RF model for their scalability and accuracy. By utilizing
this proposed technique, the model geometry scalability
with respect to the transistor’s unit width (Wf)andfinger
number (Nf) is monitored to ensure that the formulated
geometry equations are correct. Furthermore, by plotting
the proposed accuracy plots, the error population of the
developed model is monitored and ensured that they are
below the error’s specification of the developed model. The
scalable RF model was developed for 90 nm process with
channel length of 70 nm for a frequency range of 50 MHz
to 49.85 GHz. The devices under test (DUT) are NMOS
transistors with Nfof 4, 8, 16, 24, 32, 48, and 64 and Wfof 1,
2.5, and 5 μm. By studying the geometry dependence of the
RF subcircuit components for the above DUT, the physical
geometry equations with fabrication process parameters are
formulated, and from the comparison between the extracted
and calculated component values, excellent agreement for all
the above combinations of Nfand Wfis shown.
Section 2 shows the transistor’s equivalent subcircuit
model and the layout of the DUT used. The detailed expla-
nation on the formulation of the equation for the sub-
circuit components is then shown, and the plots to com-
pare between the calculated and extracted component values
are presented. In Section 3, the good fitting between the
measured and simulated DC and RF results for the various
geometry combinations is shown, and the further verifica-
tion with the proposed technique for the generated scalable
RFCMOS model is presented. The conclusion follows in
Section 4.
2. Scalable RF MOSFET Modelling
Figure 1 shows the proposed RF equivalent subcircuit model.
All the subcircuit components are physical and can be used
for transistor that has the source and body terminal tied
together and grounded.
The resistance Rgate represents the effective lumped gate
resistance that consists of both the electrode resistance and
the distributed channel resistance [15]. The resistances Rs
and Rdrepresent the effective source and drain resistance that
consist of the metal line, via, and contact resistances.
International Journal of Microwave Science and Technology 3
Gate contact portion 2MT
Source 1MT
Dummy
gate and source
Drain 3MT
P-wel l
contact
Figure 2: Simplified RF NMOS layout.
The capacitances Cgs ext and Cgd ext represent the effective
gate-to-source and gate-to-drain capacitances and consist
of both the overlap and fringing capacitances between the
terminals. Cds represents the drain-to-source fringing capac-
itance between the metal lines that connect to the source and
drain diffusions. As the internal junction capacitances of the
core model are turned off, the external diodes Djdb,Djdb perim,
Djsb,andDjsb perim are added as the junction capacitances
to connect the substrate resistance network. Djdb stands for
the area intensive diode, while the Djdb perim stands for the
perimeter intensive diode, and the definition is the same for
the source-to-body junction diodes. The parameters Rsub1,
Rsub2,andRsub3 represent the substrate network resistances.
Finally, Csubg and Rsubg are defined as the gate-to-substrate
capacitance and resistance over the shallow trench isolation
(STI) region.
Figure 2 shows the simplified layout of the RF NMOS
transistor. The transistor has a multifinger configuration
with double-contacted gate polystructure. Dummy gate poly
is added to improve the gate structure formation. The metal 1
and metal 2 are used for the connection of the gate terminal.
Thesourcediffusions are connected using the metal 1 and
shortened to the body terminal or P-well, while the drain
diffusions are pulled out using the metal 3.
In order to extract physical subcircuit components in
the macromodel, all the physical layers and their geometry
that are used to form the structure of the transistor must
be known. The extraction technique used to extract the
subcircuit components values is as shown in [16].
2.1. Gate Resistance Modelling. Figure 3 shows the simplified
polysilicon gate structure and its distributed parasitic resis-
tances.AtRFfrequencyregion,Rgate is influenced by three
physical effects. The three effects are the distributed gate
electrode resistance Rg,poly Wf, the non-quasi-static (NQS)
effect in the channel Rg,ch [15,17], and the polysilicon gate
extension out of the active region Rg,poly Wext follows:
Rgate =Rg,poly Wf+Rg,ch +Rg,poly Wext .(1)
Distributed
gate electrode
Source Drain
Gate oxide
Distributed channel
Wext
Wext
Wf
Figure 3: Simplified polysilicon gate structure and its distributed
parasitic resistances.
In [18], the distributed effect of the gate electrode has been
studied and the following equations have been derived to
calculate the distributed gate electrode resistance.
Rg,poly Wf=ρpoly ·Wf/Lg
3·Nf
, Single-contacted gate,
(2)
Rg,poly Wf=ρpoly ·Wf/Lg
12 ·Nf
,Double-contactedgate
.
(3)
In (2)and(3), the variable Nfis the number of fingers,
ρpoly is the gate sheet resistance, and Lgand Wfs are the
channel length and unit width of a single finger. The factors
of 1/3 and 1/12 are used in (2)and(3)toaccountfor
the distributed gate resistance effect and the different gate
connection configuration at the ends of the gate structure.
The polysilicon gate extension Wext as shown in Figure 1
contributes to the total gate resistance as follows:
Rg,poly Wext =ρpoly ·(Wext/2)
Nf·Lg
.(4)
4 International Journal of Microwave Science and Technology
0
5
10
15
20
25
30
35
0 10203040506070
Rgate (Ω)
Fingers number Nf
Wf=1µm
Wf=5µm
Wf=2.5µm
(a)
0
5
10
15
20
25
30
35
Rgate (Ω)
Extracted
Calculated
Wf(µm)
Nf=4
Nf=24
Nf=64
0123456
(b)
Figure 4: Extracted and calculated Rgate versus (a) Nfand (b) Wf.
X1
B- -
B’
cross section
X2
Source diffusion
Contact
Source
Source
current
flow
current
flow
Metal 1
Contact
Drain
Drain
Metal 1
Metal 2
Metal 3
Via1
Via2
A
B
l1
l1
l2
l2
Drain diffusion
B
A- -cross section
A
A
Figure 5: Source and drain metal structure.
At RF frequency region, the channel will become like a
distributed RC network as shown in Figure 1. The distributed
channel resistance will reflect to the gate through the
capacitance network and increase the total gate resistance.
Note that this NQS channel resistance is bias and geometry
dependent. However, it is reported that a simple gate resis-
tance can model the distributed gate resistance effect, and it
is accurate up to ft/2 for an MOSFET without any significant
NQS effects [19]. Hence, only a geometry-dependent NQS
channel resistance is assumed to contribute to the total gate
resistance as follows:
Rg,ch =
x1·Lg
Nf·Wf
.(5)
Note that the variable x1is defined as a factor of the channel
sheet resistance that is reflected back to the gate structure.
Figure 4 shows the comparison between the extracted
and calculated Rgate versus Nfand Wfplots. It is observed
that Rgate is inversely proportional to Nf, and there exists
a minimum Rgate at the Wfof 2.5 μm. The Nf,and Wf
dependence of Rgate can be explained by considering (1)–
(5). From (2)–(5), the three physical effects on the gate
resistance are inversely proportional to Nf, and this explains
the trend of Rgate versus Nf. As shown in (3), the resistance
Rg,poly Wfis directly proportional to Wf,butin(5), the
resistance Rg,ch is inversely proportional to Wf.TheWf
effect on the resistance Rg,poly Wfand Rg,ch will compete
International Journal of Microwave Science and Technology 5
(a) (b)
Figure 6: Extracted and calculated (a) Rsand (b) Rdversus Nf.
Figure 7: Gate-to-substrate capacitance and resistance structure.
with each other and cause Rgate to have a minimum point
as shown in Figure 4. Therefore, based on the proposed
physical geometry equation, the calculated and extracted
Rgate resistance matches well with the change in Nfand Wf
of the transistor.
2.2. Source and Drain Resistance Modelling. The resistances
Rsand Rdshown in Figure 1 are defined as the effective
resistances that consist of the metal line, via, and contact
resistances as shown in the layout of Figure 5.Itisassumed
that the source and drain resistance model in the BSIM3v3
6 International Journal of Microwave Science and Technology
(a) (b)
Figure 8: Extracted and calculated (a) Csubg and (b) Rsubg versus Nf.
Figure 9: Gate-to-source and gate-to-drain capacitance structures.
model only models the active region of the parasitic resis-
tances. Based on the above layout, the following equations
can be derived to represent Rsand Rd:
Rs=ρm1·l1/x1+(Rcon/ncon)
ndiff,source
,
Rd=ρm3·l2/x2+(Rcon +Rvia1 +Rvia2)/ncon
ndiff,drain
.
(6)
The variables ρm1and ρm3represent the sheet resistance
for metal 1 and metal 3, and the variables Rcon,Rvia1 ,and
Rvia2 represent the contact, via1, and via2 resistances and the
International Journal of Microwave Science and Technology 7
(a)
(b)
Figure 10: Extracted and calculated (a) Cgs ext and (b) Cgd ext versus
Nf.
ncon,ndiff,source ,andndiff,drain are the numbers of contacts and
source and drain diffusions in the transistor.
Figure 6 shows the comparison between the extracted
and calculated Rsand Rdversus Nfplots. It is observed that
both resistances are inversely proportional to Nf, and there
exists a minimum point of resistance value at the Wfof
2.5 μm. From (6), the ndiff,source and ndiff,drain are the number
of source and drain diffusions, and they are proportional
to Nf. Hence, the Rsand Rdresistances show the inverse
proportionality with Nf.FromFigure 5, the variables l1,l2
and ncon are proportional to the Wfof the transistor, and
when they are applied to (6), the Wfeffect on both l1and l2
will compete with ncon and cause a minimum resistance level
to occur at Wfof 2.5 μm.
2.3. Gate-to-Substrate Capacitance and Resistance Modelling.
The components Csubg and Rsubg that are shown in Figure 1
are defined as the gate-to-substrate capacitance and resis-
tance over the STI region, and they are shown in the cross-
sectional structure in Figure 7. The dotted enclosed region
in Figure 7 is the gate area that is on top of the STI region
generating the parasitic components Csubg and Rsubg,and
based on the above layout geometry, the following equations
are formulated:
Csubg =CM1,STI ·aM1+CM2,STI ·aM2.(7)
Sub
Gate
1MT 1MT
Source
Gate
3MT
Drain
A- cross section
2MT
Cds fringing
A
(a)
0 10203040506070
0
5
10
15
20
25
30
35
Cds (fF)
=1m
=5m
=2.5 m
Extracted
Calculated
µ
µ
µ
Wf
Wf
Wf
Fingers number Nf
(b)
Figure 11: Drain-to-Source capacitance structure (a) and extracted
and calculated Cds versus Nf(b).
Sub
Gate
1MT 1MT
SourceGate
3MT
Drain
2MT
Rsub1
Rsub2Rsub3
Cjsb
Cjdb
A- cross section-
A
Figure 12: Substrate resistances network.
The variables CM1,STI and CM2,STI are the parasitic capaci-
tances per unit area of metal 1 and metal 2 over the STI
region, while the variables aM1and aM2are the area of the
8 International Journal of Microwave Science and Technology
0
100
200
300
400
500
600
700
800
900
0 10203040506070
Rsub1(Ω)
Wf=1µm
Wf=5µm
Wf=2.5µm
Fingers number Nf
(a) (b)
Figure 13: Extracted and calculated (a) Rsub1 and (b) Rsub2 and Rsub3 versus Nf.
dotted enclosed region of metal 1 and metal 2 as shown in
Figure 7.
Rsubg =Rsubstrate,STI
Nf
.(8)
From (7), it is shown that Csubg is mainly contributed by
the parasitic capacitances due to the layers of gate metal 1
and metal 2 over the STI region. The extracted variables
CM1,STI and CM2,STI in (7) represent the capacitance per unit
area (fF/μm2) of the enclosed metal 1 and metal 2 regions
as shown in Figure 7. As the dielectric thickness between
metal 2 and the substrate is higher than that of metal 1, it
is expected that the extracted CM1,STI is higher than CM2,STI.
Since there is some area under the enclosed metal 1 and metal
2 regions that is overlapped with the polysilicon gate, the
proposed equation (7)mayoverestimateCsubg slightly, and
a small capacitance may be required to be subtracted from
the above equation.
Csubg and Rsubg are extracted using Seneca and Substrate
storms [20] that simulate the layout structure as shown in
Figure 7. Based on the extracted results of Rsubg,itisfound
thatitisonlydependentonNf, and it is formulated as shown
in (8). Note that the extracted Rsubstrate,STI is defined as the
substrate parasitic resistance under the STI region.
Figure 8 shows the comparison between the extracted
and calculated Csubg and Rsubg versus Nfplots. It is observed
that Csubg is proportional to Nfwhile Rsubg is inversely
proportional to Nf.In(7), Csubg is dependent on aM1
and aM2,andwhenNfincreases, the two areas will increase
and cause Csubg to increase.
Based on the layout structure in Figure 7,itisobserved
that the length of lxis proportional to Nf. By using the
simple resistance equation that uses the sheet resistance
multiply with the number of squares, it is obvious that the
number of squares in the signal flow path of Rsubg is inversely
proportional to the length of lx.Hence,Rsubg will decrease
with increasing Nf.
2.4. Gate-to-Source and Gate-to-Drain Capacitances Mod-
elling. The capacitance Cgs ext and Cgd ext in Figure 1 repre-
sent the overlap and fringing capacitances between the gate-
to-source and gate-to-drain terminals as shown in Figure 9.
Based on the above layout structure, it is obvious that the
amount of overlap capacitance is dependent on the number
of source and drain metal lines that overlap the gate metal,
while the fringing capacitances will be dependent on the
separation distance between the source/drain metal lines
to gate polysilicon structure and the Wfof the transistor.
Since the separation distance between the source/drain metal
lines and the gate polysilicon structure is fixed, therefore
the fringing capacitance is only dependent on transistor’s
Wf. Based on the above analysis, the following equations are
formulated:
Cgs ext =CM2-M1,gs overlap ·ndiff,source +CM1-Poly,gs fringing
·Nf·Wf.(9)
Note that CM2-M1,gs overlap is the overlap capacitance between
the gate (metal 2) and source (metal 1) metal lines, and
CM1-Poly,gs fringing is the fringing capacitance between the gate
structure (polysilicon) and the source (metal 1) metal lines.
Cgd ext =CM3-M1,gd overlap ·ndiff,drain +CM1-Poly,gd fringing
·Nf·Wf.(10)
Here CM3-M1,gd overlap is the overlap capacitance between
the gate (metal 1) and drain (metal 3) metal lines and
CM1-Poly,gd fringing is the fringing capacitance between the gate
structure (polysilicon) and the drain (metal 1) metal lines.
It is assumed that the fringing capacitances from the metal
2 and metal 3 lines of the drain metal structure to the
polysilicon gate are small and negligible when compared to
the metal 1 and to the polysilicon gate fringing capacitance.
As the dielectric separation distance between the metal
3 (drain) and metal 1 (gate) is larger than the case of
metal 2 (gate) and metal 1 (source), it is expected that
International Journal of Microwave Science and Technology 9
(a) (b)
(c) (d)
(e) (f)
Figure 14: Measured and simulated results for NMOS transistor with Nfof 8, Wfof 1 μm, and Lgof 70 nm.
CM2-M1,gs overlap will be larger than CM3-M1,gd over lap . Further-
more, the extracted CM1-Poly,gs fringing must be close to the
extracted CM1-Poly,gd fringing or slightly smaller.
Figure 10 shows the comparison between the extracted
and calculated Cgs ext and Cgd ext versus Nfplots. It is
observed that both capacitances are proportional to Nfand
Wf, and the extracted Cgs ext capacitance is slightly larger
than Cgd ext.In(9)and(10), the Nfdependence in both of
the capacitances is due to the variables ndiff,source and ndiff,drain,
and since ndiff,source has one more diffusion than the ndiff,drain,
the extracted Cgs ext capacitance is slightly larger than Cgd ext.
The Wfdependence as shown in Figure 10 is mainly due to
the fringing capacitance effect in (9)and(10).
2.5. Drain-to-Source Capacitance Modelling. Cds is defined
as the fringing capacitance between the metal lines that
connect the source and drain diffusions. The location of the
fringing capacitance is indicated in Figure 11(a) that uses
the cross-section view of A-Ain Figure 9. Based on the
10 International Journal of Microwave Science and Technology
(a) (b)
(c) (d)
(e) (f)
Figure 15: Measured and simulated results for NMOS transistor with Nfof 24, Wfof 1 μm, and Lgof 70 nm.
layout structure, it is predicted that the fringing capacitance
is proportional to Nfand Wfof the transistor. Hence, the
following equation is formulated for Cds:
Cds =Cds fringing ·Nf·Wf.(11)
Note that Cds fringing is the fringing capacitance per unit
width between the metal lines of the source and drain metal
structures.
In Figure 11(b), the comparison between the extracted
and calculated Cds shows that the proposed formulated
equation can accurately predict the change in Nfand Wf.
2.6. Substrate Resistances Modelling. By using the cross-
section view of A-Ain Figure 9, the substrate resistances
network is added into the structure to indicate the location of
the parasitic as shown in Figure 12.Cjsb and Cjdb are junction
capacitances that are replaced by the junction diodes as
shown in Figure 1.Rsub2 and Rsub3 represent the substrate
resistances under the channel, while Rsub1 connects the
intrinsic bulk node to the body terminal. Based on the layout
structure, it is predicted that Rsub2 and Rsub3 are proportional
to Lg/(Nf·Wf), while Rsub1 is inversely proportional Nf·
Wf. Hence, the following equations are formulated for the
substrate resistances:
International Journal of Microwave Science and Technology 11
(a) (b)
(c) (d)
(e) (f)
Figure 16: Measured and simulated results for NMOS transistor with Nfof 64, Wfof 1 μm, and Lgof 70 nm.
Rsub1 =ρsubstrate
Nf·Wf+2·XJ,
Rsub2 =Rsub3 =ρsubstrate,sheet ·Lg
2·Nf·Wf+2·XJ.
(12)
In (12), the variable ρsubstrate is the substrate resistivity and
has the unit of Ωμm, and ρsubstrate,sheet is the substrate
sheet resistance under the active region and has the unit of
Ω/number of square. The parameter XJ represents the source
and drain junction depth, and its value can be found in the
BSIM3v3 model parameters.
In Figure 13, the comparison between the extracted and
calculated substrate resistances shows that the proposed
formulated (12) can accurately predict the change in Nfand
Wf.
3. Measurement Results and Discussion
3.1. Modelling Results. The devices under test (DUT) are
thin gate NMOSs with fixed Lgof 70 nm, Wfof 1, 2.5,
and 5 μm, and Nfof 4, 8, 16, 24, 32, 48, and 64. The
S-parameters were measured using the HP8510 network
analyzer with GSG RF probes for a frequency range from
50 MHz to 49.85 GHz at the various bias combinations of
the gate-to-source Vgs and drain-to-source Vds potentials.
After the system calibration was performed using LRRM
technique, the RF transistor and its deembedding structures
12 International Journal of Microwave Science and Technology
(a) (b)
(c) (d)
(e) (f)
Figure 17: Measured and simulated results for NMOS transistor with Nfof 24, Wfof 2.5 μm, and Lgof 70 nm.
were measured. In this measurement, the standard open and
short deembedding structures were used to remove the pad
and interconnects parasitic [21].
In order to demonstrate the scalability of the RF model,
measured and simulated DC, Y-parameters, and ftplots are
presented in this section. Figures 14–16 show the measured
and simulated results for fixed Wfof 1 μm with varying Nf
of 8, 24, and 64 at the biasing combination of Vgs and Vds
ranging from 0.3 to 1.2 V. From the comparison between
the measured and simulated results, it is observed that the
RF model can accurately predict the measured results as Nf
varies. The Wfscalability of the RF model is demonstrated
in Figures 15,17,and18 for fixed Nfof 24 with varying Wf
of 1, 2.5, and 5 μm. Hence, from Figures 14–18, the proposed
RF model is shown to be geometry scalable for Nfand Wf
for the frequency range from 50 MHz to 49.85 GHz.
3.2. Further Verification with Proposed Technique for the
Scalable Model. In a scalable RFCMOS model, there are
many different variables that determined the scalability of the
RF model. It becomes very tedious to verify and monitor the
model accuracy further so that the developed model, file has
to be scalable for a certain range of geometry, biasing and
frequency variables. Hence, a new verification technique is
proposed in this paper. This proposed verification technique
is crucial to both the modelling engineers and the model
International Journal of Microwave Science and Technology 13
(a) (b)
(c) (d)
(e) (f)
Figure 18: Measured and simulated results for NMOS transistor with Nfof 24, Wfof 5 μm, and Lgof 70 nm.
file end users as it helps them to monitor the quality of the
developed model and at the same time, the model file can be
checked for any errors in the coded geometry equations of
the parasitic subcircuit components. Furthermore, by using
this proposed technique, the amount of verification time
required to check the developed model file is reduced, and
thus reducing the overall model development time.
Figure 19 shows the model accuracy plots for NMOS
transistors with different Nfof 4, 8, 16, 24, 32, 48, and 64
and Wfof 1, 2.5, and 5 μmextractedatVgs =0.95 V and
Vds =0.8 V. From the box plots, it is observed that 10 to 90%
of the error population from the DC, S-parameters, and Ft
are within ±10%. In the three plots, the model accuracy for
all the fabricated devices is monitored at DC, 2.45, 5.45, and
10.25 GHz. Therefore, by generating such model accuracy
plots, the quality of the developed RF model in terms of its
accuracy is monitored for all the fabricated device sizes and
at the different frequency points. Furthermore, by plotting at
the other biasing points, the model accuracy of the RF model
can be checked for those important biasing regions.
Figure 20 shows the model continuity plots for the
parameters Gmand Y21 versus different Nfand Wfof 1, 2.5,
and 5 μmextractedatVgs =0.95 V and Vds =0.8 V. From the
three plots, it is observed that the simulated Gm(blue line)
14 International Journal of Microwave Science and Technology
(a)
(b)
(c)
Figure 19: Model accuracy for NMOSFETs with different Nfand
Wfof 1 μmatVgs =0.95 V and Vds =0.8 V (a), with different Nf
and Wfof 2.5 μmatVgs =0.95 V and Vds =0.8 V (b), and with
different Nfand Wfof 5 μmatVgs =0.95 V and Vds =0.8 V (c).
(a)
(b)
(c)
Figure 20: Model continuity for Gmand Y21 for NMOSFETs with
different Nfand Wfof 1 μmatVgs =0.95 V and Vds =0.8 V (a),
with different Nfand Wfof 2.5 μmatVgs =0.95 V and Vds =0.8V
(b), and with different Nfand Wfof 5 μmatVgs =0.95 V and
Vds =0.8 V (c).
International Journal of Microwave Science and Technology 15
and Y21 (red line) overlap each other, and this observation
implies that the RF model is continuous from DC to RF
region. Furthermore, the simulated transistor’s gain (red and
blue lines) can accurately predict the measured data (red
and blue symbols) as the Nfand Wfchanges and their
calculated absolute errors are within the error specification
of ±10%. It is also observed that the simulated Gmand
Y21 scale linearly with Nffor all the three Wf. By plotting
such model continuity plots at other biasing points, the Nf,
Wf, and biasing effect on the RF model are monitored at
both the DC and low-frequency region. In the case when the
coded equations of the subcircuit components in the model
file are incorrect, the model accuracy and continuity plots
will immediately reflect the incorrect effects of the wrong
equations, and this will alert the modelling engineer to check
the coded model file again.
In this proposed technique, the model accuracy and
continuity plots are generated to monitor the device geom-
etry, biasing, and frequency variables of the RF model.
From these two types of plots, the quality of the developed
model and the coded model file will be inspected, and the
final verified model file will be error-free and reliable to
use.
The proposed model accuracy and continuity plots can
also be used as one of the model acceptance criteria, whereby
its accuracy and continuity can be checked before accepting
and using the developed RF model file.
4. Conclusion
In this paper, the physical formation of the subcircuit par-
asitic is discussed with respect to its layout structure. The
scaling effect of the device geometry is accounted for in the
proposed scalable equations for each of the parasitic com-
ponents. By implementing the proposed scalable equations
for the parasitic components into the conventional subcircuit
RF model, a scalable RFCMOS subcircuit model can be
generated and shown to be valid up to 49.85 GHz. By using
the proposed verification technique, the time required to
verify a scalable RFCMOS model can be reduced greatly, and
the verification step can also ensure that the developed model
is error-free, and therefore, it is more robust and reliable to
use. Although the scalable RFCMOS model can accurately
predict the DC and RF characteristics of the transistor it will
still require being able to predict its high-frequency noise.
Hence, the scalable RFCMOS model will form the base of the
RF transistor modelling so that the study of the scalable high-
frequency noise modelling can be embarked on to achieve a
fully scalable RFCMOS model.
Acknowledgment
The authors would like to thank K. Takeshita, M. Yano, M.
Abe, A. Nakamura, A. Kuranouchi, and S. Tonegawa from
Sony for their helpful discussions and valuable inputs.
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