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A Dual-Rail Voltage Supply for Battery Powered
Portable Devices
Nyambayar Baatar, Namjae Kim, Hyojong Kim and Shiho Kim
Dept. of Electrical Engineering, Chungbuk National University, Chungbuk, 361-763, Korea
Email: {nyambayar, njk84, shiho}@chungbuk.ac.kr
Abstract— A positive and negative dual rail voltage supply
proposed for battery powered portable devices and a test chip
designed and fabricated by using 0.13um CMOS triple-well
process. Proposed dual voltage scheme provides an effective way
of reducing the dynamic power consumption due to the charge
recycling through the upper power rail and lower power rail
separated by series connected capacitors. The additional
advantage of the proposed system is that we can separate digital
block and analog block depending on the requirement of
operating speed and voltage swing levels.
I. INTRODUCTION
Nowadays, battery powered portable devices such as mobile
phones, MP3 players, digital cameras, and semi-active tags are
widely used, and many applications are integrated into the
mobile devices and require multi rail voltages. Due to recent
rapid progress in development of the semiconductor process
technologies from 90nm, 65nm, 45nm to 32nm technology
node, the design density and operating frequency have greatly
increased and operating voltage domain is scaled down from
3.3V to 1.2 V and even below 1.0V[1, 2]. Most of portable
devices must operate on a mixture of several different supply
voltage levels. Therefore most of portable devices adopt DC to
DC converters with several supply voltage levels. For analog
signal processing in low voltage operating chips, we can have
a great advantage by using a dual rail voltage supply with
positive and negative supply voltage. In the conventional
single battery supply system, we need separate plus and minus
DC to DC converters for a dual-rail supply configuration.
In this paper, we propose a dual-rail voltage supply for single
battery powered portable devices. The single battery powered
designs are becoming very popular in design community,
because they reduce the costs and take advantage of the
widely available power sources commonly used in portable
devices. Since the battery contains fixed amount of charge we
need to reduce the power consumption of power supply when
the design requires the dual voltage, in common case
designers using the DC to DC and positive to negative
converters. The proposed dual-rail voltage supply system does
not adopt additional DC to DC converters, so the
implementation cost and additional operating power for dual
level DC voltage generation is negligible. And we design and
fabricated a test chip with a triple well technology to prove the
correct operation of the proposed dual-rail power supply
scheme, and it is applicable to an advanced mixed SoC design.
This paper is organized as following. Dual voltage power
supply circuit configuration and implementation are explained
in Section II. Design of the test chip is presented in section III,
and in Section IV, measurement result and discussion. We
concluded the paper in section V.
II. CONFIGURATION AND IMPLEMENTATION OF THE
DUAL-RAIL POWER SUPPLY
A. Architecture of proposed dual rail power splitter
By a capacitive voltage divider shown in Fig. 1, battery
voltage is equally splitted to +VDD/2 and -VDD/2 level with
respective to the common ground level. The proposed
capacitive voltage divider provides two power rails of supply
voltage from single battery as shown in Fig.2.
Figure 1. Proposed capacitive voltage divider for splitting battery voltage
into dual level with equal magnitude.
Since the bias voltage of a chip is two levels with plus and
minus half VDD, we can get 3 levels of signal voltage swing
inside a chip or interface signal voltage among chips. The
nominal output voltage of Lithium ion batteries, widely used
in the portable devices, is about 3.3V, so the half swing level
is about 1.65V. In the proposed dual-rail voltage power supply
(DVPS) battery powered system, some low voltage part can be
operating plus half or minus half VDD level, some high speed
or high voltage part can be operating in full VDD voltage
swing range. We designed a voltage level shifter to interface
signals for positive half swing to full swing and full swing to
positive half swing voltage domains.
This work was supported by the IT R&D program of MKE/KEIT. [KI002134
Wafer Level 3D IC Design and Integration]
978-1-4244-7456-1/10/$26.00 ©2010 IEEE
492
(a)
(b)
Figure 2. Configuration of proposed dual-rail voltage power supply
(DVPS) for a battery powered system. b) Waveform of signal voltage swing.
Figure 3. Upper half supply(A-part), lower half supply (B-part), and full
swing(C-part) operating voltage block and voltage level shifters.
Fig.3 shows a Brief configuration of the proposed block
diagram inside a DVPS chip. The A-part is circuit block
operating in a plus half voltage, and the B-Part is a block
operating in a minus half voltage, and the C-part is a full
swing circuit block. There are two types of voltage level
shifter, one is for lower part to upper part (LS L2H), and
another is for upper part to lower part (LS H2L). The dual
voltage power supply from full wave rectifier having equally
split voltage level is proposed in the reference [2]. The main
purpose of the dual voltage supply in the reference [3] is
providing multiple levels of supply voltage from the rectified
DC voltage source. In the conventional voltage split scheme
[3,4] there is no significant benefit in the power efficiency
because the main power is supplied from AC power source.
However, the main advantage of proposed dual voltage is that
the improvement in power efficiency thanks to a charge
recycling of battery power. For a battery powered system,
limited number of charges is stored in a battery. In the
proposed dual-rail supply, current from the battery charge is
recycled in the plus half power rail and minus half power rail.
B. Stability issue due to drift of Virtual Ground potential
A mismatch of load current between the upper half and
lower half rail causes a different split, resulting in a drift in
virtual ground potential due to unequal Virtual Ground Split.
In the design step, we can avoid the stability problem of
virtual ground potential, if we can distribute a device and
circuit components to balance the load current of upper half
rail and lower half rail. If the load balancing at design stage is
not possible, we can use buffered virtual ground circuit.
One of conventional way to voltage split is using a
commercial rail splitter such as TLE 2426[4]. The drawback
of this approach is current consumption caused by rail splitter
even the chip is in a standby mode and limited control range
of the mismatch current between two power rails. By using
TLE2426 chip we can handle up to 20mA current mismatch
with about 300uA current consumption of the TLE2426 rail
splitter [4].
Another conventional way to balance the virtual ground
potential is unit gain feedback circuit using an OP Amp. We
can control standby mode by putting control switches to the
OP Amp power rail as shown in Fig. 4(b). The power supply
to the OP Amp is cut off during standby mode. The main
drawback of OP Amp driver is that we need two series
connected capacitor voltage separator for the virtual ground
and reference voltage. Also for large sinking or sourcing
current capability, we must have a larger current driving stage
in the OP AMP output stage, which may cause unwanted
power consumption by quiescent current draw. Hence, we
lose a benefit of low power consumption by charge recycling
of a battery.
2
1VBT
+
TLE2426
IN OUT
COM
2
1VBT
-
VGND
(a)
Figure 4. Virtual ground driving circuit to stabilize dual voltage supply by
using a voltage splitter(a), and driving buffer with unit gain OP Amp
feedback circuit(b)
493
We proposed dual rail voltage splitter with Analog-to-
Digital Converter(ADC) based virtual ground stabilizing
circuit. The two ADC convert input voltage of two power rail
to 8-bit digital signal. The digital comparator and controller is
a circuit to compare the two digital output values and
produces a control signal to the current mirror bank(CMB).
The CMB is array of 8-bit controlled current mirrors. The
difference between upper half and lower half voltage caused
by mismatched load current is compensated by balancing
current of UCMB or LCMB. The ADC and digital
comparator and controller are operated in the full swing
circuit block. There is cut-off switched inside the ADC and
Digital comparator and controller circuit for turning off the
circuit during standby mode.
Figure 5. Proposed battery voltage splitter using digital comparator and
ADCs.
Figure 6. Proposed current mirror bank(CMB) for the proposed battery
voltage splitter.
III. DESIGN OF THE TEST CHIP
The test chip was designed by using a 0.13um CMOS
process with P-substrate Triple well structure. Triple well
structure has been popular for memory technology[5], and
some advanced analog mixed mode designs[6-7]. Fig.7 shows
cross-sectional view of the proposed triple well structure.
Deep N-WELL is biased to +VDD/2 and p-substrate are
connected to -VDD/2, respectively. The NWELL can be
biased to ground or +VDD/2, and PWELL can be biased to
ground or -VDD/2 as shown in Fig.7. For the full swing
mode, body of NMOS and PMOS devices should be biased -
VDD/2 and +VDD/2 respectively. However, devices in upper
half swing or lower half swing blocks, one of the WELL can
be biased to ground potential. Signals in upper power rail
block or lower power rail block can be exchanged through the
voltage level shifters as shown in Fig.3. Fig. 8 shows a layout
view of the fabricated test chip.
Figure 7. Cross-section of triple well structure with P-substrate.
Figure 8. Layout of the test chip
IV. MEASUREMENT RESULT AND DISCUSSION
The test chip is designed and fabricated by using a 0.13um
triple well CMOS process through MPW shuttle provide by
IDEC. Fig. 9 shows Photograph of measurement set using
packaged chip on test PCB with a coin type Li-ion battery.
Figure 9. Photograph of Packaged chip on test PCB with a coin type Li
battery, and measurement set.
The voltage of Li-ion battery is divided by series connected
capacitors of 16uF, and dual rail voltage is supplied as the
positive and negative supply to the fabricated chip. Fig. 10
shows measured signal from fabricated chip. Fig 10(a) is a
494
measured waveform of Negative and positive half voltage
swing, respectively. Fig 10(b) is the measured positive half
swing input signal and full swing output voltage waveform of
a voltage level shifter. The measurement data show that the
logic blocks in upper power rail and in lower power rail
works, and also level shifters and full swing blocks are
working correctly. Proposed dual voltage scheme provides an
effective way of reducing the dynamic power consumption
due to charge recycling through the upper power rail and
lower power rail.
Figure 10. (a) Measured waveform of Negative and Positive Half voltage
swing, and (b) Measured positive half swing input and full swing output
voltage waveform of the level shifter.
In order to check the stability of virtual ground potential,
we measured the power rail voltages and virtual ground
potential. In Fig.11 (a) shows measurement result of different
load when the mismatching current is above 50mA. The
measured virtual ground potential is about 0.72V. Fig.11 (b)
is measured power rail voltage when current mismatching
load current is in a suitable current range of 25mA.
Figure 11. Measured waveform of negative, positive rail and ground
potential at different load current of positive and negative block. Measured
waveform of unbalanced case(a), and measured power rail voltage in a
suitable current range.
The power efficiency is improved by charge recycling. The
additional advantage of the proposed system is that we can
separate digital logic block and analog block depending on
the requirement of operating speed and voltage swing levels.
V. CONCLUTIONS
We proposed a dual-rail voltage supply for battery
powered portable devices, and designed and fabricated a test
chip by using a 0.13um CMOS triple well process. Proposed
dual voltage scheme provides an effective way of reducing
the dynamic power consumption due to the charge recycling
through the upper power rail and lower power rail separated
by series connected capacitors. The proposed scheme
provides both negative and positive dual voltage power
supply from single battery by capacitive voltage divider. The
power efficiency is improved by charge recycling.
ACKNOWLEDGMENT
The authors thank to IDEC for supporting EDA tools and
for providing MPW shuttle service of Samsung 0.13um triple
well CMOS process.
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[3] N. G. Carter, and D. D. Myron, "Dual voltage power supply having
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[4] Datasheet of TLE2426 “RAIL SPLITTER and PRECISION VIRTUAL
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