No full-text available
To read the full-text of this research,
you can request a copy directly from the authors.
Investigations of the effects of blade type, dicing tape, blade preparation and process parameters on 55nm node low-k wafer
Abstract
This paper presents an investigation of the effects of blade type, dicing tape, blade preparation and the key process parameters optimization on improving topside ILD peeling (thicker scribe structures) and chipping for 55nm low-k wafer. An appropriate dicing blade selection, blade preparation / conditioning methodology and dicing tape selection plays an important role in developing a robust saw process. As such, experimental studies were conducted under varying Z1 spindle rotation, Z1 cut depth into Si as well as the blade type property variation as the input factors, in order to improve the ILD peeling and die chipping. The settings of machining parameters and blade types were determined by using the design of experiment (DOE) techniques and the critical process parameters and materials were analyzed statistically by using the analysis of variance (ANOVA). Dicing tape property variations (PO-base or PVC-base) as well as the blade preparation methodology posed some influences on the overall dicing quality, such as die backside chipping, die removal performance, ILD peeling and die topside chipping. SEM imaging and optical visual inspection were conducted to validate the impacts of the ILD peeling / chipping on post-processed low-k wafers. A thorough quantification and categorization of ILD peeling and chipping on heavy metallization at the saw scribe structures were described. As part of the recommendation for future works, a different approach in dicing technology, namely laser grooving was proposed to eliminate ILD peeling and chipping. In conclusion, the optimized dicing recipe for 55nm node low-k wafer suggested by the DOE model are: (1) a thinner PO-base dicing tape, (2) a dicing blade with higher diamond concentration and finer grit size, (3) blade preparation / conditioning done with SiC board and (4) processing at lower spindle rotation and deeper cut depth are much preferred. The overall dicing responses and cutting quality has improved and is better compa red to current production recipe.
... Another requirement for plating of TSVs is minimizing the boundary layer in the plating bath [84,[86][87][88][89]. The plating rate of high aspect ratio vias can be limited by transport of Cu ions and organic additives. ...
... Historically, dicing has been conducted after wafer thinning, using a mechanical saw with a blade that is coated with a diamond abrasive [89,119]. The wafer is mounted on dicing tape, to hold the dies together until they are needed for assembly. ...
The idea of using through-silicon-via (TSV) technology has been around for many years. However, this technology has only recently been introduced into high volume manufacturing. This paper gives a comprehensive summary of the TSV fabrication steps, including etch, insulation, and metallization. Along with the backside processing, assembly, metrology, design, packaging, reliability, testing and yield challenges that arise with the use of TSVs. Benefits and drawbacks for using each approach to manufacture TSVs are discussed including via-first, via-middle, and the via-last process. Several applications for TSVs are discussed including memory arrays and image sensors.
... Currently, there is a need to determine how to remove the blade surface glue. According to previous studies [4], [5], the application of the dressing board improves the topside chipping issue of the wafer dicing saw compared with the before method mirror wafer dressing mode. ...
for IC assembly process. This film material would cover the
gold wire which electrical conduction, to prevent the gold wire
damage cause the product fail in the stack die chip on die bond
process, but this film is easy to occur film burr issue during
wafer dicing saw process. If film burr occur, it will cause die
bond pad contamination, such that will cause gold wire can’t
eutectic with bond pad, and IC product will be fail then cause
yield loss.
In this paper, experiment how to apply the blade dressing
method improvement film burr issue, is also investigated
developed new dressing board material to increase quality and
reduce cost, thus achieving a win-win outcome.
Index Terms— FOW (Film On Wire), film burr, blade
dressing
With the farther shrink of the IC dimension, the low k material has been widely used to replace the traditional SiO<sub>2</sub> ILD in order to reduce the interconnect delay. The introduction of low k material into silicon imposed challenges on dicing saw process, ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low k material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300mm CMOS 90nm dual damascene low k wafer was chosen as a test vehicle to develop robust low k dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street...) affecting cutting quality were studied and optimized. The selected C90 dual damascene low k device passed package reliability test with the optimized low k dicing saw recipe and process. The further improvement and solutions in eliminating the low k dicing saw peeling from both wafer fab and packaging assembly were also explored.