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Speed kills? not for rise processors
... However, such improvements in IPC may be offset by an increase the critical delay path from the output of one set of latches into the next by increasing the number of levels of back-to-back logic on the critical delay path. Historically, this has lead to a form of competition between microprocessor designs embracing a "speed demon" approach (focus on higher clock frequency), versus a "brainiac" approach (focus on higher IPC) [Gwe93]. This dissertation describes techniques for increasing the average number of instructions executed per clock cycle without impacting cycle time. ...
... For many years, a major point of contention among microprocessor designers has revolved around complex implementations that attempt to maximize the number of instructions issued per clock cycle, and much simpler implementations that have a very fast clock cycle. These two camps are often referred to as "brainiacs" and "speed demons" -taken from an editorial in Microprocessor Report [7]. Of course the tradeoff is not a simple one, and through innovation and good engineering, it may be possible to achieve most, if not all, of the benefits of complex issue schemes, while still allowing a very fast clock in the implementation; that is, to develop microarchitectures we refer to as complexity-effective. ...
... The "Speed Demons" school focused on increasing frequency. The "Brainiacs" focused on increasing IPC [13], [14]. Historically, DEC Alpha [15] was an example of the superiority of "Speed Demons" over the "Brainiacs." ...
In the past several decades, the world of computers and especially
that of microprocessors has witnessed phenomenal advances. Computers
have exhibited ever-increasing performance and decreasing costs, making
them more affordable and in turn, accelerating additional software and
hardware development that fueled this process even more. The technology
that enabled this exponential growth is a combination of advancements in
process technology, microarchitecture, architecture, and design and
development tools. While the pace of this progress has been quite
impressive over the last two decades, it has become harder and harder to
keep up this pace. New process technology requires more expensive
megafabs and new performance levels require larger die, higher power
consumption, and enormous design and validation effort. Furthermore, as
CMOS technology continues to advance, microprocessor design is exposed
to a new set of challenges. In the near future, microarchitecture has to
consider and explicitly manage the limits of semiconductor technology,
such as wire delays, power dissipation, and soft errors. In this paper
we describe the role of microarchitecture in the computer world present
the challenges ahead of us, and highlight areas where microarchitecture
can help address these challenges
From its birth with 4 bits, first stumbling 8-bit steps, no longer an adolescent 16-bit design, and well past the awkward 32-bit age, the microprocessor is finally mature and well into middle age! It is only those of us for whom the Fogey Factor is high who remember this lifecycle. It has certainly not been boring or lacking drama. We remember fondly the Milli Vanilli of semiconductors,1 the overhyped RISC v. CISC wars, and our first experience with “flame wars” on comp.arch. Not to be missed is the history of the “Brainiacs” and “Speed Demons”2 with special guest star “Fireball.”3
Since its announcement, the IBM RISC System/6000® processor has characterized the aggressive instruction-level parallelism approach to achieving performance. Recent enhancements to the architecture and implementation provide greater superscalar capability. This paper describes the architectural extensions which improve storage reference bandwidth, allow hardware square-root computation, and speed floating-point-to-integer conversion. The implementation, which exploits these extensions and doubles the number of functional units, is also described. A comparison of performance results on a variety of industry standard benchmarks demonstrates that superscalar capabilities are an attractive alternative to aggressive clock rates.
A superscalar processor with three execution units is described in
details in this paper. The execution units are implemented using
reprogrammable field-programmable gate array (FPGA) chips, allowing the
user to configure them to best fit the application. Each instruction,
composed of 128 bits, directly controls all the processor resources, in
a horizontal microprogramming way
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for feature sizes of , 894 , and . Performance results and trends are expressed in terms of issue width and window size. Our analysis indicates that window wakeup and selection logic as well as operand bypass logic are likely to be the most critical in the future.
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