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Garbage in Reversible Designs of Multiple Output Functions
Abstract
In this paper we analyze the number of garbage outputs that must be added to a multiple output function to make it reversible. We give the precise formula for the theoretical minimum. For some benchmark functions, we calculate the garbage re- quired by some proposed reversible design meth- ods and compared it to the theoretical minimum. Based on the information about garbage we sug- gest a new reversible design method, that produces the minimum number of garbage outputs. Finally, we show that our proposed reversible logic struc- ture may have some application in conventional logic design.
... Because of less or no energy dissipation we can achieve high density and so we can achieve smaller size overcoming the physical limitations. Any function of Boolean variables is said to be reversible if the number of outputs is equal to the number of inputs and function mapping from input vectors to output vectors is bijective function [4]. ...
... The important parameters to be considered in synthesis of reversible logic [4]: minimum number of ancilla, minimum number of garbage outputs, minimum number of gates, and minimum quantum cost. ...
... The basic classifications with brief descriptions of methods 1.Composition method [4]: A Boolean function is realized as a network of small and well known reversible gates. 2.Decomposition method [4]: A Boolean function is decomposed into small functions which are realized as separate reversible networks. ...
... Least usage of ancillary inputs and garbage outputs is preferred [8,16,28,29]. Minimizing garbage output gets more preference over minimizing gate count [17]. ...
... Optimizing these performance parameters for a given design is the most important design criteria in reversible circuits. When optimizing these performance parameters, higher priority needs to be given for optimizing GO [17]. The number of garbage outputs in quantum circuits needs to be optimized in order to improve the footprint of the overall design [14]. ...
... Garbage outputs are present only to preserve the one-to-one correspondence of reversible gates. Optimizing garbage is an advantage in reversible circuit design [17]. ...
Reversible logic has gained importance in the last few decades because of its low power dissipation. Quantum cost, garbage outputs, ancillary inputs and gate count are some of the performance parameters used to weigh reversible designs against one another. Optimization of these parameters is of great relevance to obtain an optimal design. This paper presents the design of a reversible squaring and sum-of-squares units explored for a trade-off between garbage outputs and quantum cost. The proposed work focuses on the design of dedicated unsigned and signed squaring units with a generalized methodology for n-bit squaring unit and novel sum-of-squares unit. For the optimization of the squaring circuit, the redundant product terms from the multiplier logic are eliminated. The ancillary inputs are regenerated due to which the extraneous garbage outputs are reduced. The obtained results are compared with existing state-of-art designs for performance. The garbage-cost optimized designs were found to have a 50% improvement of both ancillary inputs and garbage outputs over the direct implementation; 51% improvement of ancillary inputs and 27% improvement of quantum cost over the garbage free designs. Usage of optimized dedicated sum-of-squares unit enhances the functionality of the digital signal processor.
... Interest in reversible logic started when Landauer (1961) proved that traditional binary irreversible gates lead to power dissipation in a circuit regardless of implementation [1]. Each bit of information that is lost, generates KT ln(2) Joules of heat energy, where K is Boltzmann's constant and T the absolute temperature (Kelvins) at which computation is performed [2,3]. Bennett (1973) showed that for power not to be dissipated in an arbitrary circuit, it is necessary that this circuit be built from reversible gates. ...
... Reversible (3,3) gates, that are universal in two arguments, can be used for the construction of the RPGA. Reversible gates are computationally universal if they can be used to generate AND, OR, NOT gates, i.e. they can be used to generate any Boolean functions. ...
... Reversible (3,3) gates, that are universal in two arguments, can be used for the construction of the RPGA. Reversible gates are computationally universal if they can be used to generate AND, OR, NOT gates, i.e. they can be used to generate any Boolean functions. ...
logic synthesis techniques will definitely be a necessary part of the long-term future of computing. The paper introduces the design of a new reversible logic module (RLM) with three versions I, II, and III. It is universal in two arguments. A proposed design of reversible programmable gate array (RPGA) based on the new (RLM) is presented. It is superior to previous types of (RPGA) structures in that the same type of reversible logic modules is used in the implementation of the entire circuit. Symmetric and no symmetric functions can be realized by the proposed (RPGA). Synthesizing reversibly the logic functions using this method is good for multi-output functions as well as it can be extended to incompletely specified functions.
... Similarly the costs of 3*3 gates by Kerntopf [24,34,37], Margolus [21], De Vos [24], Khan [20], and Maslow [21,22], costs of all 4*4 Perkowski's gates [17], and other gates from [24] can be calculated. Next observe that a new permutation quantum gate with equations: ...
... Similarly the costs of 3*3 gates by Kerntopf [24,34,37], Margolus [21], De Vos [24], Khan [20], and Maslow [21,22], costs of all 4*4 Perkowski's gates [17], and other gates from [24] can be calculated. Next observe that a new permutation quantum gate with equations: ...
... This is the cheapest quantum realization known to us of a complete (universal) permutation gate and it is thus worthy further investigations. We found that the equation of this gate was known to Peres [21], but it has been not used in reversible or quantum computing. Observe that algorithms from [33,40], when given the equation of Peres gate, would return the solution composed fro Toffoli and Feynman gates, which would lead to clearly non-minimal quantum sequence. ...
A new approach to synthesis of permutation class of quantum logic circuits has been proposed in this paper. This approach produces better results than the previous approaches based on classical reversible logic and can be easier tuned to any particular quantum technology such as nuclear magnetic resonance (NMR). First we synthesize a library of permutation (pseudo- binary) gates using a Computer-Aided-Design approach that links evolutionary and combinatorics approaches with human experience and creativity. Next the circuit is designed using these gates and standard 1*1 and 2*2 quantum gates and finally the optimizing tautological transforms are applied to the circuit, producing a sequence of quantum operations being close to operations practically realizable. These hierarchical stages can be compared to standard gate library design, generic logic synthesis and technology mapping stages of classical CAD systems, respectively. We use an informed genetic algorithm to evolve arbitrary quantum circuit specified by a (target) unitary matrix, specific encoding that reduces the time of calculating the resultant unitary matrices of chromosomes, and an evolutionary algorithm specialized to permutation circuits specified by truth tables. We outline interactive CAD approach in which the designer is a part of feedback loop in evolutionary program and the search is not for circuits of known specifications, but for any gates with high processing power and small cost for given constraints. In contrast to previous approaches, our methodology allows synthesis of both: small quantum circuits of arbitrary type (gates), and permutation class circuits that are well realizable in particular technology.
... 10-12,16-18 Some factors such as number of gates, number of garbage inputs/outputs, number of transistors, and quantum cost (QC) are considered to measure the complexity of a reversible logic design. 9,15,[18][19][20][21][22] The QC is an important figure of merit to evaluate a design. 6,15 In this paper, we design some new circuits for a reversible binary coded decimal full adder and subtractor (BCD-FA/S), using GA and DC concepts. ...
... The Minimum number of required DC-outputs for this circuit is p = log 2 q , where q is the maximum number of repetition in the output patterns. 9 There are 11 repeated '1's in truth table of the P ; therefore, requires at least p = log 2 q = log 2 11 = 4 DC-outputs. Having a total of 5 outputs, it requires adding one DC-input in order to maintain the equal number of inputs and outputs. ...
... Since the DC-input must be constant in the final circuit, this additional input is also named constant input in the literature. 9 We have synthesized the truth table of the detection unit using the genetic algorithm and the don't cares, shown in Fig. 11. In Ref. 16, we also synthesized this truth table using Fredkin gates. ...
Reversible logic and binary coded decimal (BCD) arithmetic are two concerning subjects of hardware. This paper proposes a modular synthesis method to realize a reversible BCD-full adder (BCD-FA) and subtractor circuit. We propose three approaches to design and optimize all parts of a BCD-FA circuit using genetic algorithm and don't care concept. Our first approach is based on the Hafiz's work, and the second one is based on the whole BCD-FA circuit design. In the third approach, a binary to BCD converter is presented. Optimizations are done in terms of number of gates, number of garbage inputs/outputs, and the quantum cost of the circuit. We present four designs for BCD-FA with four different goals: minimum garbage inputs/outputs, minimum quantum cost, minimum number of gates, and optimum circuit in terms of all the above parameters.
... There were several design methods proposed in the literature for the reversible design of multiple output Boolean functions. We would like to compare our results to the results of RPGA method by Perkowski et al. [17] (the method designed to synthesize the symmetric functions with reversible gates), reversible wave cascades [14], Khan gate family synthesis [9, 8], generalized Toffoli gates family [12, 5] and design of the Toffoli circuits using the templates [13]. The comparison consists essentially of the three parts: comparison of the garbage, number of gates in the reversible cascade and comparison of the quantum costs. ...
... The asymptotic reversible cost (number of gates) of the both realizations are the same, namely O(n 2 ). But, the RPGA method has excessive garbage, n(n+1) 2 (calculated in [12]), when the presented method has the garbage of maximum (2n − 1). A good quantum realization of the Kerntopf gates used in [17] was never found, therefore we claim that from the point of view of quantum cost our method will produce quantum circuits which will be constant (> 1) times cheaper. ...
... A good quantum realization of the Kerntopf gates used in [17] was never found, therefore we claim that from the point of view of quantum cost our method will produce quantum circuits which will be constant (> 1) times cheaper. Comparison to the reversible wave cascades [14] (RWC columns), Khan gate family synthesis [9] (KGF columns) and generalized Toffoli gates family [12, 5] (GT columns) reversible synthesis results is summarized inTable 1. Actual circuits for the presented design can be found in [11]. The presented comparison is not quite fair. ...
The work starts with a general idea of how to realize a dy-namic programming algorithm as a reversible circuit. This realization is not tied to a specific reversible design model and technology or a class of dynamic algorithms, it shows an approach for such synthesis. As an illustration of this approach, a class of all symmetric functions is realized in a dynamic programming algorithm manner as a reversible circuit of Toffoli elements. The garbage, quantum and re-versible costs of the presented implementation are calculated and compared to the costs of previously described reversible synthesis methods. The summary of results of this com-parison is as follows. The quantum cost of the proposed method is better than the quantum cost of any other known systematic approach. The garbage is usually lower (except for comparison with the synthesis methods, primary goal of which is synthesis with theoretically minimal garbage). For the large functions reversible cost is better or has the same asymptotic that of other methods. Although the reversible cost comparison may not look beneficial for the small func-tions, the possible technological implementation (quantum) shows that it is beneficial to use the presented approach even for the small functions.
... The output permutation is not noted if it is the identity. Specification: [0,1,2,3,4,6,5,7] (corresponds toTable 5) Circuit: TOF2(b,a) TOF3(c,a,b) TOF2(b,a) c b a c + b + a + 0 0 0 0 0 00 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 Specification: [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0] Circuit: TOF4(c,b,a,d) TOF3(b,a,c) TOF2(a,b) TOF1(a) Example 6: This example is taken from [17]. Specification: [3,11,2,10,0,7,1,6,15,8,14,9,13,5,12,4] Circuit ...
... Specification: [0,1,2,3,4,6,5,7] (corresponds toTable 5) Circuit: TOF2(b,a) TOF3(c,a,b) TOF2(b,a) c b a c + b + a + 0 0 0 0 0 00 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 Specification: [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0] Circuit: TOF4(c,b,a,d) TOF3(b,a,c) TOF2(a,b) TOF1(a) Example 6: This example is taken from [17]. Specification: [3,11,2,10,0,7,1,6,15,8,14,9,13,5,12,4] Circuit ...
... The solution is comparable to the solution given in [17]. Specification: [4,6,2,0,15,13,7,5,9,11,3,1,14,12,10,8] Circuit: TOF3(c',b',a) TOF2(c,b) TOF2(c,d) TOF1(b) TOF1(a) TOF3(b,d,c) TOF2(c,b) In this case, the output permutation is (c,b,a,d). Comparing the solution for Examples 6 and 7 shows the importance of applying the synthesis method to a problem and its inverse. ...
Reversible circuits can lead to low-power CMOS implementations and are also of interest in optical and quantum computing. In this paper, we consider the synthesis of reversible logic assuming a generalized Toffoli gate. We make use of Rademacher-Walsh spectral techniques and in particular a spectral measure of function complexity used as a metric in guiding the search for a solution. The synthesis procedure introduced develops the circuit from inputs to outputs and from outputs to inputs simultaneously taking advantage of the best translation available at each step. No backtracking or look-ahead is used. Preliminary results are given for reversible and nonreversible functions together with several ideas for future work.
... Fredkin and Toffoli proved that minimizing garbage outputs, ancillary inputs increases the efficiency of the reversible logic circuit [4]. The reduction of garbage output lines is of utmost importance in reducing the heat loss of a reversible circuit [5], [6], [7]. In [5], it has been stated that when faced with the question of reduction in gate count or garbage output, the preference must be given to the minimization of garbage output. ...
... The reduction of garbage output lines is of utmost importance in reducing the heat loss of a reversible circuit [5], [6], [7]. In [5], it has been stated that when faced with the question of reduction in gate count or garbage output, the preference must be given to the minimization of garbage output. Reversible logic has applications in quantum computing, optical computing etcetera. ...
Power dissipation has become the major concern for circuit design and implementation. Reversible Logic is the best alternative to Irreversible Logic in terms of low power consumption. Circuits designed using reversible logic have a wide array of applications. The Quantum Cost, Garbage Outputs, Ancillary Inputs and Delay are some of the parameters of reversible circuits that can be used to determine their efficiency and compare them with existing works. Optimization of these parameters are highly essential. Garbage Outputs is an important parameter that must be considered. This paper presents a design for a Reversible Radix-4 Booth Multiplier that is optimized in Garbage Cost and Ancillary inputs. The design proposed is capable of both signed and unsigned multiplication. The optimization in Garbage Cost ensures lower heat dissipation. The Encoded Booth Algorithm or Radix-4 Booth Algorithm reduces the number of partial products generated in signed multiplication to half the number generated using a Radix-2 signed multiplier making it suitable for Digital Signal Processors. The design proposed is compared to existing multiplier circuits and the parameters are tabulated.
... Another important issue in reversible logic synthesis is use of ancilla(garbage) [12] lines. Garbage lines are the extra lines that are needed to realize the given reversible function. ...
... The optical computing concept in design and synthesis of reversible logic circuit has first been introduced in [16]. Generalized implementation of reversible gate like Toffoli, Fredkin, and CNOT using optical technology has been reported in [12], where Mach-Zehnder interferometer (MZI) is used to implement all-optical reversible logic gates. Reversible implementation of NOR gate using SOA based MZI switches is realized in [10]. ...
Reversible circuits are of great importance in many applications involving low power design. One of the main areas where reversible circuits play vital role is in optical computing. Reversible logic has many other applications in several technologies such as quantum computation, digital signal processing, cryptography, ultra low power CMOS design, nanotechnology, thermodynamics and bioinformatics. Most of them are under research. In present days VLSI technology is facing a real challenge with the exponential growth of packing density in VLSI chip and CMOS technologies are reaching to a limit. So some alternative technology is required to overcome from this stagnancy. Energy losses inform of heat generation in VLSI chip is a real hurdle that is facing traditional CMOS technologies. Problem due to irreversibility of logic leads to loss of energy, generation of heat, loss of information, slow computation.
Reversible logic may provide a potential solution of such problems. Among various reversible approaches, optical computing has proved to be very significant in achieving high speed since it uses photons in light which have unmatched speed. In the optical computer of the future, the electronic circuits and wires will be replaced by a few optical fibers and films, making the systems more efficient with no interference, more cost effective, lighter and more compact. Based on optical computing, several optical switches have been proposed which have been designed for future applications. One among them is MACH-ZEHNDER INTERFEROMETER (MZI). In this thesis, we have studied behavior of MZI based switch and developed novel approaches for implementation of reversible logic circuits.
... Although advantages of using reversible computing have been known for many years all papers published in 1980s and 1990s were concerned mostly with proposing simple binary reversible gates and studying universality as well as basic properties of these gates. Research on synthesis of reversible logic circuits has started only very recently [42] [48] [15] [35] [27] [39] [24] [25] [26] [28] [33] [34] [29] [4]. Generalized families of binary and multiple-valued gates have also been proposed [24] [25] [26] [27] [35] [39]. ...
... These functions h 1 and h 2 are control inputs to the first level nodes of the fLIBDD (corresponding to the output functions F and G, respectively). To realize these functions, any method of realizing reversible circuits can be used, and particularly the cascade methods [35] [27] [33] [34] [24] [25] [4] [29] that produce no garbage or little garbage signals. Functions h 1 and h 2 are realized as a reversible cascade with inputs a, b, c, d, e, f, g and outputs A = h 0 , B = h 1 , c, d, e, f, g. ...
The paper presents a family of new expansions of Boolean functions called Function-driven Linearly Independent (fLI) expansions. On the basis of this expansion a new kind of a canonical representation of Boolean functions is constructed: Function-driven Linearly Independent Binary Decision Diagrams (fLIBDDs). They generalize both Function-driven Shannon Binary Decision Diagrams (fShBDDs) and Linearly Independent Binary Decision Diagram (LIBDDs). The diagrams introduced in the paper, can provide significantly smaller representations of Boolean functions than standard Ordered Binary Decision Diagrams (OBDDs), Ordered Functional Decision Diagrams (OFDDs) and Ordered (Pseudo-) Kronecker Functional Decision Diagrams (OKFDDs) and can be applied to synthesis of reversible circuits.
... According to Rolf Landauer's principle, if traditional irreversible binary gates are used in the circuit design, in this situation when one bit of information is lost or cleared during circuit operating, KTln2 (Joule) of energy is dissipated in the internal heat form; k is the Boltzmann's constant (≈ 1.380658 × 10 −23 J/K), and T is the environment temperature of the operation. Although the amount of dissipated energy per bit in the room temperature is small (2.9 × 10 -21 J), it is not negligible [1][2][3][4]. In the traditional computational devices, logical operations are performed using the conventional logic gates AND, OR, and NOT. ...
Reversible logic is a nowadays promising choice for circuit design technologies since it is having diversified applications in the fields of digital signal processing, cryptography, quantum computing, and low power CMOS design. Since every two qubits in the binary logic are equivalent to one qudit in the quaternary logic, the optimum designed primary binary building blocks such as adders and subtractors easily can be used in quaternary logic design. In this paper, we first proposed a novel quaternary to a binary decoder and also binary to quaternary encoder circuits. Secondly, we have used these converters to the synthesis of the quaternary quantum reversible full adder, half subtractor, and full subtractor circuits. The proposed converter circuits have promised accomplishment compared to the existing designs; these circuits are built on the elementary quantum gates, which are realizable using the liquid ion trap in the quantum technology. The designed strategy (using the converters to realize computational circuits) is easily applicable in the large-scale quaternary quantum circuit designs.
... Quantum Cost (QC) of a reversible circuit is referred to the cost of the circuit in terms of the quantity of 1 × 1 and 2 × 2 primitive gates used to realize the circuit. While designing a reversible logic circuit, fan-out and feedback are not permitted [4][5][6]. CI, GO and QC are the important parameters that need to be minimized for the design of an efficient reversible circuit. Hardware complexity of the reversible logic gates is defined in terms of number of EXOR, AND & NOT gates used to design the circuit. ...
Optimization of device power can be achieved using reversible logic computation and this technique can be applied to a variety of low power applications such as optical computing, nanotechnology, Complementary Metal Oxide Semiconductor (CMOS) Very Large-Scale Integrated Circuits (VLSI) design and many more. Basic and universal gates are the basic building blocks of digital system. In this paper, a new reversible Basic, Universal and Special (BUS) gate is proposed that is available as a single gate with multiple functionalities as basic (AND, OR & NOT), universal (NAND & NOR) and special gate (EXOR). The proposed BUS gate is implemented on Field Programmable Gate Array (FPGA) and simulated using 180nm and 90nm CMOS process technologies. Manchester adder and C17 circuit of ISCAS'85 (International Symposium on Circuits and Systems-1985) benchmark suite using BUS gate are designed and verified using Electronic Design Automation (EDA) tools. There is a power reduction of about 64.41% and 14.06% at 180nm and 90nm CMOS process technologies respectively in reversible BUS gate as compared to conventional CMOS-based designs. Thus, this paper provides a threshold to build more complex arithmetic systems using reversible logic, thus increasing the performance of computing systems with low power dissipation.
... Unwanted or unused output of a reversible gate (or circuit) is known as garbage output [10]. The garbage outputs are needed only to maintain the reversibility. ...
... And also, a reversible circuit should be designed taking minimum number of reversible gates, garbage outputs and constant inputs [11][12]. Garbage is defined as the number of outputs added to make an n- input k-output Boolean function ((n, k) function) reversible [13]. This paper is prepared as follows: In Section 2, principle and operation of TOAD-based optical switch is explained [14][15][16][17][18]. All-optical circuit realization for TOAD switch-based New TAND Gate is reported in Section 3 and universal application of this gate is informed in Section 4. Section 5 covers simulation (by Matlab-7.0) ...
Since the seventies of the past century the reversible logic has originated as an unconventional form of computing. It is new relatively in the area of extensive applications in quantum computing, low power CMOS, DNA computing, digital signal processing (DSP), nanotechnology, communication, optical computing, computer graphics, bio information, etc .Here we present and configure a new TAND gate in all-optical domain and also in this paper we have explained their principle of operations and used a theoretical model to fulfil this task, finally supporting through numerical simulations. In the field of ultra-fast all-optical signal processing Terahertz Optical Asymmetric Demultiplexer (TOAD), semiconductor optical amplifier (SOA)-based, has an important function. The different logical (composing of Boolean function) operations can be executed by designed circuits with TAND gate in the domain of universal logic-based information processing.
... As an example of problems with LNN circuit model, consider the very simple 4x4 Toffoli gate shown as a unit in Fig. 1(a). Other authors [26,27,28,29,30,31,32] calculate the quantum cost of the gate as a function of number of inputs regardless of what is the distance of the qubits used in this gate. This is not accurate when the circuit is realized in linear Ion Trap technology. ...
We present a logic synthesis method based on lattices that realize quan-tum arrays in One-Dimensional Ion Trap technology. This means that all gates are built from 2x2 quantum primitives that are located only on neighbor qubits in a one-dimensional space (called also vector of qubits or Linear Nearest Neighbor (LNN) architecture). The Logic circuits designed by the proposed method are realized only with 3*3 Toffoli, Feynman and NOT quantum gates and the usage of the commonly used multi-input Toffoli gates is avoided. This realization method of quantum cir-cuits is different from most of reversible circuits synthesis methods from the literature that use only high level quantum cost based on the number of quantum gates. Our synthesis approach applies to both standard and LNN quantum cost models. It leads to entirely new CAD algorithms for circuit synthesis and substantially decreases the quantum cost for LNN quantum circuits. The drawback of synthesizing circuits in the presented LNN architecture is the addition of ancilla qubits.
... rticular reversible gate is not fixed, but any output that is not used in a circuit in which the gate is used is labelled garbage outputs. Quantum cost (QC) refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated knowing the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit. [4] . These parameters have to be reduced while designing a reversible circuit. Some of the major problems with reversible logic synthesis are that fanouts cannot be used, and also feedback from gate outputs to inputs is not permitted. However fanout in reversible circuits is achieved using additional gates. A reversible circuit should be d ...
Reversible logic gates provide power optimization which can be used in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a new 3 * 3 reversible SRK gate that works as a reversible 2:1 Multiplexer and has a reduced quantum cost. A novel design of Reversible Universal Shift Register using SRK gates with reduced delay and quantum cost is proposed. Reduction of delay, which is a major factor contributing to the improvement of efficiency of the circuit is adequately taken care in all the components of the proposed design. Thus, this paper provides a threshold to build more complex sequential systems using reversible logic.
... That is to say, the number of inputs must be equal to the number of outputs [5]. It is inevitable that reversible logic circuit may have a number of unwanted outputs called garbage outputs [6]. Obviously, the influence is smaller in process of reversible circuit design when proposed circuit using fewer garbage outputs. ...
Reversible logic is a new rapidly developed research field in recent years, which has been receiving much attention for calculating with minimizing the energy consumption. This paper constructs a 4×4 new reversible gate called ZRQ gate to build quantum adder and subtraction. Meanwhile, a novel 1-bit reversible comparator by using the proposed ZRQC module on the basis of ZRQ gate is proposed as the minimum number of reversible gates and quantum costs. In addition, this paper presents a novel 4-bit reversible comparator based on the 1-bit reversible comparator. One of the vital important for optimizing reversible logic is to design reversible logic circuits with the minimum number of parameters. The proposed reversible comparators in this paper can obtain superiority in terms of the number of reversible gates, input constants, garbage outputs, unit delays and quantum costs compared with the existed circuits. Finally, MATLAB simulation software is used to test and verify the correctness of the proposed 4-bit reversible comparator.
... Therefore we have to add some garbage outputs to make it reversible. The minimum number of garbage outputs required for reversibility is ⎡ ⎤ log(q) , where q is the maximum number of times an output pattern repeated in the truth table [7]. In this case, 0 and 1 are repeated 4 times in the output column Q n+1 . ...
To construct a reversible sequential circuit, reversible sequential elements are required. This work presents novel designs of reversible sequential elements such as D latch, JK latch, and T latch. Based on these reversible latches, we construct the designs of the corresponding flip-flops .Comparing with previous work, the implementation cost of our new designs, including the number of gates and the number of garbage outputs is considerably reduced.
... Fig. 7: Detector part designed by Hafiz Carry out of the 4-bit binary adder in the first part of the BCD adder (Fig. 8). The Minimum number of required DC outputs is log 2 q, where q is the maximum number of repetition in the output patterns [10]. Truth table of the P equation shows that there are 11 repeated '1's in the outputs. ...
Reversible logic circuits have found emerging attention in nanotechnology, quantum computing and low power CMOS designs. In this paper we present a modular synthesis method to realize a reversible Binary Coded Decimal (BCD) adder/subtractor circuit. We use genetic algorithms and don't care concept to design and optimize all parts of a BCD adder circuit in terms of number of garbage inputs/outputs and the quantum cost. We have also developed and used genetic algorithm-based synthesis software to design and optimize proper circuits for a reversible BCD adder/subtractor such as full adder, reversible 9's complement generator and reversible multiplexer. The results show improvement in the quantum cost, the number of garbage inputs and outputs.
... In Ref [5] an algorithm was proposed for mapping Reversible Wave Cascades to reversible gates (more specifically Generalized Toffoli gates), although it was not implemented. A similar reversible architecture is described in [16], with major objective to minimize the number of garbage inputs, although at that time no algorithm for the mapping and minimization of an arbitrary function to such architectures had been proposed. In Ref [10] BDDs (Binary Decision Diagrams) along with variable reordering techniques are used to produce cellular arrays. ...
In this paper a theoretical background for the architecture of Re- versible Wave Cascades is discussed, as well as some minimization algo- rithms for this architecture. Moreover, heuristic algorithms are proposed for estimating the optimal (or near optimal) variable ordering of a switch- ing function, which drastically improves the simpliflcation results of those, previously mentioned, algorithms. The topology of Reversible Wave Cas- cades is useful because it has been proved to be reversible and moreover it may help in the design of quantum circuits.
... The garbage outputs must be added as necessary so that the output patterns are distinct, and it is not used for further computations. Of course, the constant garbage inputs must be added, as necessary, to balance the number of inputs and outputs [25]. Reduction of these quantum parameters is the bulk of the work in reversible circuits design. ...
Adders and multipliers are two main parts of arithmetic units of computer hardware and play an important role in reversible computations. This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced “Partial Product Generation Circuits” (PPGC) with Peres gates only without duplicating gates. Again, an optimized Peres full adder reversible gate is used in “Reversible Parallel Adder” (RPA) part with accompaniment with the carry save adder technique. The comparison of the proposed design with previous ones shows that the proposed reversible multiplier improves the quantum parameters. The proposed design shows lower quantum cost, depth with the help of a novel design in PPGC. The circuit cost of the proposed design is a little higher than the best compared design, but the proposed design shows the lowest total cost which is defined as sum of quantum cost and circuit cost. Moreover, the number of gates, garbage input and output has no change regarding to the best compared design. The proposed multiplier can be generalized as an n×n bit multiplication.
... Reversible circuit plays an important role in quantum computing[5,6]. There is a lot of research[7,8,4,6,[9][10][11][12][13][14][15][16][17][18]on the construction of reversible logic gates. A fundamental question on reversible logic is what kind of reversible circuits can be implemented, given a library of reversible logic gates. ...
Reversible circuits play an important role in quantum computing. This paper studies the realization problem of reversible circuits. For any n-bit reversible function, we present a constructive synthesis algorithm. Given any n-bit reversible function, there are N distinct input patterns different from their corresponding outputs, where N≤2n, and the other (2n−N) input patterns will be the same as their outputs. We show that this circuit can be synthesized by at most 2n⋅N ‘(n−1)’-CNOT gates and 4n2⋅N NOT gates. The time and space complexities of the algorithm are Ω(n⋅4n) and Ω(n⋅2n), respectively. The computational complexity of our synthesis algorithm is exponentially lower than that of breadth-first search based synthesis algorithms.
... Unfortunately, this synthesis method requires a large number of garbage bits which are expensive in some technologies , especially quantum. Authors of [8], [3], [9], [14] suggest regular synthesis methods, but they usually produce large networks when applied as formulated and are not asymptotically optimal. A multiple EXOR Toffoli gate (mEXOR) is defined analogously by allowing the target to be a set. ...
We propose a network of generalized Toffoli gates with mul-tiple EXORs for the realization of reversible functions. If implemented as a quantum circuit, the cost of such gates is shown to be only marginally higher than the cost of a Toffoli gate with a single EXOR and the same number of controls. The main result is a regular synthesis procedure which al-lows for the creation of asymptotically optimal reversible networks. However, asymptotic optimality does not neces-sarily mean absolute optimality. Thus, when the algorithm terminates, and a network is created, simplification proce-dures that may reduce the number of gates in the network can be applied.
Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors’ performance. A new scalable realization of quaternary reversible 4×1 multiplexer and 1×4 demultiplexer, based on quaternary 1-qudit Shift, 2-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversible
n
×1 multiplexer and 1×
n
demultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.
In this chapter, hardware implementation of an LSB replacement-based digital image watermarking algorithm is introduced. The proposed scheme is developed in spatial domain. In this watermarking process, data or watermark is implanted into the cover image pixels through an adaptive last significant bit (LSB) replacement technique. The real-time execution of the watermarking logic is developed here using reversible logic. Utilization of reversible logic reduces the power dissipation by means of no information loss. The lesser power dissipation enables a faster operation as well as holds up Moore's law. The experimental results confirm that the proposed scheme offers high imperceptibility with a justified robustness.
Progress made in quantum computation has resulted in logic synthesis with reversible circuits receiving considerable interest. This paper presents a synthesis of reversible array divider circuit based on non-restoring division algorithm implemented with k-CNOT gates. The execution time of such an array divider is low. Our aim is to propose a reversible array divider circuit which is efficient as regards to the number of garbage outputs and gates.
In this chapter, hardware implementation of an LSB replacement-based digital image watermarking algorithm is introduced. The proposed scheme is developed in spatial domain. In this watermarking process, data or watermark is implanted into the cover image pixels through an adaptive last significant bit (LSB) replacement technique. The real-time execution of the watermarking logic is developed here using reversible logic. Utilization of reversible logic reduces the power dissipation by means of no information loss. The lesser power dissipation enables a faster operation as well as holds up Moore's law. The experimental results confirm that the proposed scheme offers high imperceptibility with a justified robustness.
Reversible logic is an emerging technology with wide spread applications in the field of digital systems. The term RAM refers to memory that is accessed with an address and has latency independent of address. In semiconductor memories RAM usually refers to volatile memory read/write memory as opposed to ROM (read only memory). The 2 n ×2 m ×1 RAM has n rows and m columns, out of which one bit is selected as an output. The design of proposed ram requires write/read enabled FF for information read and write and address decoding circuit. The paper uses the reversible modified Frekdin gate to propose an address decoder and write enabled master slave D FF. The proposed designs are optimized in terms of quantum cost. The proposed designs are used for implementation of 2 n ×2 m ×1 reversible RAM. Several theorems related to Decoders and 2 n ×2 m ×1 reversible RAM are suggested and proved.
Reversible logic is one of the rising fields for low-power electronic devices. Testing of these devices is a significant issue where the researchers are at par with the latest innovations in the field. However, new technology gives birth to new challenges, and in this field too, several fault models have arisen. Several online testing methods have been proposed for their detection, which are scaled on various performance parameters. This paper provides a comparative study of online testability for reversible logic. We bring together a review of fault models, performance parameters and online testing strategies from the literature with the aim of obtaining a near optimal solution by efficiently exploring the entire search space. We critically analyze a range of online testing strategies reported by researchers using parity preservation and generation, dual-rail coding and concurrent error detection schemes. These strategies are presented in two broad classifications, namely designing with novel gates and designing with existing circuits. All the techniques are explained in detail with a brief mathematical illustration. A comparison of experimental results based on the available number of benchmarks and combinational logic circuits is presented. The best possible strategy is highlighted on behalf of performance parameters.
Quantum dot Cellular Automata (QCA) is an emerging technology for development of logic circuits based on nanotechnology, and is one of the alternative for designing high performance computing over existing CMOS-VLSI technology. QCA does not use voltage level for logic representation rather it represents binary state by polarization of electrons in the QCA Cell. Conventional logic circuits are irreversible in nature and always lead to energy dissipation. Thus extensive research is going on to design the circuits which does not dissipation the energy and hence will not loose the information. In this paper we have designed the QCA based toffoli gate and then implemented the basic logic gates with it. The circuits were successfully simulated and verified by QCA Designer tool.
With the advancement of nanometer scale design technology, transient faults often occur in circuits and thus require low power dissipation design. Reversible logic has become one of the recent emerging research interests contributing to the field of low power dissipating circuit design in the past few years. Few of its application areas include CMOS low power design, quantum computing, network security, digital signal and image processing, optical electronics and nanotechnology. This paper presents a comparative study of efficacy of various reversible full adder and reversible full subtractor gate and their quantum cost values to obtain energy efficient logic design. A novel design approach for implementing reversible combinational circuits using the existing Reversible logic gates and new improved Reversible logic gates is discussed in this paper. The reversible logic circuits are designed and implemented using Verilog code. The simulation results are obtained in Xilinx ISE version 9.2i.
This chapter introduces an evaluation of the implementation of the reversible structures that have been presented in Chap. 3 to realize logic functions. This evaluation gives an important first look to some of the weaknesses, strengths, and properties of the previously introduced reversible structures.
This chapter is devoted to the basic information and definitions required to travel around the reversible logic world safely. First, some preliminary concepts of reversible logic are introduced in Sect. 2.1. Basic and important definitions in reversible logic are explained in Sect. 2.2. Next the three most commonly used reversible gates of Feynman, Toffoli and Fredkin are presented in Sect. 2.3. The following Sect. 2.4 introduces interesting heuristics for reversible logic synthesis. Literature review of reversible logic synthesis methods is given in Sect. 2.5. As in everyday life everything has its price. The price of reversibility is the “garbage” outputs which are not allowed in quantum computing and have to be eliminated as explained in Sect. 2.6.
Communication in today's world is made efficient by digital data transmission. The digital communication employs parity generator at the source and parity checker at destination to ensure an error free transmission. This paper proposes the design of a 3-bit reversible even parity checker and generator using the basic reversible gates. The parity checker and generator circuit is designed using the existing basic reversible gates like Feynman gate, Toffoli gate, Peres gate and New gate and the performance of the designed parity checker and generator is discussed. The proposed design is designed using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3.
We introduce the concept of the Information Preserving Logic (IPL) based on some of the properties of reversible logic. The proposed IPL is using reversibility to dynamically recover inputs or intermediary product terms and to adaptively reconfigure itself to either a memory block or to logic processing circuit. We show that using these principles and the proposed computational model several problems in the current logic technology (such as CMOS), can be solved. In particular we show possible improvements to the heat dissipation in the Cache-CPU system, register number reduction in a computational pipeline, reversible encoding and compression and the design of the so called Universal Reversible Logic cell. Finally, to show that the logical reversibility alone can be used to implement the introduced concepts in the current technology, a Toffoli gate is implemented using adiabatic CMOS and compared to non adiabatic Toffoli gates. It is shown that our implementation of the Toffoli gate, saves power and registers when used in the reversible concepts introduced above.
Reversible logic circuits are of high interests to calculate with minimum energy consumption having applications in low-power CMOS design, optical computing and nanotechnology, especially in quantum computer. Quantum computer requires quantum arithmetic. A new design of a reversible arithmetic logic unit (reversible ALU) for quantum arithmetic has been proposed in this article. As we known, ALU is an important part of central processing unit (CPU) as the execution unit. So this article provides explicit construction of reversible ALU effecting basic arithmetic operations. By provided the corresponding control unit, the proposed reversible ALU can combine the classical arithmetic and logic operation in a reversible integrated system. This article provides a new more powerful ALU which contains more functions and it will make contribute to the realization of reversible Programmable Logic Device (RPLD) in future using reversible ALU.
Quantum-dot cellular automata (QCA) technique is one of the emerging and promising nanotechnologies. It has considerable advantages versus CMOS technology in various aspects such as extremely low power dissipation, high operating frequency and small size. In this paper, designing of a one-bit full adder is investigated using a QCA implementation of Toffoli and Fredkin gates. Then, a full adder design with reversible QCA1 gates is proposed regarding to overhead and power savings. Our proposed full adder design is more preferable when considering both circuit area and speed. The proposed design uses only two QCA1 gates and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells.
Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware and also identifying the faulty module by a proposed Reversible QCA comparator circuit. Triple Module Redundancy (TMR) mechanism is implemented for Reversible QCA circuits to make them more Reliable. Our proposed Comparator and Detector design uses the minimum number of clocking zones and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells. QCA Designer ver.2.0.3 is used for simulation and verifying the design.
Reversible circuits play an important role in quantum computation. The realization of reversible quantum circuits is required for any quantum computer to be universal. This paper1 studies the realization and synthesis problem of reversible circuits. Using group theory, we present two sets of new 3-bit reversible logic gates, which included g1g2g3 and nine complex gates, respectively. It is shown that any 3-bit reversible logic circuit is realizable by cascading NOT and Feynman gates, and at most one instance of our proposed gates. Given any n-bit reversible function, there are N distinct input patterns different from their corresponding outputs, where N ≤ 2n, and the other (2n - N) input patterns will be the same as their outputs. According to a synthesis example, it demonstrates that the main results are constructive and practical than others.
Reversible logic is one of the ways for power optimization. The produced circuits using these gates are applied in nanotechnology, bioinformatics, quantum computing and DNA. In this paper, we propose a fault tolerant reversible 4-Bit binary counter with parallel load. This is a robust and first attempt for designing a fault tolerant reversible 4-Bit binary counter with parallel load. Counters are important components in computers. Most counters are synchronous in computer systems. Some of these counters can also be made from D-Flip Flops. Counters can be designed to generate any desired sequence of states. The sequence may follow the binary count or may be any other arbitrary sequence. In this study, we propose three approaches of the fault tolerant reversible circuits for 4-Bit binary counter with parallel load. Total logical calculation and Total quantum cost of the second approach is less than the previous approaches. Third approach is implemented using Unit 3 gate. The constant inputs and the garbage outputs of its circuit is less than the mentioned approaches. All the scales are in the nanometric area. The proposed circuits can be applied for constructing more complex systems in nanotechnology.
A set of p-valued logic gates (primitives) is called universal if an arbitrary p-valued logic function can be realized by a logic circuit built up from a finite number of gates belonging to this set. In the paper, we consider the problem of determining the number of universal single-element sets of ternary reversible logic gates with two inputs and two outputs. We have established that over 97% of such sets are universal.
The work starts with a general idea of how to realize a dynamic programming algorithm as a quantum circuit. This realization is not tied to a specific design model, technology or a class of dynamic algorithms, it shows an approach for such synthesis. As an illustration of the efficiency of this approach, the class of all multiple-output symmetric functions is realized in a dynamic programming algorithm manner as a reversible circuit of Toffoli type elements (NOT, CNOT, and Toffoli gates). The garbage and quantum cost (found based on Barenco et al. paper) of the presented implementation are calculated and compared to the costs of previously described reversible synthesis methods. The summary of results of this comparison is as follows. The quantum cost of the proposed method is less than the quantum cost of any other reported systematic approach. The garbage is usually lower, except for comparison with the synthesis methods, whose primary goal is synthesis with theoretically minimal garbage. The presented algorithm application to the symmetric function synthesis results in circuits suitable for quantum technology realizations.
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