Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V

Abstract

Carbon nanotube (CNT) based integrated circuits (ICs) including basic logic and arithmetic circuits were demonstrated working under a supply voltage low as 0.4 V, which is much lower than that used in conventional silicon ICs. The low limit of supply voltage of the CNT circuits is determined by the degraded noise margin originated from the process inducing threshold voltage fluctuation. The power dissipation of CNT ICs can be remarkably reduced by scaling down the supply voltage, and it is of crucial importance for the further developments of nanoelectronics ICs with higher integration density.

Full text

Carbon nanotube based ultra-low voltage integrated circuits: Scaling down
to 0.4V
Li Ding, Shibo Liang, Tian Pei, Zhiyong Zhang, Sheng Wang et al.
Citation: Appl. Phys. Lett. 100, 263116 (2012); doi: 10.1063/1.4731776
View online: http://dx.doi.org/10.1063/1.4731776
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Published by the American Institute of Physics.
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Carbon nanotube based ultra-low voltage integrated circuits:
Scaling down to 0.4 V
Li Ding,
1
Shibo Liang,
1
Tian Pei,
1
Zhiyong Zhang,
1,a)
Sheng Wang,
1
Weiwei Zhou,
2
Jie Liu,
2
and Lian-Mao Peng
1,a)
1
Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics,
Peking University, Beijing 100871, China
2
Department of Chemistry, Duke University Durham, North Carolina 27708, USA
(Received 14 May 2012; accepted 12 June 2012; published online 29 June 2012)
Carbon nanotube (CNT) based integrated circuits (ICs) including basic logic and arithmetic circuits
were demonstrated working under a supply voltage low as 0.4 V, which is much lower than that
used in conventional silicon ICs. The low limit of supply voltage of the CNT circuits is determined
by the degraded noise margin originated from the process inducing threshold voltage fluctuation.
The power dissipation of CNT ICs can be remarkably reduced by scaling down the supply voltage,
and it is of crucial importance for the further developments of nanoelectronics ICs with higher
integration density. V
C2012 American Institute of Physics.[http://dx.doi.org/10.1063/1.4731776]
Carbon based nanoelectronics are officially recom-
mended by the International Technology Roadmap for Semi-
conductor (ITRS) in 2009 as the most promising technology
for further electronics to extend the Moore law. In particular,
carbon nanotube (CNT) is an exceptionally good electronic
material with extremely high carrier mobility, long mean
free length, and the smallest body, which may potentially
bring the CNT based field-effect transistors (FETs) and inte-
grated circuits (ICs) outstanding performances, including
high speed and low power dissipation.
1–3
After about
15 years development, various kinds of basic logic gates,
arithmetic and control circuits have been realized on
CNTs,
4–14
and extensive investigations have been carried out
to explore the potential advantages of CNT based electronics
over Si complementary-metal-oxide-semiconductor (CMOS)
technology.
15–22
Among these, the speed of CNT devices and
circuits has attracted the most attentions.
15,16,18–22
In con-
trast, only few investigations have been carried out on power
dissipation which is in fact equally important performance
metric in modern ICs and is becoming even more important
with increasing integration level.
23–26
Since both the static
power and dynamic power will decrease with decreasing
supply voltage, an effective way to reduce power dissipation
is to scale down the supply voltage of the circuit.
25,26
It is
therefore highly desirable to explore the supply voltage scal-
ing limit of CNT-based ICs and to assess the potential
advantage of CNT based ICs on power dissipation. In previ-
ously developed CNT-based ICs, supply voltages much
larger than 1 V were usually used due to the uncontrolled
threshold voltage of constituent devices.
4–11,13,14
In this let-
ter, we aim to investigate the supply voltage scaling down
behaviors of CNT-based ICs. We show that, with properly
controlled low threshold voltages near zero both for n-type
and p-type FETs, CNT-based ICs with gate length about
1lm can operate normally with a supply voltage low as
0.4 V, suggesting the potential advantage of CNT based ICs
on power dissipation over silicon CMOS circuits with similar
gate length.
The CNT FETs and circuits were fabricated on individual
ultra-long semiconducting CNTs which were directionally
grown on a silicon substrate and identified via field-effect
measurements using the substrate as the back gate. A doping-
free process
9,12
was used to manufacture CMOS FETs
with self-aligned gate structure.
27
Briefly, the source and drain
(S/D) contacts for p-type CNT FETs were formed using Pd
film
28
with thickness of 80 nm via electron beam lithography
(EBL), electron beam evaporation (EBE), and a subsequent
standard lift-off process. Windows were predefined for gates
of p-FETs using EBL, and gate stacks consisting of HfO
2
/Pd
were grown by atomic layer deposition (ALD) and EBE. The
p-type CNT FETs were finished after patterning the gate-
stacks through another lift-off process. The n-type FETs were
fabricated subsequently via fabrication processes similar to
those used for p-type FETs, except that high-quality Sc was
used instead of Pd as S/D contacts.
29
All FETs in this work
were designed with channel length (or gate length) of 1 lm.
At last, according to the requirements of the designed
circuits, FETs were connected to form integrated circuits
through Ti/Au wires, which were patterned and deposited
using EBL and EBE. Basic logic and arithmetical circuits
were constructed, in which the NOT gate or inverter is in the
CMOS style; OR, AND, and semi-adder were designed with
pass-transistor-logic (PTL) style.
12
Devices and integrated cir-
cuits were measured in atmosphere using a probe station,
semiconductor analyzer, and signal sources.
We first considered a CMOS inverter, since it is the ba-
sic logic gate in digital ICs. The inverter was fabricated
using a pair of p-type and n-type CNT FETs and the well-
developed self-aligned gate structure.
9,27
The schematic dia-
gram and top-view scanning electron microscopy (SEM)
image are shown in Figs. 1(a) and 1(b), respectively. Trans-
fer characteristics of the inverter were measured at different
supply voltages between 1 V and 0.4 V with step of 0.1 V,
but only four curves are shown in Fig. 2(a) for clarity. Volt-
age gains for different supply voltages are calculated and
plotted as a function of V
in
in Fig. 2(b). The maximum
a)
Authors to whom correspondence should be addressed. Electronic
addresses: zyzhang@pku.edu.cn and lmpeng@pku.edu.cn.
0003-6951/2012/100(26)/263116/5/$30.00 V
C2012 American Institute of Physics100, 263116-1
APPLIED PHYSICS LETTERS 100, 263116 (2012)
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voltage gain for all supply voltages is always larger than 10,
and can reach up to 38 at supply voltage of 0.6 V. A rea-
sonable gain of 34 at supply voltage of 0.4 V demonstrates
the potential applications of CNTFETs in low operating volt-
age circuits. If only voltage gain is considered, the perform-
ance of the inverter is much better at low bias than at high
supply voltage. Moreover, obvious jitters are observed espe-
cially at the transition region in transfer curves at high sup-
ply voltages such as 0.8 V or 1 V, which spread voltage gain
region and lower the maximum gain. But when the inverter
is powered at lower supply voltage, the transfer curves
become smoother at the transition region, leading to a more
abrupt transition region and thus larger voltage gain than that
at higher supply voltages. The jitters may be attributed to the
dynamic processes of carriers in the CNT channel which tun-
nel into/out charge traps in surrounding dielectric layer.
30,31
The dynamic processes can affect the electrostatic potential
of the CNT channel instantaneously and induce random
changes in the transport properties of CNT FETs. It is well
known that the kinetic energy of carriers in CNT channel
increases with supply voltage, and the tunneling probability
of carriers into/out a charge trap increases with gate voltage
and drain voltage. Therefore, the jitters prefer to appear in
the transfer curves at high supply voltage other than at low
supply voltages. As a result, the scaled supply voltage can
lead to lower electric noise in logic gates.
Once the supply voltage of the inverter is scaled down,
the noise margin (NM) is becoming the primary concern and
may eventually determine the low limit of supply vol-
age.
25,26
Since the normal techniques appearing in some pop-
ular textbooks
23,24
for extracting noise margin do not give
reliable values for a broad range of transfer characteristics,
especially for non-ideal transfer characteristics, the well
developed area technique is more suitable to give reliable
noise margin values for CNT CMOS inverter.
32
To extract
noise margin, butterfly shape transfer curves were obtained
by emulating two back to back connected inverters,
32
i.e.,
transfer curves with exchanged V
in
-V
out
were added to the
original ones as shown in Fig. 2(c). The best way to charac-
terize noise margin is by maximizing the area of a rectangle
within the transfer function loop, and then the reliable noise
margin values of the CNT inverter are determined as shown
in Fig. 2(c). At supply voltage V
dd
¼1.0 V, the NMs are
large with NM
H
¼0.34 V for the high voltage state and
NM
L
¼0.49 V for the low voltage state. When the supply
voltage is scaled down to 0.4 V, NM
H
and NM
L
are reduced
to 0.06 V and 0.25 V, respectively. It should be noted that the
degraded NM
H
of as low as 0.06 V suggests a small energy
range of about 2.4 kT/q (kT/q is the electron thermal energy)
for the high voltage state and a weak immunity from the dis-
turbance of the inverter. Figure 2(d) shows the supply
voltage-dependent relative noise margins, i.e., noise margins
normalized by the supply voltage. As the supply voltage is
scaled from 1 V down to 0.4 V, the normalized low noise
margin NM
L
increases from 49% to 62% while the normal-
ized high noise margin NM
H
decreases from 34% down to
15%. Since further lowering supply voltage may bring NM
H
below 15%, the scaling limit of the supply voltage is actually
set by the noise margin of the inverter. It is well known that
the asymmetry between NM
L
and NM
H
is induced by the
asymmetric performance between n-type and p-type FETs,
which results from fluctuations in device performance and
may be reduced by optimizing the fabrication process. In
principle, it is possible to push the supply voltage of the in-
verter to a value much lower than 0.4 V if the uniformity of
FETs is further improved.
To characterize the power dissipation level of the in-
verter, transient currents are plotted as a function of input
voltage in Fig. 2(e) for different supply voltages. It is
obvious that the transient current is remarkably reduced
when the supply voltage is scaled down. The transient cur-
rent reaches its peak value in the transition region and is
thereafter referred as the switching current. Figure 2(f)
shows the supply voltage dependent switching currents for
two inverters, in which the data denoted as blue diamond
were measured from the same inverter as that of Figs.
2(a)–2(e). It is worth noting that the switching current is low-
ered by more than two orders of magnitudes, i.e., from 40
nA down to 0.2 nA, when scaling supply voltage from 1 V
down to 0.4 V, demonstrating the big benefit achieved on
power dissipation through scaling down supply voltage.
While the switching current is a good metric for evaluating
circuit static power dissipation, most power is dissipated dur-
ing the charging and discharging of the circuit and can be
estimated by
23,24
P¼CVdd2f;(1)
in which Cis the gate capacitance of the FET and fis the
clock frequency. For our FETs with a CNT diameter of
approximately 1.8 nm, a gate length of 1 lm and gate dielec-
tric (HfO
2
) thickness of 12 nm, Cis approximately 170 aF.
Equation (1) clearly shows that the power dissipation of a
logic gate is proportional to V
dd
2
, which may be significantly
reduced by scaling down V
dd
. For example, it can be reduced
down to 27 pW/gate/MHz at V
dd
¼0.4 V when the power
FIG. 1. (a) Schematic and (b) SEM image of a CNT based CMOS inverter
with a pair of p- and n-FETs.
263116-2 Ding et al. Appl. Phys. Lett. 100, 263116 (2012)
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dissipation is 170 pW/gate/MHz at V
dd
¼1 V. If the gate
length is further scaled down to 20 nm, similar to that used in
the state-of-the-art 32 nm Si CMOS devices,
33
the power dis-
sipation may be further lowered to 0.5 pW/gate/MHz,
which is much smaller than that of the best silicon nanowires
(NWs) based CMOS inverter.
33
The significant advantage of
CNT based inverter on power dissipation over the Si-based
NWs inverter is mainly benefitted from the small gate capac-
itance of the CNT channel. We can conclude therefore that,
considering power dissipation, including both short circuit
static and dynamic charging/discharging power dissipation,
significant savings are anticipated from using CNT as the
channel material and scaling down supply voltage.
Scaling down the supply voltage brings three changes:
(1) increases voltage gain or reduces electric noise, (2)
decreases power dissipation, and (3) degrades noise margin.
Increasing voltage gain and decreasing switching current are
positive aspects resulting from scaling supply voltage, while
degrading noise margin brings negative aspect and will
finally set the scaling limit of the supply voltage. The CNT-
based inverter can operate normally under supply voltage
down to 0.4 V. This is because the threshold voltages both
for n-type and p-type FETs were controlled to center at zero
within 0.4 V to 0.4 V in our doping-free fabrication
process.
12
It is worth mentioning that 0.4 V is an ultra-low
supply voltage, especially for logic gates consisting of FETs
with gate length of 1 lm. As a reference, Si-based ICs with
similar gate length were generally powered by supply volt-
age of about 5 V.
25
Even for the state-of-the-art 32 nm Si
CMOS ICs, the supply voltage is typically larger than
0.6 V.
34,35
To learn more about the voltage scaling behavior of our
CNT based digital ICs, it is necessary to explore the scaling
behavior of other typical logic gates, such as AND and OR
gates which are also important basic logic gates widely used
in digital ICs. Both AND and OR gates are designed with
pass-transistor logic style,
12
and each consists of a pair of
p-type and n-type CNT FETs. Both AND and OR gates were,
respectively, measured under a series of V
dd
including 1 V,
0.8 V, 0.6 V, and 0.4 V. In order to weight the perfect degree
of output voltage at different supply voltages, the output vol-
tages are normalized by the supply voltage V
dd
for all four
input combinations and shown in Figs. 3(a) and 3(b). For the
AND gate, the measured normalized outputs follow the
standard AND logic functions and remain almost perfect at
both “1” and “0” levels when V
dd
is scaled from 1 V down to
0.4 V. For the OR gate, the measured normalized outputs also
follow the standard OR logic functions, but the output corre-
sponding to the input combination (0, 1) is not perfect “1”
owing to the performance fluctuation of constituent FETs.
FIG. 2. Characteristics of CNT FET-based
CMOS inverter. (a) Transfer characteristics
of the inverter at different supply voltages
V
dd
scaled from 1 V down to 0.4 V. (b)
Input V
in
-dependent voltage gain under dif-
ferent V
dd
. (c) Transfer characteristics at
different V
dd
with V
in
and V
out
plotted inter-
changeably on X and Y axis. (d) Relative
noise margins (normalized by V
dd
) plotted
against V
dd
. (e) V
in
dependent transient cur-
rent under different V
dd
values. (f) Switch-
ing current of the inverter plotted against
V
dd
.
263116-3 Ding et al. Appl. Phys. Lett. 100, 263116 (2012)
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The normalized output for the input combination (0, 1) is
approximately 0.83 at V
dd
¼1 V, and further degraded as V
dd
is scaled down. At the lowest supply voltage of V
dd
¼0.4 V,
the normalized output becomes as low as 0.69 but is still far
above 0.5, suggesting that the circuit is still operating prop-
erly at a supply voltage not higher than 0.4 V.
In addition to logic gates, arithmetic circuits are also im-
portant components of modern digital computers. As a typi-
cal arithmetic circuit, semi-adder circuit is chosen here to
explore the supply voltage scaling behavior of CNT-based
arithmetic circuits. The CNT semi-adder circuit was fabri-
cated based on CNT-FETs and designed with PTL style, and
consists of two n-type and two p-type FETs as shown in Fig.
3(c). In fact, the circuit is constructed by combining a XOR
logic
12
and an AND logic gate as shown in Fig. 3(c), where
the output of the XOR is used as the SUM, the output of the
AND gate as the carry-out C
O
, and the truth table of the so
constructed circuit is identical to that of a semi-adder as
shown in Fig. 3(d). The measured normalized outputs for all
four input combinations of (A, B,) are shown in Figs. 3(e)
and 3(f). Both Sum and C
O
agree with the truth table of the
semi-adder for all different supply voltages between 1 V and
0.4 V, demonstrating that a semi-adder circuit with a supply
voltage as low as 0.4 V was realized on CNT. It should also
be noted that, comparing to the almost ideal logic levels of
C
O
, some voltage levels of SUM are degraded. For example,
the output voltages corresponding to input combinations of
(0, 1) and (1, 1) are far from the voltage levels they should
be. In particular, as shown in Fig. 3(e), the normalized output
for input combination of (1, 1) increases with reducing sup-
ply voltage and reaches up to 0.31 for logic “0” at
V
dd
¼0.4 V, and further scaling down V
dd
is expected to
push the “0” level even higher.
As the supply voltage is scaling down, the degraded out-
put states (e.g., some SUM states) owing to devices perform-
ance fluctuations are further degraded while those almost
perfect output states (e.g., most C
O
states) remain basically
perfect. The signal degradation mainly originates from fluc-
tuations in the threshold voltages V
th
of the CNT FETs used
in the circuit, and the effect of V
th
fluctuations will further
increase with deceasing supply voltage. The threshold vol-
tages are controlled in current level of fabrication technology
to lie between 0.4 V and 0.4 V, which results in a lower
limit of our CNT circuit supply voltage to be about 0.4 V.
Therefore, in this regime, the limit of supply voltage is deter-
mined mainly by the distributions of the threshold voltages
V
th
of the CNT FETs, which can in principle be further
improved by optimizing the fabricating process.
In summary, carbon nanotube based integrated circuits
were fabricated through a doping-free process, and their sup-
ply voltage scaling down behaviors have been investigated.
For a CMOS inverter, benefitted from scaling supply voltage,
the power dissipation is shown to decrease tremendously and
the voltage gain to increase with reducing supply voltage.
The low limit of the supply voltage is mainly determined by
the degraded noise margin originating from process induced
threshold voltage variations. Owing to the threshold voltages
near to zero for the constituent CMOS FETs, CNT-based ICs
including basic logic gates, such as NOT, OR, and AND, as
well as a basic arithmetic gate, such as semi-adder, have
been demonstrated to operate normally under supply voltage
down to 0.4 V.
This work was supported by the Ministry of Science and
Technology of China (Grant Nos. 2011CB933001 and
2011CB933002) and the National Science Foundation of
China (Grant No. 61071013). Work at Duke is in part sup-
ported by a grant from ONR (N00014-09-1-0163) and a
grant from RF nano Inc. J.L. and W.Z. also acknowledge the
Shared Materials Instrumentation Facility (SMIF) at Duke
University for access to their instrumentation.
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