No full-text available
To read the full-text of this research,
you can request a copy directly from the author.
A Universal Architecture for Multiple-Valued Reversible Logic
Abstract
A modified form of Fredkin gate can be used to design any multi-valued combinational and sequential logic system [P. D. Picton, “Modified Fredkin gates in logic design”, Microelectronics J. 25, 437-441 (1994); Mult.-Valued Log. 1, 241-251 (1996; Zbl 0865.94034)]. Not only is this gate universal but it is also reversible, and can therefore be used to construct any reversible multi-valued logic circuit. The “sum-of-products” architecture for multi-valued systems provides a convenient design that is independent of the radix. This paper shows that a version of the “sum-of products” architecture can be implemented using modified Fredkin gates.
... Quantum technologies [57,77,62,31,32,30,35,68,69] are not the only ones that may (naturally) use reversibility, there are other technologies for which reversible implementations are known. Specifically, it was shown that reversible gates can also be built using technologies such as CMOS [46,83,10,86], in particular adiabatic CMOS [3], optical [63,65], thermodynamic technology [48], nanotechnology [46,47], and DNA technology [65]. The billiard ball model [14,6] is a model for reversible computations, which among others, was simulated with reversible cellular arrays [38]. ...
... Quantum technologies [57,77,62,31,32,30,35,68,69] are not the only ones that may (naturally) use reversibility, there are other technologies for which reversible implementations are known. Specifically, it was shown that reversible gates can also be built using technologies such as CMOS [46,83,10,86], in particular adiabatic CMOS [3], optical [63,65], thermodynamic technology [48], nanotechnology [46,47], and DNA technology [65]. The billiard ball model [14,6] is a model for reversible computations, which among others, was simulated with reversible cellular arrays [38]. ...
... 8. Synthesis of regular structures such as nets [60,61], lattices [2], and PLAs [65]. 11. ...
... It was shown that reversible gates can be built in CMOS [5][6], DNA [19], optical and other technologies, and that all quantum logic gates are reversible [20]. A challenging goal might be to develop a system to synthesize reversible implementations of Boolean functions and state machines. ...
... In another line of research, the concepts of regular structures, such as PLAs [19], 2-dimensional lattices [15][16], three-dimensional lattices and nets were adapted to reversible logic. The methods based on decision diagrams have been proposed, as well as composition and decomposition methods [16][9]. ...
... According to [2], it is a necessary condition to use only reversible gates to build a logic circuit that does not consume energy 1 . It was shown that reversible gates can be built in CMOS [5][6], DNA [19], optical and other technologies, and that all quantum logic gates are reversible [20]. A challenging goal might be to develop a system to synthesize reversible implementations of Boolean functions and state machines. ...
A circuit is reversible if it maps each input vector into a unique output vector, and vice versa. Reversible circuits lead to power-efficient CMOS implementations. Reversible logic synthesis may be applicable to optical and quantum computing. Minimizing garbage bits is the main challenge in reversible logic synthesis. This paper introduces an algorithm to generate the cascade of reversible complex Maitra terms (called here reversible wave cascade) implementing incompletely specified Boolean functions. The remarkable property of the presented method compared to other reversible synthesis methods is that it creates at most one constant input and no additional garbage outputs. Preliminary estimation suggests that the method may be applicable to small and medium-sized benchmarks.
... A good synthesis algorithm for reversible logic (RL) should not create an excessive " garbage " [17] or " waste of outputs " . Based on our previous research, we found that there is a very good " match " between the requirements of reversible logic [2,4,9,11,12,14,17,18,33,43,44] and the opportunities given by the regular logic/layout structure [46] and Linearly Independent Logic [47,48]. We believe that regular structures are good for reversible logic, because it is easier to re-use in them the additional outputs of reversible gates, instead of " wasting " them. ...
... This is a very bad approach to synthesis, especially for future technologies -remember the " curse of wiring " which will dominate future technologies, with most of chip area occupied by connections, unless cellular-like logic and layouts are used. Thus, efforts in reversible logic design so far were mostly on designing practical reversible circuits, but there are some publications that attempt at creating general synthesis methods [9,11,17,18,3132333439,43,45]. The weaknesses of these methods fall to one or more of the following categories: -they assume that all gates are the same -they assume cascades of gates or two-dimensional circuits based on cascades, which leads often to complex realizations with large garbage. ...
... It was introduced by Ed Fredkin and Tomasso Toffoli in 1982 [17]. Fredkin Gate has been realized or proposed to be realized in various technologies: – optical: [5], [37], [31], [33], – electrical (CMOS): [5,6,,7,8,10,11,13,26], – mechanical (nano-technology): [27]. – quantum: [38,42,30,53]. ...
Reversible logic is of increasing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2*2 net structure, allows for a more efficient realization of symmetric functions than the methods introduced by the other authors. Our synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little “garbage”. Because every Boolean function can be made symmetric by repeating input variables, our method is applicable to arbitrary multi-input multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of additional gate outputs. The method can also be used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs
... Multivalued reversible gates however have not got much attention until recent times. In [8,9,10,11,12] we find some proposed some gates and some synthesis techniques. In this paper we concentrate on the multiple-valued Fredkin gates proposed by Picton in [11,12]. ...
... In [8,9,10,11,12] we find some proposed some gates and some synthesis techniques. In this paper we concentrate on the multiple-valued Fredkin gates proposed by Picton in [11,12]. The organization of the paper is as follows: Section 2 describes the reversible logic, different gates, and the MVFG. ...
... Multi-valued Fredkin Gate (MVFG) was proposed by Picton in [11,12]. In [11] he suggested as it is possible to implement any Boolean logic function using Fredkin gates then it is also possible using MVFGs as they are modified Fredkin gates. ...
Multi-valued Fredkin gates (MVFG) are reversible gates and they can be considered as modified version of the better known reversible gate the Fredkin gate. Reversible logic gates are circuits that have the same number of inputs and outputs and have one-to-one and onto mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vectors of output states. It has been shown that for power not to be dissipated in an arbitrary circuit it is necessary that the circuit be build from reversible gates. Moreover multi-valued Fredkin gates have been shown to be a suitable choice as a basic building block for binary and different alternative logics for example multi-valued logic and threshold logic. In this paper we show the application of MVFGs in the implementation of fuzzy set and logic operations. Fuzzy relations and their composition is very important in this theory as collections of fuzzy if-then rules and, fuzzy GMP (Generalized Modus Ponens)and GMT (Generalized Modus Tollens) respectively is mathematically equivalent to them. In this paper we describe digitized fuzzy sets where the membership values are discretized and represented using ternary variables and the implementation of set operations. The composition of fuzzy relations and a systolic array structure to compute it is described. Design with reversible gates and the highly parallel architecture of systolic arrays makes the proposed circuits quite attractive for implementation.
... Universality of n-qudit gates was discussed in [13,14] but no design algorithms were given. Picton [15] presented an approach called Universal Architecture for multi-valued reversible logic but this approach produces circuits that are far from minimum and have no relation to quantum realization. Since 2001 Al-Rabadi et al proposed Galois Field approach to quantum logic synthesis (see [1,2]). ...
... Thus we have (15). Similarly, by substituting the other parts of (2), (3), and (4) in (5) and after some manipulation, we can prove (16) to (20) ...
Ternary Galois Field Sum of Products (TGFSOP) expressions are found to be a good choice for ternary reversible logic and particularly for quantum cascaded realization of ternary functions. In this paper, we propose 5 ternary shift operations and various basic and composite ternary literals for defining TGFSOP expression. We propose 16 Ternary Galois Field Expansions (TGFE) using these literals and three new types of Ternary Galois Field Decision Diagrams (TGFDD) using the proposed expansions, which are useful for reversible and quantum logic design. We also propose a heuristic for creating optimal Kronecker TGFDD and methods for flattening the TGFDDs for determining near-minimum TGFSOP expressions. Besides, we propose quantum realizations for the 5 ternary Shift gates and a ternary swap gate. We also propose a new generalization of ternary Toffoli gates with their implementation from truly realizable 2-qudit quantum primitives. Further, we propose a method of synthesizing multi-output TGFSOP using cascade of ternary Shift gates, Swap gate, and generalized Toffoli gate. Finally, we present experimental results to show the complexity of the decision diagrams, the resultant TGFSOP expressions, and the new quantum cascade for some ternary benchmark functions.
... As the truly low-power circuits (with power arbitrarily small) cannot be built without the concept of reversible logic, various technologies for reversible logic are recently intensively studied. These technologies include: (i) standard CMOS [5] [6], (ii) optical technologies [7] [8], (iii) quantum logic technologies [9] [10], (iv) DNA technology, and (v) mechanical technology (nanotechnology) [11]. ...
... As the truly low-power circuits (with power arbitrarily small) cannot be built without the concept of reversible logic, various technologies for reversible logic are recently intensively studied. These technologies include: (i) standard CMOS [5, 6], (ii) optical technologies [7, 8], (iii) quantum logic technologies [9, 10], (iv) DNA technology, and (v) mechanical technology (nanotechnology) [11]. Many binary universal reversible logic gates have been proposed [5,12131415. ...
Reversible circuits are currently on of top approaches to power minimization and the one whose importance will be only growing with time. In this paper, the well known Feynman gate is generalized to k*k gate and a new generalized k*k family of reversible gates is proposed. A synthesis method for multi-output SOP function using cascades of the new gate family is presented. For utilizing the benefit of product sharing among the output functions, two graph-based data structures are used. Another synthesis method for AND-OR-EXOR function using cascades of the new gate family and generalized Feynman gate is also presented. Synthesis method for single-output ESOP function using cascades of the new gate family is also presented. All these synthesis methods are technology independent and generate very few garbage outputs and need few input constants.
... The gates considered here are not the only possible MVL reversible gates nor are they the only possible extension to the Toffoli gate. Picton [6,7] introduced an MVL generalization of the binary Fredkin gate. Al-Rabadi [8] has considered a generalization of the Toffoli gate where EXOR is replaced by mod-sum. ...
An r-valued m-variable reversible logic function maps each of the rm input patters to a unique output pattern. The synthesis problem is to realize a reversible function by a cascade of primitive reversible gates. In this paper, we present a simple heuristic algorithm that exploits the bidirectional synthesis possibility inherent in the reversibility of the speciflcation. The primitive reversible gates considered here are MVL extensions of the well-known binary Tofioli gates. We analyze the structure of the gates that we use and show how these gates can be easily simulated in a quantum technology. We present exhaustive results for the 9! 2-variable 3-valued reversible functions comparing the results of our algorithm to optimal results found by breadth-flrst search. We also show results for speciflc ternary examples including showing how the presented technique can be applied to the synthesis of a 3-input, 3-valued adder which is not itself a reversible problem. When the circuit for the full adder is synthesized, we use it as an example of an approach to a circuit simpliflcation, called the templates tool. Formalization and proper investigation of the templates simpliflcation tool proposed in this paper is still under investigation.
... While in [3] the structure of a multi-valued logic gate is proposed which is experimentally feasible with a linear ion trap scheme for quantum computing; this approach can produce large dimensional circuits. A universal architecture for multi-valued reversible logic is given in [4] , but quantum realization of the circuits thus obtained is not apparent. The universality of n-qudit gates is presented in [5], but no algorithms for synthesis were given. ...
Synthesis of quaternary quantum circuits involves basic quaternary gates and
logic operations in the quaternary quantum domain. In this paper, we propose
new projection operations and quaternary logic gates for synthesizing
quaternary logic functions. We also demonstrate the realization of the proposed
gates using basic quantum quaternary operations. We then employ our synthesis
method to design of quaternary adder and some benchmark circuits. Our results
in terms of circuit cost, are better than the existing works.
... Reversible circuit plays an important role in quantum computing[5,6]. There is a lot of research[7,8,4,6,[9][10][11][12][13][14][15][16][17][18]on the construction of reversible logic gates. A fundamental question on reversible logic is what kind of reversible circuits can be implemented, given a library of reversible logic gates. ...
Reversible circuits play an important role in quantum computing. This paper studies the realization problem of reversible circuits. For any n-bit reversible function, we present a constructive synthesis algorithm. Given any n-bit reversible function, there are N distinct input patterns different from their corresponding outputs, where N≤2n, and the other (2n−N) input patterns will be the same as their outputs. We show that this circuit can be synthesized by at most 2n⋅N ‘(n−1)’-CNOT gates and 4n2⋅N NOT gates. The time and space complexities of the algorithm are Ω(n⋅4n) and Ω(n⋅2n), respectively. The computational complexity of our synthesis algorithm is exponentially lower than that of breadth-first search based synthesis algorithms.
... It is a fast developing area of research due to its increasing importance to future computer technologies, especially quantum ones [16] because of possibility to solve some exponentially hard problems in polynomial time [7]. For example, during the last three years many papers have been written on reversible computing [1] [2] [3] [4] [5] [8] [12] [13] [14] [15] [20] [22] [23] [24] [25] [26] [28] [29] [30] [32] [33] [34] [35] [36] [40] [41] [42] [43] [44] [45] [46] [47] [50] [53] [54], some of them proposing new multiple-valued gates [47] [41] [5] [14] [1] [2] [3] [40] [43] [30]. In designing circuits built from such gates it is important to know which of the gates have the least cost. ...
A set of p-valued logic gates (primitives) is called universal if an arbitrary p-valued logic function can be realized by a logic circuit built up from a finite number of gates belonging to this set. In the paper, we consider the problem of determining the number of universal single-element sets of ternary reversible logic gates with two inputs and two outputs. We have established that over 97% of such sets are universal.
... Which family, then, of the numerous universal gates are a good choice for synthesis with respect to high processing power, low gate count cost, and simplicity of design? Picton [15] proposed reversible MV gates which were not efficient to realize, especially using quantum primitives, and lead to inefficient structures. No synthesis method was given. ...
We present a new type of quantum realizable reversible cascade. Next we present a new algorithm to synthesize arbitrary single-output ternary functions using these reversible cascades. The cascades use "Generalized Multi-Valued Gates" introduced here, which extend the concept of Generalized Ternary Gates introduced previously. While there were 216 GTGs, a total of 12 ternary gates of the new type are sufficient to realize arbitrary ternary functions. (The count can be further reduced to 5 gates, three 2-qubit and two 1-qubit). Such gates are realizable in quantum ion trap devices. For some functions, the algorithm requires fewer gates than results previously published [1, 5, 8, 14]. In addition, the algorithm also does conversion from arbitrary ternary logic to reversible logic at the cost of relatively small garbage. The algorithm is implemented here in ternary logic, but generalization to arbitrary radix is both straightforward and sees a reduction in growth of cost as the radix is increased.
... While in [3] the structure of a multi-valued logic gate is proposed which can be experimentally feasible with a linear ion trap scheme for quantum computing, this approach produces large dimensional circuits. A universal architecture for multi-valued reversible logic is given in [4], but quantum realization of the circuits thus obtained is not apparent. The universality of n-qudit gates is presented in [5], but no algorithms for synthesis were given. ...
Basic logic gates and their operations in ternary quantum domain are involved
in the synthesis of ternary quantum circuits. Only a few works define ternary
algebra for ternary quantum logic realization. In this paper, a ternary logic
function is expressed in terms of projection operations including a new one. A
method to realize new multi-qutrit ternary gates in terms of generalized
ternary gates and projection operations is also presented. We also introduced
ten simplification rules for reducing ancilla qutrits and gate levels. Our
method yields lower gate cost and fewer gate levels and ancilla qutrits than
that obtained by earlier methods for the ternary benchmark circuits. The $n$
qutrit ternary sum function is synthesized without any ancilla qutrit by our
proposed methodology.
... Synthesis of a combinational MVL circuit implements a reversible MVL function by a cascade of reversible gates. In multiple-valued quantum circuits, the quantum digits (qudits) are the signals and quantum gates are operators, represented by unitary matrices [4,5]. ...
Multiple-valued reversible logic is an emerging area in reversible and quantum logic circuit synthesis. Multiple-valued reversible logic circuits can potentially reduce the width of the reversible or quantum circuit which is a limitation in current quantum technology. In this paper we propose a method to synthesize the multiple-valued reversible sequential circuits. Implementations for ternary D and T flip flops and edge triggered D flip flop are proposed. Synthesis of generalized fanout circuit and generalized r-valued T flip flop are also presented.
... There have been extensive work in constructing reversible gates which have certain properties such as universality, symmetry, etc. [1-7, 9, 12, 17, 19, 20, 22]. In particular, there are the synthesis algorithms by composition [15, 12], decomposition [15], factorization [23]., EXOR logic [4, 8, 15, 18, 24], group-theoretic methods [19, 20], synthesis to regular structures [14, 16, 17, 22], synthesis of various forms of reversible cascades [2, 7, 8, 9, 10, 11, 12, 15] and spectral methods [10, 11]. The Miller's gate [10] was proposed for quantum logic realizations or in emerging reversible technologies. ...
Reversible logic plays an important role in the synthesis of circuits for quantum computing. In this paper, we introduce families of reversible gates based on the majority Boolean function (MBF) and we prove their properties in reversible circuit synthesis. These gates can be used to synthesize reversible circuits of minimum “scratchpad register width” for arbitrary reversible functions. We show that, given a MBF f with 2k+1 inputs, f can be implemented by a reversible logic gate with 2k+1 inputs and 2k+1 outputs, i.e., without any constant inputs. We also demonstrate new gates from this family with very efficient quantum realizations for majority-based applications. They can be used to synthesize any reversible function of the same width in conjunction with inverters and Feynman (2-qubit controlled-NOT) gates. The gate universality problem is formulated in terms of elementary group theory and solved using the algebraic software GAP.
... It is a fast developing area of research due to its increasing importance to future computer technologies, especially quantum ones [8] because of possibility to solve some exponentially hard problems in polynomial time [3]. During the last four years over 40 papers have been published on reversible computing, some of them proposing new multiple-valued gates [25, 23, 7, 1, 22, 24, 14, 15]. To solve the important practical problem of designing circuits built from such gates we should first establish which multiple-valued gates are universal. ...
A set of p-valued logic gates (primitives) is called universal if an arbitrary p-valued logic function can be realized by a logic circuit built up from a finite number of gates belonging to this set. In this paper, we consider the problem of determining the number of universal single-gate libraries of p-valued reversible logic gates with two inputs and two outputs, under the assumption that constant signals can be applied to an arbitrary number of inputs. We have proved some properties of such gates and established that over 97% of ternary gates are universal.
... Universality of n-qudit gates was discussed in [9, 32] but no design algorithms were given. Picton [35] presented an approach called Universal Architecture for multi-valued reversible logic but this approach produces circuits that are far from minimum and have no relation to quantum realization. Since 2001 AlRabadi et al proposed Galois Field approach to quantum logic synthesis (see3456 34]). ...
Galois Field Sum of Products (GFSOP) leads to efficient multi-valued reversible circuit synthesis using quantum gates. In this paper, we propose a new generalization of ternary Toffoli gate and another new generalized reversible ternary gale with discussion of their quantum realizations. Algorithms for synthesizing ternary GFSOP using quantum cascades of these gates are proposed In both the synthesis methods, 5 ternary shift operators and ternary swap gate are used We also propose quantum realizations of 5 ternary shift operators and ternary swap gate. In the cascades of the new ternary gates, local mirrors, variable ordering, and product ordering techniques are used to reduce the circuit cost. Experimental results show that the cascade of the new ternary gates is more efficient than the cascade of ternary Toffoli gates.
... The gates considered here are not the only possible MVL reversible gates nor are they the only possible extension to the Toffoli gate. Picton [11][12] introduced an MVL generalization of the binary Fredkin gate. Al-Rabadi [1] has considered a generalization of the Toffoli gate where XOR is replaced by mod-sum. ...
low-power CMOS design, quantum computation [8][10] and optical computing. An r-valued m-variable reversible logic function maps each of the r, input patters to a unique output pattern. The synthesis problem is to realize a reversible function by a cascade of primitive reversible gates. In this paper, we present a simple heuristic algorithm that exploits the bidirectional synthesis possibility inherent in the reversibility of the specification. The primitive reversible gates considered here are one possible extension of the well-known binary Toffoli gates. We present exhaustive results for the 9! 2-variable 3-valued reversible functions comparing the results of our algorithm to optimal results found by breadth-first search. The approach can be applied to general m-variable, r-valued reversible specifications. Further, we show how the presented technique can be applied to irreversible specifications. The synthesis of a 3-input, 3-valued adder is given as a specific case.
... Reversible circuits are classical counterparts of Quantum Circuits which are inherently reversible [1], [2]. It has manifold applications in low power CMOS quantum computing, nanotechnology, optical computing, computer graphics, DNA technology and cryptography. ...
Reversible circuits find applications in many areas of Computer Science including Quantum Computation. This paper examines the testability of an important subclass of reversible logic circuits that are composed of k-wire controlled NOT (k-CNOT with k >/- 1) gates. A reversible k-CNOT gate can be implemented using an irreversible k-input AND gate and an EXOR gate. A reversible k-CNOT circuit where each k-CNOT gate is realized using irreversible k-input AND and EXOR gate, has been considered. One of the most commonly used Single Bridging Fault model (both wired-AND and wired-OR) has been assumed to be type of fault for such circuits. It has been shown that an (n+p)-input AND-EXOR based reversible logic circuit with p observable outputs, can be tested for single bridging faults (SBF) using (3n + \lefthalfcap log2p \righthalfcap + 2) tests. Comment: 6 pages, 8 figures
... The gates considered here are not the only possible MVL reversible gates nor are they the only possible extension to the Toffoli gate. Picton [11][12] introduced an MVL generalization of the binary Fredkin gate. Al-Rabadi [1] has considered a generalization of the Toffoli gate where XOR is replaced by mod-sum. ...
An r-valued m-variable reversible logic function maps each of the r<sup>m</sup> input patterns to a unique output pattern. The synthesis problem is to realize a reversible function by a cascade of primitive reversible gates. In this paper, we present a simple heuristic algorithm that exploits the bidirectional synthesis possibility inherent in the reversibility of the specification. The primitive reversible gates considered here are one possible extension of the well-known binary Toffoli gates. We present exhaustive results for the 9! 2-variable 3-valued reversible functions, comparing the results of our algorithm to optimal results found by breadth-first search. The approach can be applied to general m-variable, r-valued reversible specifications. Further, we show how the presented technique can be applied to irreversible specifications. The synthesis of a 3-input, 3-valued adder is given as a specific case.
Progress made in quantum computation has resulted in logic synthesis with reversible circuits receiving considerable interest. This paper presents a synthesis of reversible array divider circuit based on non-restoring division algorithm implemented with k-CNOT gates. The execution time of such an array divider is low. Our aim is to propose a reversible array divider circuit which is efficient as regards to the number of garbage outputs and gates.
In the contemporary world there is enormous hike in communication engineering applications, outcome with massive heat dissipation from the processing nodes. So energy efficient information network is one of paramount issue nowadays. For that optical reversible computing could be a landmark with base as optical logic gate. Reduction in power dissipation, consumption could be accomplished through a blend of reversible and irreversible optical processing and the nodes may recuperate the data. Accordingly, in this article two designs with semiconductor optical amplifier, used as Mach–Zehnder interferometer based all optical reversible Feynman gate, irreversible AND logic gate within a single photonic circuit has been proposed. The output waveforms for AND logic operation, Feynman logic the P (data output identical to input), Q (A ⊕ B) has been verified at 100 Gbps data rate. The designs have been evaluated on the basis of key parameter extinction ratio factor. Numerical simulations have inferred excellent ER performance with design-2(ER>13 dB) in contrast to design-1(ER as 10.2 dB). Performance evaluations for significant deign parameters as pump current, length, width, carrier transport, confine and current injection factor yielded excellent performance. This evaluation could be an assist toward design of contemporary optical networks.
While the role of ternary reversible and quantum computation has been growing, synthesis methodologies for such logic, have been addressed in only a few works. A reversible ternary logic function can be expressed as minterms by using projection operators. In this paper, a novel realization of the projection operators using a minimum number of permutative ternary Muthukrishnan-Stroud (M-S) gates is presented. Next, an efficient method for logic simplification for ternary reversible logic is proposed. This method along with the new construction of projection operators yields significantly lower gate cost of approximately 31% less than that obtained by earlier methodologies, for the synthesis of ternary benchmark circuits.
Ternary reversible logic synthesis is the extension and expansion of reversible logic synthesis. In order to simplify the reversible network and improve the generality of ternary reversible logic gate, the effective value of controlling bits of the existing ternary reversible controlled gates can be extended to any of 0, 1 and 2. And on the basis of that, a ternary reversible logic synthesis algorithm with minimum chaos degree is proposed. The algorithm is used to compute the relative chaos degree and absolute chaos degree of each variable in truth table under ternary logic system, according to the reversible function. As one reversible logic gate is selected, the principle of minimal chaos degree in ternary reversible logic synthesis should be followed until the relative chaos degree and absolute chaos degree of each variable in truth table decrease to 0, which means the synthesis has been finished, and the reversible network can be derived. The time complexity for the algorithm is O(n2×3n), and its space complexity is O(n×3n). The experimental results show that the average number of gates is less than the existing algorithms as known.
Multiple-valued quantum logic allows the designers to reduce the number of cells while obtaining more functionality in the quantum circuits. Large r-valued reversible or quantum gates (r stands for radix and is more than 2) cannot be directly realized in the current quantum technology. Therefore, we are interested in designing the large reversible and quantum controlled gates using the arrays of one-quantum digit (qudit) or two-qudit gates. In our previous work, we proposed quantum arrays to implement the r-valued quantum circuits. In this paper, we propose novel efficient structures and arrays, for r-valued quantum logic gates. The quantum costs of the developed quantum arrays are independent of the radix of calculations in the quantum circuit.
The advantages of reversible logic systems and circuits have drawn a significant interest in recent years as a promising computing paradigm having application in low power CMOS, quantum computing, nanotechnology, and optical computing. This paper proposes a novel reversible multiplexer circuit with the help of all-optical Toffoli and Feynman gate. Operational principle of reversible multiplexer is described and is supported with logical simulation.
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. We present an optimization method for reversible logic synthesis based on the Integrated Qubit (IQ) library. This method works in conjunction with existing methods to further improve quantum cost and delay of a synthesized reversible logic circuit. This algorithm runs in O(N) time, and reduces the quantum cost of synthesized circuit by up to 45 percent. In addition, the process of replacing the gates in the synthesized circuits with IQ gates uses a locally optimal technique whose major benefits include reduction of cost as well as delay.
Recently design of reversible logic circuits draw much attention in nanotechnology and quantum computing. Conventional logic circuits are not reversible. A reversible circuit maps each input vector, into a unique output vector and vice versa. In this paper, we propose a novel scheme of Toffoli and Feynman gates in all-optical domain using terahertz optical asymmetric demultiplexer (TOAD). Both the realizations are supported through proper flowchart followed by simulation in Macad-7. Simulation results verify the functionality of both the gates along with verified reversibility. Toffoli and Feynman gates can be used to implement Boolean expressions and arithmetic operations.
Reversible circuits are of vital importance in many applications involving low power design. One of the principle areas where reversible circuits play great role is quantum computing. One of the foremost requirements of quantum computation is that it requires all the circuits that are used should be reversible in nature. Reversible circuit is one which maps an individual input vector to a singular output vector. Because of its application in many areas including quantum computing, many synthesis approaches have been developed. In this paper we focus on a synthesis approach which is based on permutation theory and heuristic search. An artificial intelligence based search technique A* is used to find near optimal solutions. Experimental results demonstrate that the proposed approach provides solutions within a very reasonable span of time.
Reversible circuits play an important role in quantum computation. The realization of reversible quantum circuits is required for any quantum computer to be universal. This paper1 studies the realization and synthesis problem of reversible circuits. Using group theory, we present two sets of new 3-bit reversible logic gates, which included g1g2g3 and nine complex gates, respectively. It is shown that any 3-bit reversible logic circuit is realizable by cascading NOT and Feynman gates, and at most one instance of our proposed gates. Given any n-bit reversible function, there are N distinct input patterns different from their corresponding outputs, where N ≤ 2n, and the other (2n - N) input patterns will be the same as their outputs. According to a synthesis example, it demonstrates that the main results are constructive and practical than others.
Based on traditional Toffoli gate, a new reversible network cascade model PNCRC is proposed. The model consists of five line-styles, and it is able to control output of target bits with positive/negative way effectively. A reversible synthesis algorithm corresponding to the proposed model is also designed in this paper. Compared to the previously reported results, some experiments on NCMC Benchmark functions (less than or equal 16 variables) show that PNCRC decrease the number of garbage output and number of reversible gates as a whole.
Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. In this paper, we propose an improved technique for synthesizing reversible circuits based on a combined depth-first search (DFS) and breadth-first search (BFS) algorithm. A method based on DFS alone may often take a long time to converge, whereas, a BFS based method requires a large amount of memory for designing a circuit of moderate complexity. To strike a balance between these two approaches, we propose a hybrid DFS-BFS based synthesis algorithm that reduces the computation time compared to the DFS method and requires less space compared to the BFS method, while optimizing the cost of the circuit. Synthesis results on several reversible benchmark circuits have been reported.
A first practical logic function reversible synthesis method has been presented. In this method, minimizing a standard logic function for obtained a SOP of optimization in our approach previously. This efficient conversion between SOP and fixed polarity Reed-Muller (FPRM) forms. The results show that the algorithm is efficient in terms of time and space. We also proposed the synthesis algorithm for reversible functions. It uses fixed polarity Reed-Muller decomposition at each stage to synthesize the function as a network of Toffoli gates. Some examples of NCMC benchmarks with a large number of variables were presented to demonstrate the suitability of the algorithm for synthesizing complex functions
This paper presents a constructive synthesis algorithm for any n-qubit reversible function. Given any n-qubit reversible function, there are N distinct input patterns different from their corresponding outputs, where N les 2<sup>n</sup>, and the other (2<sup>n</sup> - N) input patterns will be the same as their outputs. We show that this circuit can be synthesized by at most 2nldrN '(n - 1)'-CNOT gates and 4n<sup>2</sup> ldr N NOT gates. The time complexity of our algorithm has asymptotic upper bound O(n ldr 4<sup>n</sup>). The space complexity of our synthesis algorithm is also O(n ldr 2<sup>n</sup>). The computational complexity of our synthesis algorithm is exponentially lower than the complexity of breadth-first search based synthesis algorithm.
Detection of bridging faults plays a significant role in a reversible circuit. The single and multiple inputs bridging faults model of a reversible circuit is considered here. The paper proposes that only n (number of inputs) number of universal test vectors are sufficient for detection of all single and multiple input bridging faults and all input stuck-at faults of any n-input and n-output reversible circuit. A polynomial time algorithm is proposed for generating the universal test vectors for detecting of all single and multiple input bridging faults of the reversible circuit. The results on reversible benchmark circuit show that the number of universal test vectors are significantly reduced compared to the earlier works of reversible circuit and classical circuit.
In recent years, reversible logic has emerged as a promising computing paradigm having application in low-power CMOS, quantum computing, nanotechnology and optical computing. Optical logic gates have the potential to work at macroscopic (light pulses carry information), or quantum (single photons carry information) levels with great efficiency. However, relatively little has been published on designing reversible logic circuits in all-optical domain. In this paper, we propose and design a novel scheme of Toffoli and Feynman gates in all-optical domain. We have described their principle of operations and used a theoretical model to assist this task, finally confirming through numerical simulations. Semiconductor optical amplifier (SOA)-based Mach–Zehnder interferometer (MZI) can play a significant role in this field of ultra-fast all-optical signal processing. The all-optical reversible circuits presented in this paper will be useful to perform different arithmetic (full adder, BCD adder) and logical (realization of Boolean function) operations in the domain of reversible logic-based information processing.
This article presents a novel technique for fault detection as well as fault location in a reversible combinational circuit under the missing gate fault model. It is shown that in an (n×n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate, yields an easily testable design, which admits a universal test set (UTS) of size (n+1) that detects all single missing-gate faults (SMGFs), repeated-gate faults (RGFs), and partial missing-gate faults (PMGFs) in the circuit. Furthermore, storage of only one vector (seed) of the UTS is required; the rest can be generated by n successive cyclic bit-shifts from the seed. For fault location under the SMGF model, a technique for identifying the faulty gate is also presented that needs application of a single test vector, provided the circuit is augmented with some additional observable outputs.
We consider the symmetric group S n in the special case where n=pq (both p and q being integers). Applying Birkhoff’s theorem, we prove that an arbitrary element of S pq can be decomposed into a product of three permutations, the first and the third being elements of the Young subgroup S p q , whereas the second one is an element of the dual Young subgroup S q p . This leads to synthesis methods for arbitrary multiple-valued reversible logic circuits of logic width ω. These circuits indeed form a group isomorphic to S rω , where r is the radix of the multiple-valued logic. A particularly efficient decomposition is found by choosing p=r and thus q=r ω-1 . As a result, an arbitrary reversible logic circuit of radix r and width ω is decomposed into a cascade of 2ω-1 control gates, i.e. logic building blocks which manipulate only one of the ω dits.
Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Newer technologies like ion trapping or nuclear magnetic resonance are required to emulate quantum gates. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely, single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. In this paper, it is shown that in an (n · n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate yields an easily testable design, which admits a universal test set of size (n +1) that detects all SMGFs, RGFs, and PMGFs in the circuit. Keywords: Missing-gate faults, quantum computing, reversible logic, testable design, universal test set
Testing of bridging faults in a reversible circuit is investigated in this paper. The intra-level single bridging fault model is considered here, i.e. any single pair of lines, both lying at the same level of the circuit, may be assumed to have been logically shorted in order to model a defect. For an (n X n) reversible circuit with d levels realized with simple Toffoli gates, the time complexity of the test generation procedure is O(nd<sup>2</sup> log<sub>2</sub>n). A test set of cardinality O(d log<sub>2</sub>n) is found to be sufficient for testing all such detectable faults. A minimal test set can also be easily derived by using the concept of test equivalence.
Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose reversible gates are also shown.
ResearchGate has not been able to resolve any references for this publication.