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Integrated switches for
implantable medical devices,
in HV-MOS technology
Author: Joel Gak Szollosy
Advisor: Alfredo Arnaud
Committee: Dr. Fernando Rangel – UFSC Brazil
Eng. Federico de Mula – CCC Uruguay
Dr. Enrique Ferreira – UCU Uruguay
Montevideo, May 2010
Integrated switches for implantable medical devices, in HV-CMOS
technology
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Safety note:
Medical device manufacturer, that
employs any of the designed
switches on this document, shall
guarantee that when not stimulating
all the electrodes are either in high
impedance, or connected to GND.
GND shall be the common mode
voltage for biological tissue.
Integrated switches for implantable medical devices, in HV-CMOS
technology
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Abbreviations
The following abbreviations were used along this document.
UCU, Universidad Católica del Uruguay.
FIT, Facultad de Ingeniería y Tecnologías.
CMOS, complementary metal-oxide-semiconductor.
SIO, Silicon on insulator.
MOS, metal-oxide-semiconductor.
CCC, Centro de Construcción de Cardioestimuladores del
Uruguay.
ESD, electro static discharge.
DIE, Departamento de Ingeniería Eléctrica, FIT-UCU.
µDIE, grupo de microelectrónica de la UCU.
HV, high voltage.
ASIC, application specific integrated circuit.
LV, low voltage.
EMI, electro magnetic interference.
PHV, PMOS high voltage.
NHV, NMOS high voltage.
TG, transmission gate.
Integrated switches for implantable medical devices, in HV-CMOS
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Resumen
Los dispositivos médicos implantables se utilizan en el tratamiento de un
número cada vez mayor de patologías. La microelectrónica es una
herramienta esencial en el desarrollo de los mismos. Un aspecto
importante del diseño, son los circuitos que controlan los estímulos
eléctricos hacia el tejido biológico.
En este trabajo se diseñó, fabricó, midió, y comparó, tres tipos de llaves
(Llave A, B y C) integradas, capaces de dejar pasar o cortar estímulos
tanto en tensión (100mV-16V) como en corriente (100µA-30mA). Los
circuitos fueron fabricados en una tecnología CMOS de alto voltaje sobre
un waffer de SOI (XT06 de Xfab) [3].
Las especificaciones para las llaves fueron obtenidas en conjunto con la
empresa CCC del Uruguay [12], acorde a su experiencia en la ingeniería
de dispositivos médicos implantables. El objetivo es cumplir con un amplio
espectro de posibles aplicaciones, para servir de llave de estímulo de uso
genérico en prototipos y pequeñas series de dispositivos innovadores
para diversas terapias. Las llaves diseñadas incluyen transistores de paso
MOS de gran tamaño, y una compleja circuitería para el manejo de la
conmutación y adaptación de los niveles de voltaje. Deben cumplir con las
siguientes especificaciones:
1. Impedancia menor a 5Ω, cuando están conduciendo.
2. Tensión de alimentación V
CC
entre 2v y 5V para los circuitos lógicos
y drivers.
3. Consumo estático despreciable (máximo decenas de nA).
4. Corrientes de fugas despreciables (debajo de 20nA).
5. Tiempo de cierre y apertura menor a 1µs.
6. Capacidad de conmutar estímulos en tensión, desde 100mV hasta
16V
7. Estímulos en corriente, desde 100µA hasta 30mA
8. Llave completamente simétrica, esto significa que los nodos de
entrada/salida (V
IN
, V
OUT
) pueden ser intercambiables y las llaves
deben funcionar sin degradar su performance.
9. Frente a una falla simple (por ejemplo ruptura de un GATE), no
entregar corriente continua a tejido o en caso de hacerlo que no
supere unos pocos µA ya que se puede poner en riesgo al paciente.
10.Minimizar Crosstalk, esto es los picos de corriente parásitos a través
de la llave cuando está abierta, pero la salida cambia abruptamente
de potencial. Idealmente no debería entrar corriente a la llave, sin
embargo no es posible hacer una llave libre de crosstalk devido a
capacidades parásitas, este efecto debe ser el mínimo posible.
11. Inyección de carga hacia la carga cuando se abre y se cierra la
llave debe ser la mínima posible.
12. Protección contra descarga electrostática (ESD).
Integrated switches for implantable medical devices, in HV-CMOS
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Las medidas realizadas, muestran que se cumplió de forma satisfactoria
con estas especificaciones.
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Abstract
Implantable medical devices are being used in the treatment of a growing
number of pathologies. Microelectronics is an essential tool for the
development of these devices especially novel applications. An important
aspect of the design, is the capability of controlling electrical stimuli
delivered to biological tissue.
In this work, three different integrated switches (Switch A, B and C) were
designed, fabricated, measured and compared, to control either voltage
(100mV-16V), or current (100µA-30mA), stimuli. The circuits were
fabricated in a high voltage CMOS technology over a SOI waffer (XT06
from XFAB) [3].
For this research, the specifications were determined with the aid of CCC–
Uruguay [12], because of their experience in the engineering of
implantable medical devices. The objective is to be able to use the
designed switches in a wide spectrum of devices, either at prototype level,
or in small production batches. The designed switches are composed of
large size MOS pass transistors and a complex circuitry for MOS gates
control and voltage level adaptation. The switches shall comply with the
following specifications:
1. On resistance below 5Ω.
2. Power supply V
CC
from 2V to 5V for logic circuits and drivers.
3. Negligible static power consumption (few tens nA maximum).
4. Negligible leakage currents (below 20 nA at any pin).
5. On/Off time below 1µs.
6. Support voltage stimuli from 100mV to 16V.
7. Support current stimuli form 10µA to 30mA.
8. The switches must be symmetrical, that means the input/output
(V
IN
– V
OUT
) pins can be exchanged at any circuit configuration and
the switch must operate with no further changes or significant
performance degradation.
9. Safety, the failure of a single circuit element (for example a
punctured MOS gate) must not cause a DC current flow through to
the electrodes in contact with the tissue, larger than a few micro-
amperes because otherwise it may be a risk for the patient.
10. Crosstalk shall be the minimum possible: when the switch is off, in
the case of a voltage pulse in the output, ideally no current peaks
flow into the switch. Although it is not possible to develop a
crosstalk-free device because of the parasitic capacitance in the
output node, the effect shall be the minimum possible.
11. Charge injection to the load when the switch is turned on or off,
shall be the minimum possible.
12. Electro static discharge (ESD) protection shall be included on every
circuit pin.
Integrated switches for implantable medical devices, in HV-CMOS
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A rough conclusion after fabrication and measurements, is that all
specifications were met without a major deviation.
Integrated switches for implantable medical devices, in HV-CMOS
technology
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Agradecimientos
CCC del Uruguay, por la financiación de la beca y circuitos, especialmente
Federico de Mula y Pedro Arzuaga, que participaron en la definición de
requerimientos y aportaron su experiencia en el área de dispositivos
médicos implantables. A José Pereira y Gabriel Barbat por la ayuda con
algunas medidas.
A la ANII, Proy.FCE 592, que ayudo a presentar algunas publicaciones.
Universidad Católica del Uruguay por la beca de maestría.
Alfredo y Matías que participaron en todas la etapas de este proyecto,
diseño, simulaciones y layout.
Al tribunal: Fernando Rangel, Federico de Mula y Enrique Ferreira.
A toda la gente del DIE y µDIE.
Familia y amigos.
Noel.
Integrated switches for implantable medical devices, in HV-CMOS
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Index
1
Introduction ..............................................................................11
1.1
Background, motivation and goals. .........................................12
1.2
Microelectronics and medical implants.....................................13
1.2.1
Safety requirements of implantable medical devices ..........14
1.3
Design specifications, circuit PINs ...........................................15
1.4
Conclusions and Contents......................................................17
2
HV CMOS technology and the main MOS transistors .......................18
2.1
Introduction.........................................................................18
2.2
XT06...................................................................................19
2.2.1
PMOS High Voltage transistor (phv) and Switches B, C.......20
2.2.2
NMOS High Voltage transistor (nhv) ................................22
2.2.3
High Voltage Transmission gate (TG) for switch A..............23
2.3
Main switch dimension ..........................................................26
3
Driver circuitry & complete switch design ......................................27
3.1
Basic building blocks .............................................................27
3.1.1
Level-shifters................................................................27
3.1.2
2V
CC
generator. .............................................................35
3.1.3
V
SS
generator................................................................36
3.1.4
Negative driver. ............................................................37
3.1.5
A novel over voltage V
GS
protection circuit ........................39
3.2
Switch A..............................................................................42
3.3
Switches B and C .................................................................46
3.3.1
Switch B design ............................................................46
3.3.2
Switch C ......................................................................50
4
Measurements ...........................................................................53
4.1
Switch impedance (RON).......................................................53
4.1.1
R
ON
with 2V
CC
(switch A) and V
SS
(switch B, C) ..................53
4.1.2
R
ON
without charge pump: without 2V
CC
(Switch A) or V
SS
(Switch B, C).............................................................................58
4.2
Voltage stimuli with 2V
CC
(switch A) and V
SS
(switches B, C) ......60
4.3
ON/OFF time........................................................................65
4.4
Power consumption ..............................................................66
4.4.1
Static power consumption ..............................................66
4.4.2
Dynamic power consumption with charge pumps connected
67
4.5
Leakage currents..................................................................69
4.6
Crosstalk.............................................................................70
4.7
Current stimuli (charge injection) ...........................................74
4.7.1
Current stimuli sweep with 2V
CC
(switch A) and V
SS
(switches
B, C) 75
4.7.2
V
Stimuli
sweep with 2V
CC
(switch A)and V
SS
(switches B, C) ...77
4.8
ESD testing .........................................................................79
5
Conclusions...............................................................................81
5.1
Future work .........................................................................84
5.2
Publications .........................................................................84
6
References ................................................................................86
7
Annex A: ESD protection design...................................................88
Integrated switches for implantable medical devices, in HV-CMOS
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7.1
Human Body model ..............................................................88
7.2
ESD protection device types ..................................................89
7.3
ESD protection strategy ........................................................90
7.4
Low voltage I/O ESD protected pads.......................................91
7.5
High voltage I/O ESD protected pads ......................................92
7.6
V
SS
ESD protected pad ..........................................................93
7.7
V
CC
and GND ESD protected pads ...........................................94
7.8
PAD list ...............................................................................95
Integrated switches for implantable medical devices, in HV-CMOS
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1 Introduction
Most implantable medical devices are electrical stimulation systems, that
deliver either current or voltage pulses to the patient according to
different requirements. Microelectronics technology steadily contributes to
the development of such devices. Stimuli section of the circuit may consist
of the basic elements shown in Figure 1.1, a stimuli generator (either a
voltage or current source), electrodes connecting the tissue to the device,
a switch that toggles the electrical connection of the electrodes and a
control block that decides when and for how long a stimulus shall be
applied. Stimulation can be either a voltage applied to the tissue from a
few hundreds mV to well over 10 V, or a current forced through it ranging
from a few tens of µA to tens of mA. Although at a glance it appears
simple, in this work we will focus in a circuit to implement the switch of
Figure 1.1. A 0.6 microns high voltage (HV) technology on a p-type SOI
wafer with insulator trenches capability was selected (XT06 from XFAB),
first to enable stimulation up to 16 Volts, while insulating characteristics
allowed the design of a safety compliant circuit in a wide range of
connection schemes. Different medium and high voltage, fully isolated
transistors can be fabricated with maximum ratings between 8V and up to
60V V
DS
. Because of trench isolation, floating diodes can also be
fabricated.
Stimuli Generator
V
I
Switch
Electrode
Tissue
Control
Figure 1.1. Typical stimuli section of an implantable medical device.
Integrated switches for implantable medical devices, in HV-CMOS
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1.1 Background, motivation and goals.
The microelectronics research group (from now on µDIE –
http://die.ucu.edu.uy/microdie) at the Electrical Engineering Department
Universidad Católica del Uruguay (UCU) is dedicated to the research and
development of application specific integrated circuits (ASICs), with
emphasis on analog and mixed mode "full custom" design in CMOS
technology. Low voltage and micropower applications for implantable
medical devices are a main research area. In recent years the µDIE has
designed and fabricated six ASICs, containing different research &
development circuits aimed to be part of implantable medical devices. The
circuits were fabricated in 0.35µm, 0.35µm-HV, 0.6µm-HV and 1.5µm
CMOS technologies and include ultra low-noise amplifiers [13], G
m
-C
filters [14], DC-DC converters [15] and several test structures for
transistor modeling.
This work is part of a first cooperation project with Centro de Construcción
de Cardioestimuladores del Uruguay (CCC) [12], with the objective to
receive some feedback from the medical device industry and to focus the
research activities at µDIE towards the needs of real novel implantable
electronics under development. CCC helped with the specifications for the
circuit and provided us helpful suggestion during the design process.
Another main objective of this work was to gain expertise on HV
technology. Our research group currently has a strong interest in HV due
to its relevance for implantable electronics, but also because HV will be
probably required in the development of ASICs to incorporate
microelectronics technology in several cases studied for the national
industry (most cases are front-ends involving relatively large voltages).
This work allowed the fabrication of the first research ASIC on HV
technology at µDIE and because of the challenging design, it required the
use of the full features available in HV. At present, two more circuits are
being fabricated in HV (XT06, XC06) [3].
This thesis work included the design and test measurements of integrated
circuits designed at Departamento de Ingeniería Eléctrica (DIE). The CAD
tool employed was Mentor Graphics using a University license through the
Mentor-HEP program [16]. Laboratory measurements required only
standard instruments like precision multimeters, oscilloscope, voltage
sources and function generator.
Although this work prime objective is research, it allowed a rich exchange
of ideas with the industry. It is our hope that the designed circuits and the
acquired knowledge, may contribute to the development of valuable and
innovative products in the near future.
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1.2 Microelectronics and medical implants
An electronic medical implant is defined as any type of medical device that
incorporates electronic components and is used inside the body to achieve
a physiological response. The first microelectronic medical implant was a
heart pacemaker, which became a common device in the 1970s [17]. But
many other implants are now in use, like hearing aids [18],
neurostimulators [19], or implantable drug infusion pumps [20], among
others. In recent years the use of implantable medical devices has
increased and it is expected to continue rising [1]. Not only there has
been an increase in the use of existing medical devices, but also new
devices, like vision enhancers, are expected to be developed in a nearby
future.
Medical devices used for treatment of different diseases have widely
different requirements and specifications, nonetheless there are several
characteristics shared by most of them.
1. Low power consumption: Changing or charging batteries can be
inconvenient, difficult, costly and even risky for the patient; all
implantable medical devices need to consume as little energy as
possible [21].
2. High reliability: A failure of an implantable medical device can result
on inconvenience, pain, damage or even death for the patient. Also
maintenance is costly and risky [2].
3. Low voltage signals. Most of the natural signals inside a human
body, as well as the output of the transducers, are in the µV or mV
range which requires special care in sensing and amplifying
[22][23].
4. Low frequencies: The natural frequency span of biological signals
vary from a fraction of a hertz to several kilohertz.
5. Small Size: Implantable devices need to be as small as possible, so
as to be less invasive to the human body [24]. This does not always
means that silicon area should be as small as possible, because
increasing silicon area to minimize external components can reduce
overall size.
6. High voltage and/or current stimuli.
To fulfill the above needs, microelectronics becomes an essential tool for
the development of implantable medical devices. This work deals with a
generic circuit for electrical stimuli control, taking into account the above
mentioned characteristics.
Integrated switches for implantable medical devices, in HV-CMOS
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1.2.1 Safety requirements of implantable medical
devices
To guarantee safety requirements of implantable medical devices, is one
of the most important issues on the design of an ASIC to ensure no harm
is done to the patient. The two principal aspects to take into account are:
• Reliability: reliability stands for the probability of a failure to
occur. Medical reliability means the frequency (probability) of a
failure should be as low as possible. Thus several design practices
will be adopted to enhance the reliability of the circuit.
• Safety: But even after ASIC test, it is not possible to guarantee
that no failure will occur. A safe circuit means that the device does
not cause harm to the patient, in case of a single circuit element
failure (for example a punctured gate, a short circuit transistor).
The fail safe device does not exist, but if the probability of a single failure
is low (high reliability) and considering failures as statistical independent
events, the probability of two simultaneous failures can be considered
virtually impossible [2][28][29]. Thus, the regular practice for implantable
medical devices designers is to ensure that if a single failure occurs in the
circuit, it does not cause harm to the patient. The kinds of potentially
hazardous effects in an electronic device in direct contact with the human
body, may vary with the application. For example in a pacemaker a failure
must not result in an artificial pace rate above 200ppm. But for any circuit
delivering stimuli like the one in this work, it is mandatory at least to
comply with the following rule: any single failure (may be a punctured
gate in a MOS transistor, Drain to Source short, etc.) must not cause a
significant (for example larger than few µA) DC current flow to the tissue.
A DC current for example to the heart muscle may produce defibrillation,
but any tissue constitution is damaged due to electrochemical phenomena
in the case of DC current flow [28][29]. So DC current must be
guaranteed to be virtually zero in the case of single failure, for any
electrode driver, or electrode sensing circuit (either connected to nerves,
muscles, etc.). While the regular practice is to include capacitors in series
with the stimulating or sensing electrodes [25][26] , in this project a
capacitor in series cannot be assumed. Thus a more complex safety
mechanism shall be implemented.
Integrated switches for implantable medical devices, in HV-CMOS
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1.3 Design specifications, circuit PINs
The designed switches must comply with requirements of a wide spectrum
of possible applications, in fact it was projected as a general purpose
switch for prototypes and low volume series of novel implantable medical
devices for several therapies. The designed switches include large MOS
transistors to control the current flow and a complex circuitry to drive the
transistors’ gates.
An application example is shown in Figure 1.2, where the switch controls a
voltage pulse to the load R
Meas
. The following PINs are necessary:
• CTRL: (Digital Input) Opens and closes the switch. This pin is
normally connected to a microcontroller that controls the switch.
• GND: Switch ground.
• V
CC
: Power supply, for digital and low voltage circuitry.
• C
ap
: C
1
connection. This capacitor is part of an embedded charge
pump that generates, if necessary, either a 2V
CC
voltage, or a
negative voltage V
SS
= (-V
CC
) to drive the main transistors gates to
achieve the necessary 5Ω in the full range of stimuli voltages.
• 2V
CC
/V
SS
: 2V
CC
/V
SS
Charge pump generated voltage.
• V
IN
: Switch input.
• V
OUT
: Switch output to tissue.
• V
High
:
Reference voltage, it is normally connected to V
IN
. It is a
reference voltage for a protection circuit in switches B,C, to be
discussed in chapter 3.
Note 1: if the charge pump operation is not necessary, Cap pin is not
connected and 2V
CC
/V
SS
shall be connected to V
CC
/GND.
Note 2: V
IN
V
OUT
can be exchanged
The switches shall verify the following specifications:
1. On resistance below 5Ω.
2. Power supply V
CC
from 2V to 5V.
3. Negligible static power consumption (few tens nA maximum).
4. Negligible leakage currents (below 20 nA at any pin).
5. On/Off time below 1µs.
6. Support voltage stimuli from 100mV to 16V.
7. Support current stimuli form 10µA to 30mA.
8. Symmetrical, that is the V
IN
– V
OUT
pins can be exchanged in Figure
1.2 or any other connection scheme and the switch must operate
with no further changes or significant performance degradation. To
put it simple, the switch must block or allow current flow, in both
directions.
9. Safety, the failure of a single circuit element (for example a
punctured MOS gate) must not cause a DC current flow through to
Integrated switches for implantable medical devices, in HV-CMOS
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16
the electrode larger than a few micro-amps, otherwise it may be a
risk for the patient.
10.Crosstalk shall be the minimum possible: Crosstalk phenomenon is
explained in Figure 1.3. In the case of a voltage pulse in the output,
ideally no current peaks flow through the switch when opened.
Although it is not possible to develop a crosstalk-free device
because of the parasitic capacitance in the output node, the effect
shall be minimized.
11.Charge injection to the load when the switch is turned on or off,
shall be the minimum possible.
12.Electro static discharge (ESD) protection shall be included on every
circuit pin.
V
Stimuli
V
IN
V
OUT
C
ap
2V
CC
/V
SS
CTRL
V
High
GND
Switch
GND
R
Meas
C1
V
CC
V
CC
0V
50% duty cycle
square wave
GND
Figure 1.2 Voltage stimuli configuration. CTRL signal is provided by a
microcontroller, high voltage stimuli are delivered to the tissue (R
Meas
).
V
Stimuli
V
IN
V
OUT
C
ap
2V
CC
/V
SS
CTRL
V
High
GND
Switch
GND
R
Meas
C1
V
CC
8V
0V
50% duty cycle
square wave
Crosstalk
current
Opened
switch
Figure 1.3 Crosstalk phenomena: tissue voltage can abruply change due
to a stimulus through a different electrode, causing a parasitic current
into the switch.
Integrated switches for implantable medical devices, in HV-CMOS
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1.4 Conclusions and Contents
The design of ASICs, for implantable medical devices has both academic
and industrial interest. However there is very little published work about
the design of circuits to control voltage or current stimuli. This work deals
with the design of integrated switches for electrical stimuli delivery to
biological tissue, that must comply with a broad span of possible uses in
implantable devices, combinded with strict safety rules, ESD protection,
low crosstalk, low charge injection and negligible leakages, among others,
resulting in challenging specifications. A HV-CMOS over SOI waffer was
chosen for the application (XT06 from XFAB).
Three different circuits will be developed for the task, named Switch A,
Switch B and Switch C. Switch A is a large composite CMOS transmission
gate to control stimuli and its driving circuitry. Switches B and C, are very
similar, include a dual PMOS large composite transistor and its driving
circuitry (there is only a slight difference in the driver circuit between
Switches B and C.).
In the following chapter, the selected HV CMOS technology is presented as
well as the design of the main transistors (the transmission gate of Switch
A and the PMOS of Switches B and C). In chapter 3 the driving circuits and
the complete design of the switches are presented, including simulations
of the driving circuits. In chapter 4 measurement results are shown. In
chapter 5 a comparison between the proposed circuits result is shown, as
well as overall conclusions and future work. Mainly because of ESD
performance, Switches B or C seems to be the first option for a real
device. ESD considerations are presented in Annex A.
Integrated switches for implantable medical devices, in HV-CMOS
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2 HV CMOS technology and the main
MOS transistors
In this chapter the main HV technology characteristics are described,
focusing on the employed MOS transistors. The designed switches are
composite ones, composed of very large (very wide) transistors that let
the current flow or not and a driving circuitry that controls the gate of
these so called main transistors. At the end of the chapter the main
transistors are designed while the driving circuitry and whole switch
operation is described in the next chapter.
2.1 Introduction
In spite of the existence of several techniques for the use of standard
CMOS technology with relatively high voltages [10][11], high voltage
technology (HV) is preferred by medical equipment manufacturers
because they strictly follow the integrated circuit (IC) manufacturer rules.
Introducing new process layers, a HV CMOS technology allows the
fabrication of devices that can support elevated voltages [5]. In this work
the selected process is XT06, from Xfab [3], a 0.6 microns HV-MOS on
SOI waffer. Regular 5V core CMOS can also be fabricated, as well as
double poly capacitors and high-resistivity poly resistors in the target
process. For example, in Figure 2.1 a HV NMOS transistor (named nhv)
vertical cut is shown. Nhv has the usual structure of a HV transistor,
incorporating a thick gate oxide that enables up to 18V V
GS
, V
GB
and the
drain diffusion is growth into a N-Well to complete a diffused Drain to
support elevated V
DS
voltages. To help the interpretation of the circuits in
this work (different kind of HV, LV, transistors are used) the symbols used
for each transistor are shown in Figure 2.2. HV transistors are not
symmetrical, the drain which is designed to withstand the highest voltage,
is marked with a double line.
NDIFF
NDIFF
PDIFF
FOX
PTUB
NWELL
BULK
SOURCE
GATE
DRAIN-
EDGE-FOX
DRAIN
FOX
FOX
FOX
Figure 2.1 Vertical cut view of a typical HV NMOS (nhv)
Integrated switches for implantable medical devices, in HV-CMOS
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LV
5V
NMOS
LV
5V
PMOS
HV
NMOS
nhv
HV
P
MOS
phv
Figure 2.2 Symbols for the different kinds of transistors used in the
circuits: LV NMOS and PMOS and HV NMOS (nhv) and PMOS (phv). LV
transistors use thin oxide and withstand up to 5V V
GS
. HV ones use a
thick oxide to withstand up to 18V V
GS
and up to 60V V
DS
because of their
diffused Drain.
2.2 XT06
XT06 technology from XFAB [3] was selected for the ASIC, because apart
of being HV, its unique isolation capability allowed the widest range of
possible connection configurations without the risk of latchup, or safety
problems.
The XT06 Series complements X-FAB's 0.6µm Modular Mixed Signal
Technology. XT06 uses dielectric isolation on SOI wafers, which allows
unrestricted 40 V high and low side operation of all devices. The process
offers reduced parasitics which results in smaller crosstalk, reduced noise
and better EMI characteristics. XT06 thus allows innovative circuit design
with reduced circuit complexity. CMOS as well as bipolar transistors are
available with breakdown voltages of up to 110 V. The 5V CMOS core is
compatible in design rules and transistor performance with simpler,
similar 0.6 µm CMOS processes (for example XC06 technology in standard
waffer). For analog applications, several capacitor and resistor devices can
be realized using the double poly architecture [4]. Also isolating trenches
allows the use of forward diodes. In Table 2.1 a summary of available
devices in XT06 is shown.
Table 2.1 XT06 devices and characteristics.
MOS TRANSISTORS V
T
(V) I
DS
@V
GS
(µA/µm) BV
DSS
(V)
Max V
DS
(V)
NMOS 5V 0.87 470@5 31
5.5
PMOS 5V 0.9 230@5 12
5.5
NMOS with ESD
implant 0.9 520@5 12
5.5
NMOS HV 0.82 220@12 60
30
PMOS HV 0.75 190@12 70
40
RESISTORS RS (Ω/□) Max V
CE
(V)
Low TC poly0 580 60
High resistive poly0 3500 60
FORWARD DIODES V
f
(V) Max I
f
(mA/µm) Max V
r
(V)
Rectifier diode 0.82 0.25 10
Rectifier HV diode 0.83 0.25 50
CAPACITORS BV (V) Area Cap (fF/
µm
2
) Max V
CC
poly0/pol1 cap 30 1.87 8
linear poly0/pol1 cap 20 1.02 8
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2.2.1 PMOS High Voltage transistor (phv) and
Switches B, C.
PHV transistor in XT06 will be used as the main pass transistor in switches
B and C (also in parallel with nhv in Switch A), to allow the passage or not
of the stimuli. In Figure 2.3 a vertical cut of a phv transistor is shown.
P
DIFF
P
DIFF
N
DIFF
FOX
FOX
FOX
FOX
N
TUB
(SNWELL)
FIEL
IMPLANT
BOX
TRENCH
TRENCH
BULK
SOURE
GATE
DRAIN
-
EDGE
-
FOX
DRAIN
HANDLE WAFER
Figure 2.3 PHV transistor vertical cut.
In Figure 2.4 phv transistor with its associated parasitic diode is shown,
the switch is opened (preventing current flow) when V
CTRL1
is connected to
V
IN
, but if V
OUT
is larger than V
IN
, conduction of the stimuli will take place
through the parasitic diode. It is important to mention that in the Switches
to be presented, because there is no absolute maximum voltage in the
circuit, but also because of the required symmetry, Source and Bulk nodes
will be always tied. To comply with the symmetry specification, two phv
transistors in series (shown in Figure 2.5) are used as the main composite
transistor for switches B and C. The driver circuit connects V
CTRL1
to V
IN
and V
CTRL2
to V
OUT
, to open the switch. Because this PMOS switch shall
control pulses down to 100mV, to close the switch both gates are
connected to a negative voltage V
SS
. V
SS
will be also generated in switches
B and C, with the aid of an external capacitor (section 3.1.3) in a charge
pump configuration. If for a given application, no extremely low stimuli
voltages are required, then the charge pump operation can be avoided
connecting the gates to GND to close the switch.
Parasitic
Diode
M
1
V
IN
V
C
TRL1
V
OUT
Figure 2.4 PHV transistor switch.
Integrated switches for implantable medical devices, in HV-CMOS
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Parasitic
Diodes
M
1
M
2
V
I
N
V
O
UT
V
C
TRL1
V
C
TRL2
DRIVER
Figure 2.5 Switches type B and C connection scheme. Two pvh
transistors are connected in series to control the current flow.
In Figure 2.6 the simulated on
resistance (R
ON
) of the switch (Figure 2.5)
is shown, for the three transistor models (corners) available from the
manufacturer, typical (TM), worst slow (WS – maximum threshold voltage
V
T
) and worst power (WP - minimum threshold voltage V
T
). A W/L =
40000µm/3µm was selected; the length is the minimum possible for phv’s,
the width was selected to comply with 5Ω resistance (Typical transistor,
V
CC
= 2V).
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0
1
2
3
4
5
6
W/L=40000
µ
m/3
µ
m
V
CTRL1,2
=-2V
V
CC
=2V
R
ON
(
Ω
)
V
IN
(V)
TM
WS
WP
Figure 2.6 Dual phv switch (switches B and C) on resistance R
ON
, TM
black, WS red and WP green.
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2.2.2 NMOS High Voltage transistor (nhv)
NHV transistor will be the main transistor (in parallel with phv) for the
Switch A. In Figure 2.7 a vertical cut of a nhv transistor is shown.
NDIFF
NDIFF
PDIFF
FOX
FOX
FOX
FOX
PTUB
NWELL
B
OX
TRENCH
TRENCH
BULK
SOURE
GATE
DRAIN
-
EDGE
-
FOX
DRAIN
HANDLE WAFER
Figure 2.7 NHV transistor vertical cut.
In Figure 2.8 nhv transistor with its parasitic diode is shown, the switch is
opened (preventing current flow) when V
CTRL
is set to 0V. By making a
similar analysis as in 2.2.1, two nhv transistors in series are used (shown
in Figure 2.9).
Parasitic
Diode
M
1
V
I
N
V
C
TR
L1
V
OUT
Figure 2.8 NHV transistor switch.
Integrated switches for implantable medical devices, in HV-CMOS
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M
2
V
OUT
V
C
TRL2
Parasitic
Diodes
M
1
V
IN
V
C
TRL1
DRIVER
Figure 2.9 Two nvh transistors in series switch.
In Figure 2.10 the simulated on
resistance (R
ON
) of the switch (Figure 2.9)
is shown, simulations for the three models, typical (TM), worst slow (WS)
and worst power (WP).
0 1 2 3 4 5
0
20
40
60
80
100
120
140
V
CTRL1,2
=6V
W/L=20000
µ
m/3
µ
m
V
IN
(V)
R
ON
(
Ω
)
TM
WS
WP
Figure 2.10 Switch R
ON
, TM black, WS red and WP green.
2.2.3 High Voltage Transmission gate (TG) for switch
A.
By combining the main switches shown in Figure 2.5 and Figure 2.9 a high
voltage transmission gate switch is obtained as shown in Figure 2.11. The
driver circuit connects V
CTRL1
to 0V, V
CTRL2
to 0V, V
CTRL3
to V
IN
and V
CTRL4
to
Integrated switches for implantable medical devices, in HV-CMOS
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V
OUT
, to open the switch. Because this switch shall control pulses down to
100mV, to close the switch V
CTRL1,2
gates are connected to 2V
CC
voltage
(two times power supply voltage) while V
CTRL3,4
are connected to 0V. 2V
CC
will be also generated in switch A, with the aid of an external capacitor
(section 3.1.2) in a charge pump configuration. In comparison to the
circuit in Fig.2.5, apart from the lower total resistance particularly for the
lower stimuli voltages, the main advantage of the HV TG configuration, is
that it avoids the use of a negative voltage for switching. A negative
voltage even in the case of a isolated technology may, present some
difficulties for the designer.
M
3
M
4
V
C
TRL
3
V
C
TRL4
M
2
V
OUT
V
C
TRL2
Parasitic Diodes
M
1
V
IN
V
C
TRL1
DRIVER1
DRIVER2
Figure 2.11 High voltage transmission gate of Switch A.
In Figure 2.12 the simulated on
resistance (R
ON
) of the switch (Figure
2.11) is shown, all simulations were done for three models, typical (TM),
worst slow (WS) and worst power (WP).
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0 2 4 6 8 10 12 14 16 18
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
R
ON
(
Ω
)
V
IN
(V)
V
CC
=2V
V
Ctrl3,4
=0V
V
Ctrl1,2
=4V
(W/L)
P
=40000
µ
m/3
µ
m
TM
WP
WS
(W/L)
N
=20000
µ
m/3
µ
m
Figure 2.12 High voltage transmission gate of Switch A total on-
resistance R
ON
, TM black, WS red and WP green.
Integrated switches for implantable medical devices, in HV-CMOS
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2.3 Main switch dimension
Transistor sizing was calculated to comply with the 5Ω switch resistance
specified in section 1.3 (with only small deviation in the case of WS
transistors, which was considered acceptable for the sake of a moderate
silicon area). The total resistance of PMOS main MOSFETs of Switch B and
Switch C, are shown in Figure 2.6, while Figure 2.12 shows the equivalent
resistance of Switch A’s TG. The selected main transistor’s dimensions
are:
• For PMOS 40000µm/3µm
• For NMOS 20000µm/3µm (Only Switch A)
It should be pointed out that the approximated resistance of the metal
wires user for routing was calculated. The amount of contacts and metal
wires width, were determined to achieve an approximated 1Ω total
connection resistance in the stimulus path that shall be added to MOSFETs
R
ON
. Total maximum resistance was still considered acceptable for the
application. The detailed metal wire plus contacts resistance calculation is
omitted for the sake of simplicity.
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3 Driver circuitry & complete switch
design
3.1 Basic building blocks
In this section the basic blocks that compose the designed switches
(drivers) are presented.
3.1.1 Level-shifters
A level-shifter (LS) adapts logical signals (0 to V
CC
) to another level that
could be higher or lower than V
CC
or in our case even negative voltage
values. For the design of the switches drivers, different types of level-
shifters were used.
3.1.1.1 NMOS level-shifter
In Figure 3.1 a basic level shifter (from now it will be denoted as
NMOS_LS) is shown, it is a classical circuit to translate a low voltage (LV)
digital signal 0-V
CC
, into a high voltage (HV) one, 0-2V
CC
in this case
[5][27][30]. The circuit is named NMOS_LS because it will drive the gate
of the main NMOS in the TG of Figure 2.11. The “In” signal controls the
output “Out”, the NMOS_LS has two states:
• State “1”: When the “In” signal is V
CC
the M
1
,M
5
and M
6
transistors
are turned on and the output “Out” goes to 2V
CC
voltage which will
be generated by a two times voltage multiplier (section 3.1.2).
• State “0”: When the “In” signal is 0V, the transistors M
2
, M
3
and M
4
are switched on and the output “Out” goes to 0V.
It should be pointed that the circuit in Figure 3.1 has no static power
consumption.
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M
5
M
i1
M
i2
M
i3
M
i4
V
cc
= 2
–
5
V
G
ND
= 0
V
M
4
M
1
M
2
M
3
M
6
2 V
CC
Out
In
G
ND
Figure 3.1 NMOS level-shifter.
Transistor sizes were designed to ensure a stable operation of the
NMOS_LS in the full range of operation for V
CC
from 2 to 5V and a full
charge (from 100m to 10V) or discharge (from 10V to 100mV) of the
output in less than 500ns with a load of 0.18nF corresponding to the
approximated capacitive load of each driver in Figure 2.11. In Table 3.1 a
summary of transistors size is presented.
Table 3.1 NMOS_LS level-shifter transistors dimensions.
Transistors W/L (µm/ µm)
M
i1-4
100/3
M
1,2
60/3
M
3,6
400/3
M
4,5
10/3
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3.1.1.2 2V
CC
level-shifter
The 2V
CC
level-shifter (named 2V
CC
_LS) is a small variation of the
NMOS_LS with only a slight transistor size change. 2V
CC
_LS will be used in
the charge pump of section 3.1.2.
Whilst 2VCC_LS is nearly equal to the one in Figure 3.1, in this work we
opted to provide different names to different circuit blocks, even with only
a small change in circuit topology or layout. Also the original circuit block
names set given at the very first design stages was preserved in this
document, although it may look a bit cumbersome for who is not familiar
with the circuits.
Table 3.2 2V
CC
level-shifter transistors dimensions.
Transistors W/L (µm/ µm)
M
i1-4
100/3
M
1,2
60/3
M
3,6
100/3
M
4,5
10/3
3.1.1.3 Negative level-shifter
In Figure 3.2 the negative level-shifter (NEG_LS) is shown. This LS
translates a logical ‘0’ from 0V at the input, to a negative voltage V
SS
at
the output. The logical ‘1’ is equal to V
CC
at both LV and HV side. The
NEG_LS has two inverted outputs in the HV, the circuit operation can be
described in two states:
• State “1”: When the “In” signal is V
CC
the transistors, M
6
, M
8
, M
11
,
M
13
, M
16
and M
17
are closed and transistors, M
5
, M
9
, M
12
,
M
14
, M
15
and M
18
are open, making the output “Out” to go to V
CC
and “NOut”
go to V
SS
, generated by the V
SS
generator (section 3.1.3).
• State “0”: When the “In” signal is 0V the transistors, M
6
, M
8
, M
11
,
M
13
, M
16
and M
17
are opened and transistors, M
5
, M
9
, M
12
,
M
14
, M
15
and M
18
are closed, making the output “Out” to go to V
SS
and
“NOut” to V
CC
.
Note transistor pairs NMOS-PMOS in parallel were connected to V
SS
, to
ensure a stable NEG_LS operation in the full range of V
CC
and V
SS
.
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M
6
M
i1
M
i2
M
i3
M
i4
V
cc
= 2
–
5V
V
SS
M
5
M
8
M
12
M
14
M
13
V
CC
In
M
18
NOut
M
9
M
16
M
11
Out
GND
M
15
M
17
Figure 3.2 Negative level-shifter.
In Table 3.3 a summary of transistors dimensions is presented.
Table 3.3 Negative level-shifter transistors dimensions.
Transistors W/L (µm/ µm)
M
i1-4
20/3
M
5,6,13,14,15,16
60/3
M
8,9,11,12
10/3
In Figure 3.3 and Figure 3.4 the NEG_LS simulated outputs “Out” and
“NOut” are shown, for a 10KHz square wave input. This and most
simulations in the document were performed for the three models: TM,
WS and WP, but only TM is shown for the sake of simplicity, but also
because no significant difference was observed.
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0.0 50.0µ 100.0µ 150.0µ 200.0µ
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
V
OUT
(V)
Time (s)
V
CC
=2V and V
SS
=-2V
V
CC
=5V and V
SS
=-5V
Figure 3.3 Negative level shifter non inverted output (Out) transient
simulation for V
CC
2V, 5V and V
SS
-2V, -5V.
0.0 50.0µ 100.0µ 150.0µ 200.0µ
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
V
CC
=2V and V
SS
=-2V
V
CC
=5V and V
SS
=-5V
V
NOUT
(V)
Time (s)
Figure 3.4 Negative level shifter inverted output (NOut) transient
simulation, for V
CC
2V, 5V and V
SS
-2V, -5V.
3.1.1.4 SAFEPMOS1 level-shifter
In Figure 3.5 a PMOS level-shifter (named SAFEPMOS1_LS) is shown, to
translate a digital input signal ‘In’ 0-V
CC
, into a HV digital output signal 0-
V
Ref
, with a distinctive full range for V
Ref
from 0 to 16V. The
SAFEPMOS1_LS is a variation of the NMOS_LS, but the output signal “Out”
is connected to V
Ref
through a transmission gate (TG) M
6
and M
7
. Also
transistors M
4
, M
5
, in Figure 3.1, are now substituted by a TG. The
transmission gate is necessary because V
Ref
can be very small (100mV)
and M
6
will not work properly; for small V
Ref
’s current conduction will take
place through M
7
. Transistors M
8
and M
9
, added for the same reason,
Integrated switches for implantable medical devices, in HV-CMOS
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guarantee the stability of the level shifter at low V
Ref
values. Because V
Ref
voltage may be connected directly to the electrodes in tissue contact (see
Section 3.2) and since the gates of transistors M
7
, M
8
and M
9
go to V
CC
when there is no stimulation, if there is a failure in the gate oxide of one
of these transistors, a direct path from V
CC
to tissue may be created. To
prevent this direct path, the gates are commanded through a RC circuit,
where R has an impedance larger than 1MΩ, to limit the current flow into
tissue under a single element failure condition. The LS_P has two states:
• State “1” or “V
Ref
”: When the “In” signal is V
CC
the the output “Out”
goes to V
Ref
.
• State “0”: When the “In” signal is 0V, the output “Out” goes to 0V.
M
5
M
i1
M
i2
M
i3
M
i4
V
cc
= 2
–
5
V
G
ND
= 0
V
M4
M
1
M
2
M3
M
6
V
Ref
Out
In
M
7
R
1
C
1
R
2
C
2
R
3
R
4
C
3
C
4
M8
M
9
G
ND
Figure 3.5 SAFEPMOS1 level-shifter.
Transistor sizes were chosen ensure a full charge (from 100m to 16V) or
discharge (from 16V to 100mV) of the output in less than 500ns with a
load of 0.36nF corresponding to the approximated capacitive gate load of
the large 40000µm/3 µm phv transistor.
In Table 3.4 a summary of transistors sizes is presented.
Table 3.4 SAFEPMOS1 level-shifter transistors dimensions and R, C,
values.
Transistors W/L (µm/ µm)
M
i1-4
20/3
M
1,2
60/3
M
3,6,7
400/3
M
4,5,8,9
10/3
Component Value
C
1,2
(cpoly-poly) 20pF
C
3,4
(cpoly-poly) 5ºpF
R
1,2,3,4
(rpolyh) 500kΩ
The SAFEPMOS1_LS simulated output “Out” is shown for a 10KHz square
wave input and V
CC
= 2V.
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0.0 50.0µ 10 0.0µ 150.0µ 200.0µ
0.0
20.0m
40.0m
60.0m
80.0m
100.0m
V
CC
=2V
V
Out
(V)
Time (s)
V
Ref
=100mV
Figure 3.6 SAFEPMOS1_LS simulated output “Out” with V
Ref
100mV and
V
CC
2V.
0.0 50.0µ 100.0µ 150.0µ 200.0µ
-2
0
2
4
6
8
10
12
14
16
18
V
CC
=2V
V
Ref
=16V
V
Out
(V)
Time (s)
Figure 3.7 SAFEPMOS1_LS simulated output “Out” with V
Ref
16V and
V
CC
2V.
Integrated switches for implantable medical devices, in HV-CMOS
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3.1.1.5 SAFEPMOS2 level-shifter
In Figure 3.8 the SAFEPMOS2 level-shifter (SAFEPMOS2_LS) is shown.
This circuit connects its output, “GATE”, with the input, “V
IN
”, when the
“CTRL” signal is 0V. If CTRL is V
CC
, “GATE” is left in third state. “Φ2N” is
generated by the NEG_LS (section 3.1.1.3) used as an inverter. The
SAFEPMOS2_LS circuit is very similar to the SAFEPMOS1_LS, but with a
few differences:
• All transistors connected to V
IN
(M
4x
, M
5x
, M
6,7
) are implemented
with two transistors connected in series but flipped (Source
connected to Source). This configuration with two diodes connected
in opposite, prevents current circulation even in the case of
negative voltage peaks in V
IN
(remember V
IN
is connected to tissue
and its voltage may vary because of different kinds of coupling).
• The only connection to the output GATE is V
IN
through M
6,7
, which is
controlled by CTRL, allowing to leave GATE in high impedance (third
state) when CTRL is V
CC
.
• As V
IN
can vary from 16V to 100mV, M
4x
, M
5x
, M
6,7
are connected as
a transmission gate, ensuring operation in all the possible ranges.
• As M
4
, M
5
and M
7
gates are connected to V
CC
when no stimulus is
present, for safety reason this could be a problem, as if any of this
transistors oxide is punctured (single failure), there will be a direct
current path into the tissue. The connection of this gates through
an RC circuit, limit this current to acceptable levels (two capacitors
are used to withstand the HV after a failure).
Figure 3.8 SAFEPMOS2 level-shifter.
Integrated switches for implantable medical devices, in HV-CMOS
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In Table 3.5 a summary of transistors sizes is presented.
Table 3.5 SAFEPMOS2 level-shifter transistors dimensions.
Transistors W/L (µm/ µm)
M
i1-4
100/3
M
1,2
60/3
M
6,7
400/3
M
4i,5i
10/3
Component Value
C
(cpoly-poly) 5pF
R (rpolyh) 650kΩ
3.1.2 2V
CC
generator.
The main NMOS transistors in Figure 2.11 require a voltage two times V
CC
.
This voltage is generated on-chip, momentarily during a stimulus, by the
2V
CC
generator shown in Figure 3.9. An external pumping capacitor is
necessary, the 2V
CC
generator has two states:
• State “1”: When the “In” signal is V
CC
, the capacitor C
1
is charged to
V
CC
through M
1
and M
2
. The M
3
transistor is in diode configuration, it
is used to start-up the circuit.
• 2V
CC
state: When the “In” signal is 0V the output “C
ap
” of the
inverter goes to V
CC
. As the capacitor already charged and cannot
discharge because the 2VCC_LS cuts off the transistors M
1
and M
2
the output “2V
CC
” goes to 2xV
CC
volts.
Note: C1 is an external capacitor and its value can vary from tens nF to
few µF, depending on admissible leakages, capacitor footprint size, type,
or stimuli duration.
Integrated switches for implantable medical devices, in HV-CMOS
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M
2
M
i1
M
i2
V
cc
= 2
–
5V
M
3
M
1
V
CC
2V
CC
In
2Vcc
_LS
GND = 0V
C
1
C
ap
R
1
In
G
ND
Figure 3.9 2V
CC
generator, C
1
external.
In Table 3.6 a summary of transistors sizes and components values is
presented.
Table 3.6 2V
CC
generator transistors dimensions and components values.
Transistors W/L (µm/ µm)
M
i1-2
200/3
M
1,2
60/3
M
3
10/3
Component Value
C
1
(external) 1µF (typical)
R
1
(rpolyh) 100Ω
3.1.3 V
SS
generator
The main PMOS transistors of Switches B, C in section 2.2.1, require a
negative voltage (V
SS
) (see also NEG_LS and the NegD of section 3.1.4).
This voltage is generated on-chip by the V
SS
generator shown in Figure
3.10. As the V
SS
is only needed when stimulating, it is only generated
when “CTRL” goes to V
CC
. The generated voltage is V
SS
= -V
CC
, using an
external pump capacitor C
pump
. “CTRLLS” is generated by a NEG_LS block
using the inverted output. The V
SS
generator has two states:
• State “0”: When “CLK” is 0V the node C
AP
is connected to V
CC
through M
i2
and the node V
SS
is connected to GND through M
1
and
M
2
. This effectively charges the external capacitor C
pump
to V
CC
. The
diode is used in the start-up of the circuit.
• -V
CC
state: When “CLK” is V
CC
the node CAP is connected to GND
but the capacitor cannot discharge, so the node V
SS
acquires a
negative voltage of -V
CC
.
Integrated switches for implantable medical devices, in HV-CMOS
technology
37
M
2
M
i1
M
i2
V
CC
= 2
–
5
V
M
1
V
SS
CLK
GND=0V
C
pump
R
1
C
AP
CTRLLS
GND
Figure 3.10 V
SS
generator.
In Table 3.7 a summary of transistors sizes and components value is
presented.
Table 3.7 V
SS
generator transistors dimensions and components values.
Transistors W/L (µm/ µm)
M
i1-2
200/3
M
1,2
60/3
Component Value
C
1
(external) 1µF (typical)
R
1
(rpolyh) 100Ω
3.1.4 Negative driver.
In Figure 3.11 the Negative driver (NegD) is shown. The NegD will be
used in Switch B and Switch C, to connect the gate of the main PMOS (the
output “GATE” of Figure 3.11) to V
SS
, but depending on the control loop
current I
Ref
, of section 3.1.5. When the “CTRL” signal is ‘1’ (V
CC
) GATE
node goes to V
SS
if I
ref
= 0. If the “CTRL” signal is a 0V, the “GATE” is left
in third state. “CTRLS” is generated by a NEG_LS (section 3.1.1.3) and is
in phase with “CTRL”. When I
Ref
≈ 0 and “CTRL” is V
CC
, the transistor M
2
is
closed and “GATE” is connected to V
SS
through M
1
and M
2
, but if I
Ref
is
large enough, M
2
will be open and “GATE” will be connected to GND
through M
3
(and the diode in series). The diode also ensures that when
I
Ref
≈ 0 no conduction between “GATE” and GND occurs. To summarize,
NegD connects “GATE” to a low voltage when CTRL is V
CC
and leaves it in
third state otherwise. The low voltage is either V
SS
if I
Ref
≈ 0 or GND.
Integrated switches for implantable medical devices, in HV-CMOS
technology
38
G
ND
= 0
V
R
1
V
SS
GATE
M
2
M
1
M
3
CT
RLS
CTR
L
L
I
Ref
Figure 3.11 Negative driver.
In Table 3.8 a summary of transistors size and components value is
presented.
Table 3.8 Negative driver transistors dimensions and component values.
Transistors W/L (µm/ µm)
M
1,2,3
600/3
Component Value
R
1
(rpolyh) 683kΩ
Integrated switches for implantable medical devices, in HV-CMOS
technology
39
3.1.5 A novel over voltage V
GS
protection circuit
The circuit in Figure 3.12 shows a PMOS switch M
1
, which may be a large
output driver transistor that may connect the voltage V
IN
to V
OUT
. While
V
DS1
(V
IN
-V
OUT
) may be large for example up to 50V in a HV technology,
V
GS1
is limited to a much lower value, 5V in standard CMOS and upto 12-
18V in a HV technology, because of the gate oxide strength. To turn on
M
1
, a driver may connect its gate to V
SS
(the most negative voltage in the
circuit) but there is a risk of gate puncturing if V
GS1
exceeds maximum
rating. To overcome this problem a voltage control loop is proposed.
V
CTRL
is a low voltage logic signal varying between a low voltage V
CC
(i.e. 3
V) and V
SS
; when V
CTRL
is V
CC
M
2
is turned on if I
Ref
= 0 thus pushing V
G1
to
V
SS
and turning on M
1
. But as I
Ref
increases, the voltage drop through R
1
increases as well and M
2
resistance dramatically increases (up to cutoff)
and V
G1
may reach an equilibrium voltage well above V
SS
. I
Ref
is a function
of V
GS1
voltage because of the n stacked diode-connected M
di
transistors,
which copy their current to the V
G2
node through M
ci
transistors. As V
GS1
increases, I
Ref
increases in a strongly-non linear way and an equilibrium
V
GS1
voltage close to the voltage drop of the stacked M
di
diodes is
achieved. V
GS1
voltage during M
1
conduction is a function of n, the number
of stacked M
di
transistors, their threshold voltage and M
2
, R
1
characteristics. These circuit elements should be designed according to
rated V
GS
voltage for the technology and corner cases.
When V
CTRL
is V
SS
, M
2
transistor is opened and R
2
pushes V
G1
to V
IN
thus M
1
is opened. R
2
has been placed to illustrate circuit operation but may be
substituted by a more complex circuit to avoid static current consumption
when M
1
is turned on, or to increase speed. Note that this control loop
also draws some current when M
1
is on (that can be minimum with a
careful design), but may operate regardless of the V
IN
value ranging to an
arbitrarily large value. A modified version of the circuit will be employed,
to implement Switch B, Switch C circuits, using the driver in the previous
section.
Finally it should be pointed that in regular switching applications M
1
size is
very large thus validating the use of the extra circuit elements count. In
these work a large M
1
(W/L = 40000µm/3µm) dual transistor is employed
and the control loop resulted much smaller.
Integrated switches for implantable medical devices, in HV-CMOS
technology
40
R
1
M
2
M
1
V
CTRL
I
Ref
M
dn
M
d1
M
c1
M
c2
M
c3
V
SS
V
IN
V
OUT
R
2
I
Ref
I
Ref
V
GATE
n transistors
connected as
diodes M
di
.
Figure 3.12 Over voltage V
GS
protection circuit scheme.
In Figure 3.13 the actual employed circuit that generates the current I
Ref
for the NegD (section 3.1.4) is shown. The circuit copies the current
through the M
0
branch to the output transistors M
2
and M
3
. If there is no
stimulation, CTRL is 0V, M
0
is opened so I
Ref
= 0. When CTRL is V
CC
, M
0
is
closed, but only if V
HIGH
is high enough to overcome the V
GS
of the 6
transistors (M
di
) connected as diodes, does current actually flow through
M
0
. Therefore the I
Ref
current is only generated if CTRL is V
CC
and V
High
is
high enough. Note that this is a variation of the control loop previously
proposed (see Figure 3.12), where the reference voltage is measured to
fixed ground instead of V
GATE
, the actual protection circuit is the
combination of the circuit in Figure 3.13 and the negative driver form
section 3.1.4.
Integrated switches for implantable medical devices, in HV-CMOS
technology
41
M
1
Md1
V
SS
G
ND
V
Hihg
IRefB
IRefA
VCTRL
M
d
M
2
M
3
Md2
Md3
Md4
Md5
Md6
M0
Figure 3.13 Implemented over voltage V
GS
protection circuit.
In Table 3.9 a summary of transistors dimensions is presented.
Table 3.9 Implemented over voltage V
GS
protection circuit transistors
dimensions.
Transistors W/L (µm/ µm)
M
D,0,dx
4/4
M
1,2,3
20/3
Integrated switches for implantable medical devices, in HV-CMOS
technology
42
In Figure 3.14 the simulated current reference of the over voltage V
GS
protection circuit is shown, for V
SS
-3V and V
CC
3V sweeping V
High
from
100mV to 16V.
-2 0 2 4 6 8 10 12 14 16 1 8
-200.0n
0.0
200.0n
400.0n
600.0n
800.0n
1.0µ
1.2µ
1.4µ
V
CC
=3V
V
SS
=-3V
I
RefA,B
(A)
V
High
(V)
Figure 3.14 Simulated current reference of the over voltage V
GS
protection circuit for V
SS
-3V and V
CC
3V
3.2 Switch A
In Figure 3.15 the switch A is shown, it is implemented with the following
basic building blocks from section 3.1:
• Two SAFEPMOS1 level-shifters (SAFEPMOS1_LS1(2)) (section
3.1.1.4).
• Two NMOS level-shifters (NMOS_LS1(2)) (section 3.1.1.1).
• One high voltage transmission gate (section 2.2.3).
• Two standard inverters (Inv1(2)).
• 2V
CC
generator (section 3.1.2).
Stimuli conduction is done through the high voltage transmission gate
(M
1
, M
2
, M
3
and M
4
). To turn the switch off (no stimuli conduction) M
1
and
M
2
gates are connected to V
IN
and V
OUT
respectively and M
3
and M
4
to
ground. To turn on the switch (stimuli conduction) M
1
and M
2
gates are
connected to ground and M
3
and M
4
gates to 2V
CC
. The 2V
CC
voltage is
generated during stimulation only. To sum up the complete switch has two
states:
• Closed state: When the signal “CTRL” is 0V the outputs of
SAFEPMOS1_LS1(2) and NMOS_LS1(2) are 0V and 2V
CC
respectively, making conduction possible through the high voltage
transmission gate (M
1
, M
2
, M
3
and M
4
). If the voltages V
IN
, V
OUT
are
high, the M
1
, M
2
branch will conduct most of the current, if not, the
M
3
, M
4
branch will transport most of the current.
Integrated switches for implantable medical devices, in HV-CMOS
technology
43
• Open State: When the signal “CTRL” is V
CC
the outputs of
SAFEPMOS1_LS1(2) and NMOS_LS1(2) are V
High
(V
OUT
) and 0V
respectively, cutting off conduction through high voltage
transmission gate (M
1
, M
2
, M
3
and M
4
) if V
High
≥V
IN
.
GND
M
1
M
2
M
4
V
OUT
Parasitic Diodes
M
3
V
I
N
SAFEPMOS1_LS1
SAFEPMOS1_
LS2
GND
CTRL
V
High
V
OUT
NMOS_LS1
NMOS_LS2
GND
2V
CC
GND
2V
CC
Inv2
GND
V
CC
Inv1
GND
V
CC
CTRL
2V
CC
generator
In
2V
CC
C
ap
C
1
GND
V
CC
CTRL
Figure 3.15 Switch A schematic, M
1,2W/L
=40000µm/3µm and
M
3,4W/L
=20000µm/3µm .
The switch A has 8 PADs:
• CTRL: Opens (V
CC
) and closes (0V) the switch.
• GND: Switch ground.
• V
CC
: Power supply.
• C
ap
: C
1
external capacitor connection for the charge pump.
• 2V
CC
: 2V
CC
generated voltage.
• V
IN
: Switch input.
• V
OUT
: Switch output.
• V
High
:
Reference voltage for closing the switch, normally is just
connected to V
IN
.
In Figure 3.17 the complete layout of the switch A is shown. The total
occupied area is 3.8mm
2
(PADs included). Special care was taken in to
account when making the layout, to prevent DC current to go through the
electrode in case of a single failure. The following precautions were taken:
• Wires conducting V
CC
or 2V
CC
shall not be closer than three times
the minimum metal spacing to V
IN
or V
OUT
.
• Lines conduction V
CC
or 2V
CC
shall cross over V
IN
or V
OUT
lines only if
they have two or more metal layer level of difference (see Figure
3.16 B).
Integrated switches for implantable medical devices, in HV-CMOS
technology
44
• The total resistance of the line going from V
IN
to the high voltage
transmission gate (TG) and from the TG to V
OUT
shall be smaller
than 1Ω
VCC or 2VCC line MX line
VIN or VOUT line MX line
MX
imperfection
MX minimum
spacing
VCC or 2VCC line MX line
VIN or VOUT line MX line
Three
times
MX minimum
spacing
NOT ALLOWED
ALLOWED
A
MX= Metal1,
Meta2 or Metal3
M1(2)
line
M2(3)
line
VIN or VOUT
line
Vcc or
2Vcc
line
Insulator
rupture
NOT ALLOWED
M1
line
M3line VIN or VOUT
line
Vcc or
2Vcc
line
Insulator
rupture
ALLOWED
B
Figure 3.16 Layout taken cautions.
Safety Analysis:
In the circuit in Figure 3.15, M
2
, M
4
and SAFEPMOS1_LS1(2) are in direct
contact to the electrode to tissue. Thus the safety analysis shall consider
any possible failure on these circuit devices when not stimulating. If M
2
’s
gate is punctured there is no problem. If M
4
’s gate is punctured, the tissue
is connected to GND through an unpredictable resistance. In an
implantable device, there is no problem to connect the tissue to a given
voltage; the problem is to allow a DC current through it.
Thus the
medical device manufacturer, that employs the
Switch A, shall guarantee that when not stimulating
all the electrodes are either in high impedance, or
connected to GND. GND shall be the common mode
voltage for biological tissue.
Now the safety condition can be
better described in the following manner: a single failure of a circuit
device shall not connect the electrode to a potential different than GND, or
the current shall be limited to a few µA. SAFEPMOS1_LS fulfils this
requirement as discussed in the corresponding section. Finally, a Drain to
Source short circuit in M
4
, M
2
may connect V
IN
to V
OUT
through M
3
’s, M
1
’s
associated diodes , thus depending on the medical device electrode’s
distribution, the manufacturer shall turn off the stimuli voltage generator
V
IN
when not stimulating.
An overall conclusion is that the proposed Switch cannot guarantee by
itself the safety of the device being implemented. In fact, at least V
IN
to
V
OUT
connection in the case of failure cannot be avoided. From the
implantable medical device perspective, the proposed switch provides a
tool to design a safe device because any single failure may provoke only
leakages to GND (or to V
IN
). According to our knowledge, this is the
Integrated switches for implantable medical devices, in HV-CMOS
technology
45
regular situation in the design of implantable devices. Note for example if
any single failure may provoke leakages either to GND or V
DD
(or any
other fixed potential) the design of a safe device becomes virtually
impossible because at least a common mode voltage is fixed to tissue.
Figure 3.17 Switch A layout, High voltage transmission gate (Red), LS_P
(Blue), LS_N (Green), 2V
CC
generator (Violet) and PADs (Orange).
Integrated switches for implantable medical devices, in HV-CMOS
technology
46
3.3 Switches B and C
3.3.1 Switch B design
In Figure 3.18 the switch B is shown, it is implemented with the following
basic building blocks from section 3.1:
• Two Negative level-shifters (NEG_LS1(2)) (section 1.3).
• Two SAFEPMOS2 level-shifters (SAFEPMOS2_LS1(2)) (section
3.1.1.5).
• Two pvh transistors in series array (see section 2.2.1).
• Two standard drivers (Driv1(2)).
• Two negative drivers (NegD1(2)) (section 3.1.4).
• V
SS
generator (section 3.1.3).
• Over voltage V
GS
protection circuit (Loop) (section 3.1.5)
Stimuli conduction takes place through transistors M
1
, M
2
. CTRL is 0V
when the switch is open (no stimulus), SAFEPMOS2_LS1 connects M
1
’s
gate to V
IN
and SAFEPMOS2_LS2 connects M
2
’s gate to V
OUT
. Since V
IN
and
V
OUT
may vary, only in this way it is guaranteed that V
GS
= 0V to
effectively open the phvs thus the switch. In this case V
SS
= GND and no
static current is consumed. To closed (stimulus), CTRL is set to V
CC
, the
SAFEPMOS2_LS1(2) goes to high impedance and both NegD connect the
gates to either GND or V
SS
to ensure M
1
, M
2
, conduction. The negative
voltage V
SS
is necessary as the stimulus voltage can be very small
(100mV), the V
SS
charge pump provides the momentary negative voltage.
On the other hand, when the stimulus voltage is very high (16V) and for
example V
SS
= -4V the V
GS
~ 20V may damage the gate oxide of M
1
, M
2
.
To overcome this problem, the subcircuit Loop was designed to generate a
high enough current (I
Ref
) to close the path to V
SS
in NegD when
V
High
> 12V. On this scheme V
High
shall be connected to the highest of V
IN
or V
OUT
. In this way the circuit is protected in extreme voltages while
ensuring low impedance when the stimulus voltage is very low. To sum up
the complete switch has two states:
• Open state: When CTRL is 0V, SAFEPMOS2_LS1 open M
1
and
SAFEPMOS2_LS2 open M
2
. V
SS
= GND and no static current is
consumed.
• Closed State: When CTRL is V
CC
, V
SS
generator generates
V
SS
= -V
CC
, NegD1 closes M
1
and NegD
2
closes M2. If V
High
>12V, I
Ref
closes the path to V
SS
and M
1
and M
2
gates are connected to GND,
otherwise they are connected to V
SS
.
Integrated switches for implantable medical devices, in HV-CMOS
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47
Parasitic
Diodes
M
1
M
2
V
I
N
V
O
UT
Driv1
GND
V
DD
V
SS
generator
CLK
V
SS
C
ap
C
1
GND
V
CC
CTRLS
SAFEPMOS2_LS1
GND
V
IN
NegD1
GND
V
SS
I
RefB
SAFEPMOS2_LS2
GND
V
High
NegD2
GND
V
SS
I
RefA
NEG_LS1
V
SS
V
DD
Driv2
GND
V
DD
NEG_LS2
V
SS
V
DD
CTRL
CTRLS
CTRL
CTRLS
CTRL
Φ2N
Φ2N
CTRL
D1
D1
LSD1
LSD1
CTRL
Loop
D2
V
SS
I
RefA
GND
V
High
I
Ref
B
D2
Figure 3.18 Switch B schematic, M
1,2W/L
=40000µm/3µm .
The switches B and have 8 PADs:
• CTRL: Opens (0) and closes (V
CC
) the switch.
• GND: Switch ground.
• V
CC
: Power supply.
• C
ap
: C
1
external capacitor connection, for the V
SS
generator.
• V
SS
: V
SS
negative generated voltage.
• V
IN
: Switch input.
• V
OUT
: Switch output.
• V
High
:
Reference voltage for the protection circuitry. Shall be
connected to the largest voltage when stimulating.
In Figure 3.19 the complete layout of the switch B is shown. The same
precautions as switch A were taken. The total occupied area is 2mm2
(PADs included).
Integrated switches for implantable medical devices, in HV-CMOS
technology
48
Safety Analysis:
In the circuit in Figure 3.18, M
1
, M
2
and SAFEPMOS2_LS1(2) are in direct
contact to the electrode to tissue. Thus the safety analysis shall consider
any possible failure on these circuit nodes when not stimulating. If M
2
’s
gate is punctured there is no problem. If a Drain to Source short circuit in
M
1
, M
2
may connect V
IN
to V
OUT
through M
1
’s, M
2
’s associated diodes.
Thus the medical device manufacturer, that employs
the Switches B, C shall guarantee that when not
stimulating all the electrodes are either in high
impedance, or connected to GND. GND shall be the
common mode voltage for biological tissue.
An overall conclusion is that the proposed Switch cannot guarantee by
itself the safety of the device being implemented. In fact, at least V
IN
to
V
OUT
connection in the case of failure cannot be avoided. From the
implantable medical device perspective, the proposed switch provides a
tool to design a safe device because any single failure may provoke only
leakages to GND (or to V
IN
).
Integrated switches for implantable medical devices, in HV-CMOS
technology
49
Figure 3.19 Switch B layout, PHV opposing diodes array (Red), SLS
(Blue), NegD (Green), LSN(Violet), V
SS
generator (sky blue), loop
(yellow) and PADs (Orange).
Integrated switches for implantable medical devices, in HV-CMOS
technology
50
3.3.2 Switch C
Switch C is a very small variation of switch B, the difference is that DRV2
(see Figure 3.18) is changed by a chain of asymmetrical inverters [6][7],
shown in Figure 3.20. This chain generates a significant delay only in the
low to high transition (see Figure 3.21) making the NegD2 turning on
slower and turning off faster. The delay was introduced to reduce the
short-circuit current generated when the SAFEPMOS2_LS is not yet off
and the NegD2 is on. The short-circuit current is small but the proposed
modification makes it even smaller.
GND
M
i1
M
i2
M
i3
M
i4
V
cc
= 2 – 5V
In
M
i5
M
i6
M
i7
M
i8
Out
Figure 3.20 Implemented asymmetrical invertes chain.
In Table 3.10 a summary of transistor sizes are presented.
Table 3.10 Asymmetrical inverte chain transistors dimensions.
Transistors W/L (µm/ µm)
M
1,2,3,6
10/3
M
4,5
4/30
M
7,8
20/3
From Figure 3.21 to Figure 3.23 some simulation results of the
asymmetrical inverter chain can be shown. Note delay is only generated in
the low to high transition.
Integrated switches for implantable medical devices, in HV-CMOS
technology
51
150.0µ 150.1µ 150.2µ
0
1
2
3
4
5
Times (s)
V
CC
=3.3V
V
IN
V
OUT
Amplitude (V)
Figure 3.21 Simulated asymmetrical inverters chain rising edge.
99.990µ 99.995µ 100.000µ 100.005µ 100.010µ 100.015µ 100.020µ
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Times (s)
Amplitude (V)
V
CC
=3.3V
V
IN
V
OUT
Figure 3.22 Simulated asymmetrical inverters chain falling edge.
Integrated switches for implantable medical devices, in HV-CMOS
technology
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2.0 2.5 3.0 3.5 4.0 4.5 5.0
50.0n
100.0n
150.0n
200.0n
250.0n
300.0n
350.0n
400.0n
450.0n
Delay (s)
V
CC
(V)
WS
TM
WP
Figure 3.23 Simulated delay vs V
CC
.
It should be pointed that, from simulations and measurements, no
significant difference was observed between both circuits (Switch B and
C). However both were included in the available 10mm
2
and in the
following chapter, both were measured like different circuits.
Integrated switches for implantable medical devices, in HV-CMOS
technology
53
4 Measurements
The circuits were fabricated and measured, to compare their performance
and select the best option for a future project. A first conclusion is that the
three circuits worked properly, switching the load as expected. In this
chapter, the full measurement result of switches A, B and C, are
presented. Switch on resistance, transient response, power consumption,
leakages, crosstalk, charge injection and ESD robustness, measured
characteristics will be shown in this order.
4.1 Switch impedance (RON)
4.1.1 R
ON
with 2V
CC
(switch A) and V
SS
(switch B, C)
In Figure 4.1 the setup used to measure R
ON
is shown (2V
CC
and V
SS
were
generated with the aid of an external supply). R
ON
measurements were
obtained by sweeping V
Stimuli
from 100mV to 16V for V
CC
= 2, 2.4, 3.3, 4
and 5V, the measured values are shown from Figure 4.2 to Figure 4.9.
500
Ω
ΩΩ
Ω
V
Stimuli
V
IN
V
OUT
C
ap
2
V
CC
V
CC
CTRL
V
High
GND
Switch
A
500
Ω
ΩΩ
Ω
V
Stimuli
V
IN
V
OUT
C
ap
V
SS
V
CC
CTRL
V
High
GND
Switches
B & C
V
CC
GND
GND
GND
3
1/2
digits
multimeter
3
1/2
digits
multimeter
Figure 4.1 R
ON
measurement circuit configuration.
Integrated switches for implantable medical devices, in HV-CMOS
technology
54
0 2 4 6 8 10 12 14 16
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
SWITCH A
R
ON
(
Ω
)
V
Stimuli
(V)
V
CC
= 2V
V
CC
= 2.4V
V
CC
= 3.3V
V
CC
= 4V
V
CC
= 5V
Figure 4.2 Switch A R
ON
for different stimuli voltage V
stimuli
and supply
voltage V
CC
. The voltage doubler is supposed to generate 2V
CC
voltage.
0 2 4 6 8 10 12 14 16
3
4
5
6
7
8
SWITCH B
V
CC
= 2V
V
CC
= 2.4V
V
CC
= 3.3V
V
CC
= 4V
V
CC
= 5V
R
ON
(
Ω
)
V
Stimuli
(V)
Figure 4.3 Switch B R
ON
for different stimuli voltage V
stimuli
and supply
voltage V
CC
. The negative voltage generator is supposed to provide
V
SS
= (-V
CC
) voltage.
Integrated switches for implantable medical devices, in HV-CMOS
technology
55
0 2 4 6 8 10 12 14 16 18
3
4
5
6
7
8
9
SWITCH C
V
CC
= 2V
V
CC
= 2.4V
V
CC
= 3.3V
V
CC
= 4V
V
CC
= 5V
R
ON
(
Ω
)
V
Stimuli
(V)
Figure 4.4 Switch C R
ON
for different stimuli voltage V
stimuli
and supply
voltage V
CC
. The negative voltage generator is supposed to provide
V
SS
= (-V
CC
) voltage.
-1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
V
CC
=2V
R
ON
(
Ω
)
V
Stimuli
(V)
Switch A
Switch B
Switch C
Figure 4.5 Switch A, B and C R
ON
comparison, for V
CC
= 2V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
56
-2 0 2 4 6 8 10 12 14 16 18
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
Switch A
Switch B
Switch C
V
CC
=2.4V
R
ON
(
Ω
)
V
Stimuli
(V)
Figure 4.6 Switch A, B and C R
ON
comparison, for V
CC
= 2.4V.
0 2 4 6 8 10 12 14 16 18
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
Switch A
Switch B
Switch C
V
Stimuli
(V)
R
ON
(
Ω
)
V
CC
=3.3V
Figure 4.7 Switch A, B and C R
ON
comparison, for V
CC
= 3.3V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
57
-2 0 2 4 6 8 10 12 14 16 18
3.5
4.0
4.5
5.0
5.5
6.0
R
ON
(
Ω
)
V
Stimuli
(V)
V
CC
=4V
Switch A
Switch B
Switch C
Figure 4.8 Switch A, B and C R
ON
comparison, for V
CC
= 4V.
-2 0 2 4 6 8 10 12 14 16 18
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
Switch A
Switch B
Switch C
R
Key
(
Ω
)
V
Stimuli
(V)
V
CC
=5V
Figure 4.9 Switch A, B and C R
ON
comparison, for V
CC
= 5V.
The measured R
ON
of switches A, B and C are within expected values,
considering both MOSFET and wires resistance, for all V
Stimuli
and V
CC
ranges. The result tough exceeds a bit the target 5Ω value for the lower
V
Stimuli
, it is assumed to comply with specifications in section 1.3.
Integrated switches for implantable medical devices, in HV-CMOS
technology
58
4.1.2 R
ON
without charge pump: without 2V
CC
(Switch
A) or V
SS
(Switch B, C).
In some cases, the user may suppress the external capacitor (thus the
charge pump) for the sake of a simpler circuit, if no low stimulus voltages
will be required. In Figure 4.10 the setup used to measure R
ON
is shown
(2V
CC
connected to V
CC
and V
SS
connected to ground). R
ON
measurement
was obtained sweeping V
Stimuli
from 100mV to 16V, for V
CC
2, 2.4, 3.3, 4
and 5V, the measured result are shown from Figure 4.11 to Figure 4.13.
500
Ω
ΩΩ
Ω
V
Stimuli
V
IN
V
OUT
C
ap
2
V
CC
V
CC
CTRL
V
High
GND
Switch
A
500
Ω
ΩΩ
Ω
V
Stimuli
V
IN
V
OUT
C
ap
V
SS
V
CC
CTRL
V
High
GND
Switches
B & C
V
CC
GND
GND
GND
3
1/2
digits
multimeter
3
1/2
digits
multimeter
GND
Figure 4.10 R
ON
measurement circuit configuration.
-2 0 2 4 6 8 10 12 14 16 18
4
6
8
10
12
14
16
SWITCH A
V
DD
= 2V
V
DD
= 2.4V
V
DD
= 3.3V
V
DD
= 4V
V
DD
= 5V
R
ON
(
Ω
)
V
Stimuli
(V)
Figure 4.11 Switch A R
ON
for different stimuli voltage V
stimuli
and supply
voltage V
CC
. 2V
CC
connected to V
CC
Integrated switches for implantable medical devices, in HV-CMOS
technology
59
2 4 6 8 10 12 14 16 18
0.0
20.0
40.0
60.0
80.0
100.0
SWITCH B
RON (
Ω
)
VStimuli (V)
VCC= 2V
VCC= 2.4V
VCC= 3.3V
VCC= 4V
VCC= 5V
Figure 4.12 Switch B R
ON
for different stimuli voltage V
stimuli
and supply
voltage V
CC
. V
SS
connected to ground
2 4 6 8 10 12 14 16 18
0.0
20.0
40.0
60.0
80.0
100.0
R
ON
(
Ω
)
SWITCH C
V
Stimuli
(V)
V
DD
= 2V
V
DD
= 2.4V
V
DD
= 3.3V
V
DD
= 4V
V
DD
= 5V
Figure 4.13 Switch C R
ON
for different stimuli voltage V
stimuli
and supply
voltage V
CC
. V
SS
connected to ground
As expected the R
ON
impedances of switches B and C get larger when
V
Stimuli
is low (see Figure 4.12 and Figure 4.13) without the V
SS
generator,
because the gates of the main PMOS are put to 0V to close the switches,
making V
GS
very small though making the transistor impedance large. For
switch A the R
ON
impedance is quite low in all V
Stimuli
regions because of
the high voltage transmission gate configuration (see Figure 3.15), but
not as low as specified in section 1.3 V
Stimuli
for certain values.
Integrated switches for implantable medical devices, in HV-CMOS
technology
60
4.2 Voltage stimuli with 2V
CC
(switch A) and V
SS
(switches B, C)
In Figure 4.14 the setup used for the measurement of voltage stimuli
response of the three switches is shown. The measurement was done with
V
Stimuli
100mV, 5V and 16V and V
CC
2V, 2.8V and 5V, turning on and off
the switches with a 10kHz, 50% duty cycle, square wave.
V
CC
V
SS
V
Stimuli
V
IN
V
OUT
C
ap
2V
CC
CTRL
V
High
GND
Switch A
GND
R
Meas
C1
V
CC
V
Stimuli
V
IN
V
OUT
C
ap
CTRL
V
High
GND
Switch B & C
GND
R
Meas
C1
V
CC
0V
50% duty cycle
square wave
Oscilloscope Oscilloscope
V
CC
0V
50% duty cycle
square wave
GND
GND
Figure 4.14 Voltage stimuli measurement setup, R
Meas
=500Ω.
From Figure 4.15 to Figure 4.23 the measurement results of voltage
stimuli are shown.
0.0 50.0µ 100.0µ 150.0µ
-150.0m
-100.0m
-50.0m
0.0
50.0m
100.0m
150.0m
200.0m
250.0m
Switch A
Switch B
Switch C
V
CC
=2V
V
Stimuli
=100mV
V
OUT
(V)
Time (s)
Figure 4.15 Swtiches A,B and C voltage stimuli response for
V
Stimuli
=100mV and V
CC
=2V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
61
0.0 50.0µ 100.0µ 150.0µ
-300.0m
-200.0m
-100.0m
0.0
100.0m
200.0m
300.0m
400.0m
V
Stimuli
=100mV
V
CC
=2.8V
V
OUT
(V)
Time (s)
Switch A
Switch B
Switch C
Figure 4.16 Swtiches A,B and C voltage stimuli response for
V
Stimuli
=100mV and V
CC
=2.8V.
0.0 50.0µ 100.0µ 150.0µ
-400.0m
-300.0m
-200.0m
-100.0m
0.0
100.0m
200.0m
300.0m
400.0m
500.0m
Switch A
Switch B
Switch C
V
CC
=5V
V
Stimuli
=100mV
V
OUT
(V)
Time (s)
Figure 4.17 Swtiches A,B and C voltage stimuli response for
V
Stimuli
=100mV and V
CC
=5V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
62
0.0 50.0µ 1 00.0µ 150.0µ
0
1
2
3
4
5
6
Switch A
Switch B
Switch C
V
CC
=2V
V
Stimuli
=5V
V
OUT
(V)
Time (s)
Figure 4.18 Swtiches A,B and C voltage stimuli response for
V
Stimuli
=5V and V
CC
=2V.
0.0 50.0µ 100.0µ 150.0µ
0
1
2
3
4
5
6
V
Stimuli
=5V
V
CC
=2.8V
Switch A
Switch B
Switch C
V
OUT
(V)
Time (s)
Figure 4.19 Swtiches A,B and C voltage stimuli response for
V
Stimuli
=5V and V
CC
=2.8V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
63
0.0 50.0µ 100.0µ 150.0µ
0
1
2
3
4
5
6
Switch A
Switch B
Switch C
V
Stimuli
=5V
V
CC
=5V
V
OUT
(V)
Time (s)
Figure 4.20 Swtiches A,B and C voltage stimuli response for
V
Stimuli
=5V and V
CC
=5V.
0.0 50.0µ 100.0µ 150.0µ
-2
0
2
4
6
8
10
12
14
16
18
Switch A
Switch B
Switch C
V
CC
=2V
V
Stimuli
=16V
V
OUT
(V)
Time (s)
Figure 4.21 Swtiches A,B and C voltage stimuli response for
V
Stimuli
=16V and V
CC
=2V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
64
0.0 50.0µ 100.0µ 150.0µ
-2
0
2
4
6
8
10
12
14
16
18
V
Stimuli
=16V
V
CC
=2.8V
Switch A
Switch B
Switch C
V
OUT
(V)
Time (s)
Figure 4.22 Swtiches A,B and C voltage stimuli response for
V
Stimuli
=16V and V
CC
=2.8V.
0.0 50.0µ 100.0µ 150. 0µ
-2
0
2
4
6
8
10
12
14
16
18
20
Switch A
Switch B
Switch C
V
CC
=5V
V
Stimuli
=16V
V
OUT
(V)
Time (s)
Figure 4.23 Swtiches A,B and C voltage stimuli response for
V
Stimuli
=16V and V
CC
=5V.
As specified in section 1.3, the three designed switches are capable of
delivering stimuli pulses form 100mV to 16V, for V
CC
ranging from 2V to
5V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
65
4.3 ON/OFF time
ON/OFF time was measured for voltage stimuli application, using the
setup of Figure 4.14, for the three switches. In Figure 4.24 and Figure
4.25 a rising and falling edge of the three switches is shown, all the
measured delays were below 500ns complying with specified in section
1.3.
-1.5µ -1.0µ -500.0n 0.0 500.0n 1.0µ 1.5µ
-2
0
2
4
6
8
10
12
14
16
18
20
V
CC
=2V
V
Stimuli
=16V
Switch A
Switch B
Switch C
V
OUT
(V)
X Axis Title
Figure 4.24 Measured rising edge transient response, for V
CC
2V and
V
Stimuli
16V.
-1.5µ -1.0µ -500.0n 0.0 500.0n 1.0µ 1.5µ
-2
0
2
4
6
8
10
12
14
16
18
Switch A
Switch B
Switch C
V
CC
=2V
V
Stimuli
=16V
V
OUT
(V)
Time (s)
Figure 4.25 Measured falling edge transient response, for V
CC
2V and
V
Stimuli
16V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
66
As expected the rising edge of the switch C is slower than Switch B due to
the adding off asymmetrical inviters that affect only one edge. The 200n
delay is within the expected values as shown in Figure 3.23.
4.4 Power consumption
4.4.1 Static power consumption
V
CC
current was measured for the switches opened for V
CC
, 2, 2.8, 3.3, 4
and 5V and V
Stimuli
2.4V and 16V. The experimental setup for this measure
is shown in Figure 4.26.
3
1/2
digits
multimeter
500
Ω
ΩΩ
Ω
V
Stimuli
V
IN
V
OUT
C
ap
2
V
CC
CTRL
V
High
GND
Switch
A
GND
GND
GND
V
CC
R
Meas
500Ω
ΩΩ
Ω
V
Stimuli
V
IN
V
OUT
C
ap
V
SS
CTRL
V
High
GND
Switch
B & C
GND
GND
3
1/2
digits
multimeter
GND
V
CC
R
Meas
GND
C1
C1
Figure 4.26 Static power consumption measurement setup, R
Meas
=1MΩ.
In all cases for the three switches (A, B and C), static consumption was
below 5nA, complying with specifications in section 1.3.
Integrated switches for implantable medical devices, in HV-CMOS
technology
67
4.4.2 Dynamic power consumption with charge pumps
connected
V
CC
current was measured for the switches being opened and closed with a
frequency of 10Hz, 100Hz, 1kHz, 2kHz, 4kHz, 6kHz, 8kHz and 10KHz
(50% duty cycle) for V
CC
2, 2.8, 3.3, 4 and 5V and V
Stimuli
2.4V and 16V.
The setup used to measure is shown in Figure 4.27, while the results are
shown from Figure 4.28 to Figure 4.31.
CV
cc
3
1/2
digits
multimeter
500
Ω
ΩΩ
Ω
V
Stimuli
V
IN
V
OUT
C
ap
2
V
CC
CTRL
V
High
GND
Switch
A
GND
GND
GND
V
CC
R
Meas
500
Ω
ΩΩ
Ω
V
Stimuli
V
IN
V
OUT
C
ap
V
SS
CTRL
V
High
GND
Switch B & C
GND
GND
3
1/2
digits
multimeter
GND
V
CC
R
Meas
GND
C1
C1
CV
cc
Figure 4.27 Dynamic power consumption measurement setup. C1=1µF
external capacitor was utilized.
0.0 2.0k 4.0k 6.0k 8.0k 10.0k
0.0
1.0µ
2.0µ
3.0µ
4.0µ
5.0µ
6.0µ
7.0µ
8.0µ
9.0µ
10.0µ
11.0µ
12.0µ
13.0µ
14.0µ
Switch A
Frequency (Hz)
I
V
CC
(A)
V
Stimuli
=16V
V
CC
=2V
V
CC
=2.8V
V
CC
=3.3V
V
CC
=4V
V
CC
=5V
Figure 4.28 Switch A dynamic power consumption measurement for
V
Stimuli
=16V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
68
0.0 2.0k 4.0k 6.0k 8.0k 10. 0k
0.0
2.0µ
4.0µ
6.0µ
8.0µ
10.0µ
12.0µ
14.0µ
16.0µ
18.0µ
20.0µ
22.0µ
24.0µ
26.0µ
28.0µ
Switch A
V
CC
=2V
V
CC
=2.8V
V
CC
=3.3V
V
CC
=4V
V
CC
=5V
V
Stimuli
=2.4V
I
V
CC
(A)
Frequency (Hz)
Figure 4.29 Switch A dynamic power consumption measurement for
V
Stimuli
=2.4V.
0.0 2.0k 4.0k 6.0k 8.0k 10.0k
0.0
2.0µ
4.0µ
6.0µ
8.0µ
10.0µ
12.0µ
14.0µ
16.0µ
18.0µ
20.0µ
22.0µ
24.0µ
26.0µ
28.0µ
30.0µ
32.0µ
34.0µ
36.0µ
38.0µ
V
Stimuli
=16V
I
V
DD
(A)
Frequency (Hz)
Switch B V
CC
=2V
Switch B V
CC
=2.8V
Switch B V
CC
=3.3V
Switch B V
CC
=4V
Switch B V
CC
=5V
Switch C V
CC
=2V
Switch C V
CC
=2.8V
Switch C V
CC
=3.3V
Switch C V
CC
=4V
Switch C V
CC
=5V
Figure 4.30 Switches B and C dynamic power consumption measurement
for V
Stimuli
=16V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
69
0.0 2.0k 4.0k 6.0k 8.0k 10.0k
0.0
10.0µ
20.0µ
30.0µ
40.0µ
50.0µ
60.0µ
V
Stimuli
=2.4V
I
V
CC
(A)
Frequency (Hz)
Switch B V
CC
=2V
Switch B V
CC
=2.8V
Switch B V
CC
=3.3V
Switch B V
CC
=4V
Switch B V
CC
=5V
Switch C V
CC
=2V
Switch C VDD 2.8V
Switch C VDD 3.3V
Switch C VDD 4V
Switch C VDD 5V
Figure 4.31 Switches B and C dynamic power consumption measurement
for V
Stimuli
= 2.4V.
Note that the dynamic power consumption of Switch A is approximately
proportional to frequency, indicating that power consumption is due to the
repetitive charge-discharge of gate and parasitic capacitors. In the case of
switches B and C, power consumption has a fixed floor for large VStimuli
values corresponding to the current through the protective loop of section
3.1.5.
4.5 Leakage currents
Leakage currents were measured for the switches opened, V
Stimuli
16V and
V
CC
2, 2.8, 3.3, 4 and 5V, the measurement setup is shown in Figure 4.32.
V
CC
V
SS
V
Stimuli
V
IN
V
OUT
C
ap
2
V
CC
CTRL
V
High
GND
Switch
A
GND
GND
R
Meas
C1
3
1/2
digits
multimeter
V
CC
V
Stimuli
V
IN
V
OUT
C
ap
CTRL
V
High
GND
Switch
B & C
GND
GND
R
Meas
C1
3
1/2
digits
multimeter
GND
Figure 4.32 Leakage current measurement setup, R
Meas
=1MΩ.
The measured leakage current for all cases was below 1nA (in the
precision boundaries of the setup of Fig.4.20).
Integrated switches for implantable medical devices, in HV-CMOS
technology
70
4.6 Crosstalk
An implantable medical device generally has more than one stimulus
channels and when one channel switch closes (stimuli pass) the others
channel switches opens. Because of the conductive tissue, an electric
pulse in an electrode causes also a voltage pulse in the other ones
connected near the former. If the switches that block current flow from/to
electrodes were ideal, no current should exist trough them when open.
But real switches allow some current to pass, this phenomenon is called
crosstalk. In Figure 4.33 the setup used to measure crosstalk is shown,
with V
Stimuli
0 and 16V for V
CC
2.8V. The measurement results are shown
form Figure 4.34 to Figure 4.37.
V
CC
V
SS
V
Stimuli
V
IN
V
OUT
C
ap
2V
CC
CTRL
V
High
GND
Switch
A
GND
R
Meas
C1
V
CC
V
Stimuli
V
IN
V
OUT
C
ap
CTRL
V
High
GND
Switch
B & C
GND
R
Meas
C1
GND
8V
0V
50% duty cycle
square wave
Oscilloscope
8V
0V
50% duty cycle
square wave
Oscilloscope
Figure 4.33 Crosstalk measurement setup.
Integrated switches for implantable medical devices, in HV-CMOS
technology
71
0.0 100.0n 200.0n
-2.0m
0.0
2.0m
4.0m
6.0m
8.0m
10.0m
12.0m
14.0m
V
CC
=2.8V
V
Stimuli
=16V
Crosstalk Current (A)
Time (s)
Switch A
Switch B
Switch C
Figure 4.34 Rising edge crosstalk current, for V
Stimuli
=16V and V
CC
=2.8V.
0.0 100.0n 200.0n
-12.0m
-10.0m
-8.0m
-6.0m
-4.0m
-2.0m
0.0
2.0m
V
CC
=2.8V
V
Stimuli
=16V
Switch A
Switch B
Switch C
Crosstalk Current (A)
Time (s)
Figure 4.35 Falling edge crosstalk current, for V
Stimuli
=16V and V
CC
=2.8V.
Integrated switches for implantable medical devices, in HV-CMOS
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72
0.0 100.0n 200.0n
-2.0m
0.0
2.0m
4.0m
6.0m
8.0m
10.0m
12.0m
V
CC
=2.8V
V
Stimuli
=0V
Switch A
Switch B
Switch C
Crosstalk Current (A)
Tiempo (s)
Figure 4.36 Rising edge crosstalk current, for V
Stimuli
=0V and V
CC
=2.8V
0.0 100.0n 200.0n
-12.0m
-10.0m
-8.0m
-6.0m
-4.0m
-2.0m
0.0
2.0m
V
cc
=0V
V
Stimuli
=0V
Switch A
Switch B
Switch C
Corsstalk Current (A)
Time (s)
Figure 4.37 Falling edge crosstalk current, for V
Stimuli
=0V and V
CC
=2.8V
In all cases, the integrated charge going into the switches is
approximately 0.6nC for the switch A and 0.3nC for switches B and C, this
charges includes the charge introduced by the oscilloscope probes. The
oscilloscopes charge was measured in 0.2nC, so the actual charge going
into the switches is 0.4nC for switch A and 0.1nC for switches B and C. To
compare, in Figure 4.38 and Figure 4.39 the simulated crosstalk current is
shown, the charge going into the switches is 0.5nC for switch A and
0.075nC for switches B and C. It should be highlighted the accuracy of the
simulations when compared to measured results, as well as the fact that
crosstalk resulted 4 times less in the case of switches B and C.
Integrated switches for implantable medical devices, in HV-CMOS
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73
0.0 5.0µ 10.0µ 15.0µ 20.0µ
-1.0m
-500.0µ
0.0
500.0µ
1.0m
Switch A
Crosstalk current (A)
Time (s)
Figure 4.38 Switch A simulated crosstalk current.
-2.5µ 0.0 2.5µ 5.0µ 7.5µ 10.0µ 12.5µ 15.0µ
-200µ
-150µ
-100µ
-50µ
0
50µ
100µ
150µ
200µ
Switches B and C
Crosstalk Current (A)
Time (s)
Figure 4.39 Switches B and C simulated crosstalk current.
Switches B and C present a much smaller crosstalk, because the switches
are close by connecting V
OUT
with the gate of transistor M
2
(see Figure
3.18), instead of switch A that connects M
2
gate to 0V (see Figure 3.15).
Integrated switches for implantable medical devices, in HV-CMOS
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74
4.7 Current stimuli (charge injection)
In Figure 4.40 the setup used for measuring current stimuli response of
the three switches is shown. The idea is to use the designed switches to
connect/disconnect a current source to tissue instead of a voltage, which
is a usual configuration in medical devices. The current source was
implemented with an opamp and a NPN bipolar transistor and switches
were turned on and off with and 10kHz 50% duty cycle square wave.
In Fig.4.28 R
Meas
emulates the tissue load. In the case of an ideal current
source, the current through the load shall be an ideal square current
pulse. But because of charge injection at the switch turn on/off, a
undesired current peak can be observed.
V
IN
R
Meas
V
High
V
CC
V
SS
V
Stimuli
V
IN
V
OUT
C
ap
2V
CC
CTRL
GND
Switch
A
GND
R
pol
C1
V
CC
V
OUT
C
ap
CTRL
V
High
GND
Switch
B & C
R
Meas
C1
V
CC
0V
50% duty cycle
square wave
V
CC
0V
50% duty cycle
square wave
GND
Oscilloscope
-
+
V
Ref
GND
I
Load
Figure 4.40 Current stimuli measurement setup.
Integrated switches for implantable medical devices, in HV-CMOS
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75
4.7.1 Current stimuli sweep with 2V
CC
(switch A) and
V
SS
(switches B, C)
From Figure 4.41 to Figure 4.45 the measured transient current pulses
when sweeping the stimuli current (see Figure 4.40) from 200µA to 10mA,
for V
Stimuli
= 4V and V
CC
= 2.8V are shown.
0.0 10.0µ 20.0µ 30.0µ 40.0µ 50.0µ 60.0µ
0.0
100.0µ
200.0µ
300.0µ
400.0µ
500.0µ
600.0µ
700.0µ
800.0µ
900.0µ
1.0m
1.1m
1.2m
1.3m
V
CC
=2.8V
V
Stimuli
=4V
I
Switch
(A)
Time (s)
Switch A
Switch B
Switch C
Figure 4.41 Measured 200µA current stimulus pulse for V
Stimuli
=4V and
V
CC
=2.8V.
0.0 10.0µ 20.0µ 30.0µ 40.0µ 50.0µ 60.0µ
0.0
200.0µ
400.0µ
600.0µ
800.0µ
1.0m
1.2m
1.4m
1.6m
1.8m
2.0m
2.2m
2.4m
V
CC
=2.8V
V
Stimuli
=4V
I
Switch
(A)
Time (s)
Switch A
Switch B
Switch C
Figure 4.42 Measured 400µA current stimulus pulse for V
Stimuli
=4V and
V
CC
=2.8V.
Integrated switches for implantable medical devices, in HV-CMOS
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0.0 10.0µ 20.0µ 30.0µ 40.0µ 50.0µ 60.0µ
500.0µ
1.0m
1.5m
2.0m
2.5m
3.0m
3.5m
4.0m
4.5m
V
CC
=2.8V
V
Stimuli
=4V
I
Swtich
(A)
Time (s)
Switch A
Switch B
Switch C
Figure 4.43 Measured 1mA current stimulus pulse for V
Stimuli
=4V and
V
CC
=2.8V.
0.0 10.0µ 20.0µ 30.0µ 40.0µ 50.0µ 60.0µ
0.0
500.0µ
1.0m
1.5m
2.0m
2.5m
3.0m
3.5m
4.0m
4.5m
5.0m
5.5m
6.0m
6.5m
7.0m
V
CC
=2.8V
V
Stimuli
=4V
Switch A
Switch B
Switch C
I
Switch
(A)
Time (s)
Figure 4.44 Measured 2mA current stimulus pulse for V
Stimuli
=4V and
V
CC
=2.8V.
Integrated switches for implantable medical devices, in HV-CMOS
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0.0 10.0µ 20.0µ 30.0µ 40.0µ 50.0µ 60.0µ
0.0
2.0m
4.0m
6.0m
8.0m
10.0m
12.0m
14.0m
16.0m
18.0m
20.0m
22.0m
24.0m
26.0m
28.0m
30.0m
32.0m
V
CC
=2.8V
V
Sitmuli
=4V
Switch A
Switch B
Switch C
I
Swtich
(A)
Time (s)
Figure 4.45 Measured 10mA current stimulus pulse for V
Stimuli
=4V and
V
CC
=2.8V.
4.7.2 V
Stimuli
sweep with 2V
CC
(switch A)and V
SS
(switches B, C)
From Figure 4.46 to Figure 4.48 the measured transient current pulses
when sweeping V
Stimuli
(see Figure 4.40) from 2V to 16V, for a load current
of 100µA and V
CC
2.8V, are shown.
0.0 10.0µ 20.0µ 30.0µ 40.0µ 50.0µ 60.0µ
-200.0µ
-100.0µ
0.0
100.0µ
200.0µ
300.0µ
400.0µ
500.0µ
600.0µ
700.0µ
800.0µ
900.0µ
1.0m
1.1m
1.2m
1.3m
1.4m
1.5m
1.6m
V
CC
=2.8V
Switch A
V
Stimuli
=2V
V
Stimuli
=3V
V
Stimuli
=5V
V
Stimuli
=10V
V
Stimuli
=16V
I
Switch
(A)
Time (s)
Figure 4.46 Switch A measured 100µA current stimulus pulse for V
Stimuli
from 2V to 16V and V
CC
=2.8V.
Integrated switches for implantable medical devices, in HV-CMOS
technology
78
0.0 10.0µ 20.0µ 30.0µ 40.0µ 50.0µ 60.0µ
-100.0µ
0.0
100.0µ
200.0µ
300.0µ
400.0µ
500.0µ
600.0µ
700.0µ
800.0µ
900.0µ
1.0m
1.1m
1.2m
1.3m
1.4m
1.5m
1.6m
V
CC
=2.8V
Switch B
I
Switch
(A)
Time (s)
V
Stimuli
=2V
V
Stimuli
=3V
V
Stimuli
=5V
V
Stimuli
=10V
V
Stimuli
=16V
Figure 4.47 Switch B measured 100µA current stimulus pulse for V
Stimuli
from 2V to 16V and V
CC
=2.8V.
0.0 10.0µ 20.0µ 3 0.0µ 40.0µ 50.0µ 60.0 µ
-200.0µ
-100.0µ
0.0
100.0µ
200.0µ
300.0µ
400.0µ
500.0µ
600.0µ
700.0µ
800.0µ
900.0µ
1.0m
Time (s)
I
Switch
(A)
V
CC
=2.8V
Switch C
V
Stimuli
=2V
V
Stimuli
=3V
V
Stimuli
=5V
V
Stimuli
=10V
V
Stimuli
=16V
Figure 4.48 Switch C measured 100µA current stimulus pulse for V
Stimuli
from 2V to 16V and V
CC
=2.8V.
As specified in section 1.3, the three designed switches are capable of
delivering stimuli pulses form 10µA to 30mA, for V
CC
ranging from 2V to
5V. Significant current spikes and current diminishments were detected
when opening or closing the switches, due to the charge injected (NHV
transistors) or taken (PHV transistors) by the main transistors
switches (Figure 3.15 and Figure 3.18). In Figure 4.49 the measured
injected charge for 100µA stimulus current is shown.
Integrated switches for implantable medical devices, in HV-CMOS
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79
0 2 4 6 8 10 12 14 16 18
-1.0n
0.0
1.0n
2.0n
3.0n
4.0n
V
CC
=2.8V
Charge (C)
V
Stimuli
(V)
Swtich A
Swtich B or C
Figure 4.49 Measured injected charge, 100µA current stimulus pulse for
V
Stimuli
from 2V to 16V and V
CC
=2.8V.
4.8 ESD testing
ESD testing was performed using an ESD gun “ESD Simulator NSG435”
from Schaffner Instruments, that deliver ESD test pulses complying with
the HBM (ESD Human Body Model) described in section 7.1. The test was
carried by delivering a positive and negative ESD pulse to each pad of the
three switches, with different amplitude values, with and without power
supply connected. In Table 4.1 a summery of the test to be performed is
presented.
Table 4.1 Normalized ESD conditions to be tested.
Level 0 1 2 3
No power
supply
HV pads
500V 1kV 2kV 6kV
No power
supply
Other pads
250V 500V 1kV 2kV
Power supply
HV pads 500V 1kV 2kV 6kV
Power supply
Other pads 250V 500V 1kV 2kV
The pass/fail criterion to determine the test success after ESD pulse
injection includes: the switches must work properly (OPEN and CLOSE)
and static power consumption must be normal (below 20nA) , after the
induced ESD event.
Integrated switches for implantable medical devices, in HV-CMOS
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In Table 4.2 the summery of the test result is shown.
Table 4.2 ESD test results.
Level Switch A Switch B Switch C
0 No power
supply PASS PASS PASS
0 Power
supply PASS PASS PASS
1 No power
supply FAIL
1
PASS PASS
1 Power
supply PASS PASS PASS
2 No power
supply FAIL
1
PASS PASS
2 Power
supply FAIL
1
PASS PASS
3 No power
supply FAIL
1
PASS PASS
3 Power
supply FAIL
1
PASS PASS
Note 1: Failed to open properly.
A very important conclusion is that the ESD strength of Switches B and C,
is much higher than in the case of Switch A. The reason is that for the
target process and in general, large NMOS like the ones in the TG of
Figure 2.11, are much sensitive to ESD (a brief explanation is detailed in
Annex A)
Integrated switches for implantable medical devices, in HV-CMOS
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5 Conclusions
Throughout this thesis work, a study of HV-CMOS technology applied to
implantable medical devices was conducted. A general purpose switch for
electrical stimuli control in widely different situations was designed,
fabricated in XT06 HVCMOS technology and measured. Three different
versions of the circuit were compared (two of them very similar). The
designed switches presented low impedance (around 5Ω), high voltage
capability (up to 16V), high current (up to 30mA) capability, with almost
no static power consumption and leakage current below 1nA on each pin.
The switches performance was almost the same for power supply ranging
form 2V to 5V. For the three switches the measured characteristics
comply with minor deviations, the initial specifications presented in section
1.3.
First a study of basic HV-CMOS devices and composite current control
transistors, were presented (section 2).Then the complete switches
design, including composite pass transistors and driving circuitry was
presented in Section 3. Some novel HV circuit blocks were developed, like
full range Level Shifters and a self-protected gate driver for PMOS
transistors. In Section 4, an extensive set of measurements is presented,
allowing comparing the performance of the three circuits.
Switches comparison:
Regarding the on-Resistance, all the switches show a good measured
performance. Although the measured value exceeds the target 5Ω on
certain circumstances, the result is considered to be acceptable. High
current conduction capability is limited by the heat dissipation in the ASIC.
It should be pointed out that during testing, a switch was damaged due to
a short circuit. In a real medical device, the switches shall be protected
against an accidental short circuit between electrodes.
Regarding voltage stimuli, the three designed switches are capable of
delivering stimuli pulses form 100mV to 16V, for V
CC
ranging from 2V to
5V. No significant differences were detected between the switches.
Regarding response time, all the switches show a good measured on/off
time below 500ns.
Regarding the power consumption, all the switches show negligible static
consumption (Below 5nA). Dynamic power consumption of Switch A is
approximately proportional to frequency, indicating power consumption is
due to the repetitive charge-discharge of gate and parasitic capacitors. In
the case of switches B and C, power consumption has a fixed floor for
large V
Stimuli
values corresponding to the current through the protective
loop of section 3.1.5.
Integrated switches for implantable medical devices, in HV-CMOS
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In all three switches negligible leakage currents were measured.
Regarding crosstalk, Switches B and C present a much smaller crosstalk,
because the switches are close by connecting V
OUT
with the gate of
transistor M
2
(see Figure 3.18), instead of switch A that connects M
2
gate
to 0V (see Figure 3.15).
Regarding current stimuli and charge injection, the three designed
switches are capable of delivering stimuli pulses form 10µA to 30mA, for
V
CC
ranging from 2V to 5V. Significant current spikes and current
diminishments were detected when opening or closing the switches, due
to the charge injected (NHV transistors) or taken (PHV transistors) by the
main transistors switches, the injected charge is dependent of the stimuli
voltage. In some cases switch A is able to diminish the effect of charge
injection due to the high voltage transmission gate used as main switch.
Regarding area, switch A (3.8mm
2
) is almost two times larger than
switches B,C (2mm
2
), because of the use of the HV transmission gate
instead of two in series PHV transistors.
Regarding ESD, Switch B,C proved to be much more robust than Switch A.
The problem with switch A is the large nhv NMOS transistors in the
transmission gate configuration. As pointed in the manufacturer's ESD
design guidelines, HV-PMOS are much more robust than HV-NMOS. In
effect, phv turn-on characteristic in the case of an ESD event, is like in
Figure 7.2 on the left, while for nhvs is like in Figure 7.2 on the right. For
a large phv, turn on characteristic is homogeneous in the 40000µm/3µm
very wide transistor, thus ESD discharge can take place through the whole
transistor (becomes what is known as a self-protected device). But the
nhv deep snapback characteristic may cause a single transistor finger to
trigger before the rest of the wide nhv, thus all the ESD current goes
through a single finger (or transistor zone) causing a local transistor
damage.
Due to ESD weakness, Switch A is, in principle, discarded and Switches
B,C, are proposed as the better option. Switch A failed when performing
ESD tests of section 4.8. Of course a better ESD protection mechanism
can be designed with the cumulated ESD experience of the last designs in
XT06 of our group, but in any case phv are inherently more robust. Also
Switch A showed a much larger crosstalk effect than switches B, C
(section 4.6) and a larger circuit area. On the other hand only a smaller
charge injection can be observed in switch A under certain circumstances
(because nhv, phv charge injection effect can be compensated in the TG).
No significant differences were found between switches B and C.
Integrated switches for implantable medical devices, in HV-CMOS
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83
The proposed switch:
Thus an overall conclusion is that Switch B, C can be either selected for
the task. Switch A is momentarily put aside mainly because of ESD
strength.
The proposed switches fulfill with minor deviations, the specifications in
section 1.3.
In Table 5.1 the measured characteristics of the switches B (C) are
presented,
Table 5.1
Switches B and C mesured characteristics.
Characteristic
Min Typ Max
Impedance 3.5Ω -- 8Ω
Power supply
2V -- 5V
Static current
consumption -- -- Below 5nA
Leakage
currents -- -- Below 1nA
Voltage
stimuli 100mV -- 16V
Current
stimuli 100µA -- 30mA
Crosstalk -- 0.1nC --
ON/OFF time
-- -- Below 500nS
Symmetrical -- YES --
ESD
protected -- -- 6k
Area 2mm
2
The selected switches have 8 pins as shown in Figure 5.1, in pins names,
function and type (see ANNEX A) is presented.
V
SS
V
IN
V
OUT
C
ap
CTRL
V
High
GND
Switch
B or C
V
CC
Figure 5.1 Switch B and C block.
Integrated switches for implantable medical devices, in HV-CMOS
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84
Table 5.2 Switch B or C pins.
Name Function Type
CTRL
Open and
closes the
switch
IN
V
CC
Power supply
V
CC
GND Switch
ground GND
CAP Pump
capacitor OUT
V
SS
Negative
generated
voltage
V
SS
V
IN
Switch input HV
V
OUT
Switch
output HV
V
High
Voltage
reference to
close the
switch
HV
5.1 Future work
Some aspects were identified that can be improved in future versions of
the switches:
- A compensator to diminish the spikes detected in section 4.7 can be
incorporated and integrated into the switches if the necessary circuit area
(a large capacitor will be required) can be assigned.
- A current limiting circuit can be introduced to protect the switches in the
case of a short circuit between electrodes. Several techniques shall be
investigated: current limit will be complex in the full range of operation,
power limit via a temperature sensor in the die is easy to implement but
may not fully protect the device.
5.2 Publications
Three publications are associated to this thesis work:
1) A.Arnaud, J.Gak, M.Miguez, “An integrated switch in a HV-SOI wafer
technology, with a novel self-protection mechanism.” JICS accepted to be
published in 2010.
Integrated switches for implantable medical devices, in HV-CMOS
technology
85
2) A.Arnaud, J.Gak, M.Miguez ,"A self-protected integrated switch in a
HV technology", Proc. 22th Symposium on Integrated Circuits and
Systems Design - SBCCI 09 - Natal, Brazil - Sep.2009.
3)
A.Arnaud, J.Gak, M.Miguez ,"Integrated Switch for Implantable Medical
Devices", Proc.XV Workshop of iberchip - Buenos Aires, Argentina -
Mar.2009.
Integrated switches for implantable medical devices, in HV-CMOS
technology
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P. Gerrish, E. Herrmann, L. Tyler and K. Walsh, "Challenges and
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Annual International Conference New York City, USA, Aug 30-Sept 3,
2006.
[28]
Y. Moghe and T. Lehmann “A Novel Safety System Concept and
Implementation for Implantable Stimulators: A Universal DC Tissue
Leakage Current Detector”, ISCAS 2008, Seattle, USA.
[29]
R. Shannon, “A model of safe levels for electrical stimulation,”IEEE
Transactions on biomedical engineering, VOL. 39, NO. 4. APRIL 1992.
[30]
M. Khorasani, L. van den Berg, P. Marshall, M. Zargham, V. Gaudet,
D. Elliott and S. Marte “Low-Power Static and Dynamic High-Voltage
CMOS Level-Shifter Circuits”, ISCAS 2008, Seattle, USA.
Integrated switches for implantable medical devices, in HV-CMOS
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7 Annex A: ESD protection design
ESD is a crucial factor for integrated circuits and influences their quality
and reliability [8]. Custom PAD libraries including special HV protections,
were designed for all the inputs and outputs, of the designed circuits.
Custom PADS allowed an efficient die area allocation, as well as to verify
safety considerations even at ESD protection circuitry level. In this Annex
a brief introduction to ESD protection is presented, as well as the different
protection circuits that were included in the ASIC.
7.1 Human Body model
Several models are used for ESD events but the most used is the Human
Body model (HBM) and the ESD protections in this work were selected
according to it. The HBM ESD event describes the discharge procedure of
a charged human body directly into a device. The device is directly
contacted and the charges are transferred into the device [8], the ESD
test model uses the simplified equivalent circuit in Figure 7.1, were the
human body is modeled by a 100pF capacitor and 1500Ω series resistors.
R
Body
Charge Resi
s
tor
C
Body
HV Supply
DOT
Short
Figure 7.1 MIL-STD HBM circuit.
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7.2 ESD protection device types
Basically, ESD protection circuitry limits the voltage between internal
nodes in the ASIC and provides a discharge path in the HBM model, to
avoid large current peaks through devices in the ASIC that are not
prepared to do so. The ESD protecting follows some rules [8]:
• Sufficient discharging paths to bypass any ESD stress.
• Certain degree of ESD robustness and protect themselves against
ESD damages during an ESD discharge.
• Provide a high ESD protection capability with minimum layout area
• Remain inactive in the normal operating condition of the IC and to
pass normal I/O signals.
• Cause acceptable, as small as possible signal delays when added to
an I/O structure.
There are basically two kinds of ESD protection devices to realize the ESD
protection concept, turn-on characteristic or snap-back characteristic [8].
The turn-on characteristic ESD protection device is turned on at the
threshold point V
t1
, I
t1
in a certain triggering time and forms a low-
impedance discharge path to divert the ESD current, shown in Figure 7.2
left side. The turn-on voltage needs to be sufficiently low for voltage
clamping but ought to be greater than the operating voltage to avoid
accidental triggering under normal operation.
The snap-back characteristic of ESD protection device uses a snap-back
I-V characteristic as in Figure 7.2 right side. When the ESD protection
device is turned on at the triggering point the device is driven into the
snap-back region with a low holding voltage creating a low impedance
discharge path. The trigger voltage needs to be high enough above the
operating voltage. The low trigger voltage ensures proper voltage
clamping. Thus, a deep snap-back I-V curve is preferable for better ESD
protection. The trigger current at the trigger voltage has to be selected
with latch-up in consideration. The maximum ESD protection level of this
device is represented by the second breakdown point, V
T2
I
t2
.
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I
V
ESD protection
region
Breakdown voltage
I=1µA trun-on
V
t1
,I
t1
V
t2
,I
t2
Second breakdown
Device destroyed
I
V
Snap-back
region
Breakdown voltage
I=1µA
Snap-back
trigger voltage
V
t2
,I
t2
Second breakdown
Device destroyed
V
t1
,I
t1
Snap-back
Holding voltage V
h
Figure 7.2
Typical turn-on and snap-back characteristics if ESD protection
structure.
7.3 ESD protection strategy
ESD protection strategies can be implemented with a pad based
protection. Pad based ESD protection shown in Figure 7.3, relies on ESD
protection devices between the I/O pad and the ground rail. These devices
will be forward biased or break down during ESD stress to divert the
discharge current. Devices with snap back characteristic are preferred as
breakdown devices. Additional ESD protection devices between the I/O
pad and the supply rail are recommended but not required. The supply
and ground pads have also to be protected by snap-back devices. A
continuous ground rail is preferred [8].
Figure 7.3 Pad based ESD prtection.
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7.4 Low voltage I/O ESD protected pads
In Figure 7.4 the low voltage I/O ESD protected pad is shown. It consist in
a diode configuration PMOS (M
pd1
), diode configuration NESD (M
nd1
) (the
NESD transistor is a low voltage NMOS transistor with a special ESD
protection implant [9]) and poly resistor (R
S
, not present in output type
pads).
If a positive ESD event occurs discharge will be done through M
pd1
, if a
negative ESD event occurs discharge will be done through M
nd1
, R
S
limits
the input current to the integrated circuit.
M
nd1
M
pd1
V
cc
G
ND
R
S
PAD
To/From
circuit
Figure 7.4 Low voltage I/O pad.
Transistors and resistors layout and sizes were determined using [9], in
Table 7.1 a summary of transistors and resistors dimensions are shown.
Table 7.1 I/O pad dimensions.
Transistor W/L (µm/ µm) Number of gates
M
pd1
60/0.8 16
M
n1
68/1.1 20
Resistors Type Value
R
S
R
POLYH
1.5KΩ
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7.5 High voltage I/O ESD protected pads
XT06 allows stacking of low voltage ESD protection devices to achieve
higher break down voltages to use as a high voltage ESD protection
device [9]. In Figure 7.5 the high voltage I/O ESD protected pad is shown
consisting off 4 stacked diode configuration NESD (M
nd1-4
).
If a positive ESD event occurs discharge will be done through stacked
NESD deep NPN snap-back (the NPN is a parasitic bipolar transistors), if a
negative ESD event occurs discharge will be done through stacked diodes
configuration NESD.
M
nd1
G
ND
HV
PAD
M
nd2
M
nd3
M
nd4
Figure 7.5 High voltage I/O pad.
Transistors layout and sizes were determined using [9], in Table 7.2 a
summary of transistors sizes are shown.
Table 7.2 HV pad dimensions.
Transistor W/L (µm/ µm) Number of gates
M
nd1-4
68/1.1 6
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7.6 V
SS
ESD protected pad
In Figure 7.6 the V
SS
pad is shown. It consist in a diode configuration,
diode 2 stacked diode configuration NESD (M
nd1-2
).
If a negative ESD event occurs discharge will be done through stacked
NESD deep NPN snap-back (the NPN is a parasitic bipolar transistors), if a
positive ESD event occurs discharge will be done through stacked diodes
configuration NESD.
M
n1
M
n2
V
SS
PAD
GND
Figure 7.6 V
SS
pad.
Transistors layout and sizes were determined using [9], in Table 7.3 a
summary of transistors sizes are shown.
Table 7.3 V
SS
pad dimensions.
Transistor W/L (µm/ µm) Number of gates
M
n1,2
60/1.1 20
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7.7 V
CC
and GND ESD protected pads
In Figure 7.7 V
CC
(left) and GND (right) protected pads are shown. It
consist in a diode configuration PMOS (M
pd1
) for V
CC
and a diode
configuration NESD (M
nd1
) for GND (the NESD transistor is a low voltage
NMOS transistor with a special ESD protection implant [9]).
M
nd1
M
pd1
G
ND
V
CC
PAD
V
cc
GND
PAD
Figure 7.7 V
CC
(left) and GND pads (rigth).
Transistors layout and dimension were determined using [9], in Table 7.4
a summary of transistors sizes are shown.
Table 7.4 V
CC
and GND pad dimensions.
Transistor W/L (µm/ µm) Number of gates
M
pd1
60/0.8 16
M
nd1
68/1.1 20
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7.8 PAD list
In Table 7.5 the complete list of pad and pad type for each switch is
presented.
Table 7.5 Pads complete list.
Name Switch Type
CTRL A IN
V
CC
A V
CC
GND A GND
CAP A OUT
2V
CC
A HV
V
IN
A HV
V
OUT
A HV
V
High
A HV
CTRL B or C IN
V
CC
B or C V
CC
GND B or C GND
CAP B or C OUT
V
SS
B or C V
SS
V
IN
B or C HV
V
OUT
B or C HV
V
High
B or C HV
