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A novel capillary-effect-based solder pump structure and its potential application for through-wafer interconnection
Abstract
Through-wafer electrical interconnection is a critical technology for advanced packaging. In this paper, a novel capillary-effect-based solder pump has been proposed and analyzed, which could produce interconnects through and between silicon dies. The principle of this pump is to use the surface tension of a molten solder, introduced in the form of balls, to drive sufficient material into a deep reactive-ion etched hole to form a through-wafer conductive path. The solder pump structure uses unwettable through-wafer holes of different diameters together with wettable metallization on two dies to provide the pressure differential and flow path. Using multiple feed holes and a single via hole complete through-wafer interconnects are demonstrated.
... Several studies have focused on liquid metal via-filling. Our previous work of a solder ball based 'solder-pump' method utilize surface tension only to drive liquid solder for via-filling, which however can only pump liquid solder from small holes to larger holes [2,3,4]. Furthermore, electrostatic force make it a troublesome work to handle solder balls less than 200μm. ...
... The geometry of the nozzles and the minimum via holes fillable can be derived from ∆ can be get by the equation [2]: ...
... All the via and nozzle wafers are finally coated with 2 micron SiO2 film by thermal oxidation. The wafer alignment is assisted by a pin-dowel approach [2]. A specific reflow oven is made to accomplish the experiment as shown in Figure 7. ...
Via-filling is a critical and costly process of TSV fabrication and is usually realized by Cu-plating, CVD, etc. Liquid metal via-filling made by pressing solder from a melting solder pool into via holes faces problems of wafer breakage caused by pressure differential and cutting off solder-vias from the pool. A liquid bridge pinch-off effect based cutting-off method, together with a 'wafer sandwich' structure, has the feasibility to solve the above problems faced by the pressure assisted liquid metal via-filling approach.
... The conductive core of the TSVs is most commonly fabricated by electrodeposition of copper [107,104,108,105,109,110], chemical vapor deposition (CVD) of tungsten [102,111], or CVD of polysilicon [102,112]. Other approaches include the use of low-resistivity bulk silicon [113], conductive metal pastes [101,114,115], solder [116,117], as well as wire-bonded metal cores [118,119,106]. The insulation layer between the conductive core and the substrate can also be manufactures with different materials, the most common amongst which are CVD silicon oxide and silicon nitride. ...
... (SAC305) solder can be filled into vias by applying solder, either with solder paste coating, or a dip into a molten solder bath, and subsequently applying vacuum to the wafer backside to suck the solder up into the vias [137]. A capillary-effect-based solder pump method has been developed, in which solder balls are filled into throughholes, and after reflow, a solder column is formed as the TSV conductor [138]. Conductive polymers such as Dupont CB100 have also been used as TSV conductors, being filled into through-holes with a screen printing machine [139]. ...
After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore’s Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D hetero-integration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the hetero-integration of the MEMS and CMOS technologies. [2015-0158]
... Conventionally, [43]). Alternatively, they are stacked on top of each other [43,44] using through-substrate-vias (TSV) [45,46,47,48] for vertical electrical interconnection. The main technical advantage is the uncomplicated integration of different technologies, materials or devices. ...
... In particular, high aspect ratio TSVs with void-free conductive metal cores are difficult to implement [7]. Alternative approaches to plating processes have therefore been investigated, such as filling with conductive metal pastes [1,20,21], solder [22,23] as well as the use of wirebonded gold [9]. ...
Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or MEMS-based transducers using through silicon vias (TSVs). TSVs enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In this paper we demonstrate a new manufacturing technology for high-aspect ratio (>;8) through silicon metal vias using magnetic self-assembly of gold-coated nickel rods inside etched through-silicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in TSV fabrication using conventional approaches, such as the metal deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio state-of-the-art TSVs for e.g. interposer, MEMS and RF applications.
... In particular, it is challenging to implement high aspect ratio TSVs with void-free conductive metal cores [4,9,32]. Alternative approaches to plating processes have therefore been investigated, such as the via filling with conductive metal pastes [1,33,34], solder [35,36] as well as the use of wirebonded metal cores [37,38,15]. As shown in table 2, the electrical resistivity of ferromagnetic nickel is similar to tungsten, but approximately three to four times higher as compared to gold and copper. ...
Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.
... In particular, high aspect ratio TSVs with voidfree conductive metal cores are difficult to implement [9]. Alternative approaches to plating processes have therefore been investigated, such as filling with conductive metal pastes [1] as well as the use of solder balls [15] and the assembly of pre-fabricated wires [17]. ...
Three-dimensional integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies with through-silicon vias (TSVs). They enable the realization of circuits with shorter signal path lengths, smaller packages and lower parasitic capacitances, which results in higher performance and lower costs. This paper presents a novel technique for fabricating TSVs from bonded gold wires. The wires are embedded in a polymer, which acts both as an electrical insulator, resulting in low capacitive coupling toward the substrate and as a buffer for thermo-mechanical stress.
A through‐substrate via (TSV) is an electrical interconnect, which passes vertically through a substrate to conduct the electrical signals from one side of the substrate to the other. As an enabling technology, TSVs allow micro electro mechanical system (MEMS) devices and systems to achieve new integration schemes and wafer‐level vacuum packaging with high performance, multifunctions, low costs, high reliability, and small package sizes. Typically a TSV consists of a through‐hole etched in a substrate, a conductor in the through‐hole, and an insulator isolating the conductor from the substrate. Although TSVs facilitate MEMS and complementary metal oxide semiconductor integration, process compatibility is a concern in MEMS applications. The methods for TSV fabrication highly depends on the TSV configurations and the materials. Polysilicon TSVs have minimized thermal stresses, good process compatibility, and low fabrication costs. Metal TSVs have more significant diversities than other TSVs in metal materials, TSV configurations, and fabrication methods.
In this paper, we present an alloy via-filling method that does not need pre-metallization of via holes and can be realized on wafer level. Through-Silicon Via(TSV)/Through Glass Via(TGV) with different geometries can be filled simultaneously in few minutes, instead of few hours by electroplating. A specific equipment is made for the alloy via-filling method. The alloy TSV filling method presented in this paper has the potential for industrial applications.
Through-silicon via (TSV) is increasing its importance in advanced device packaging. In this paper, a through-silicon/substrate via filling method based on the combinative effect of liquid bridge rupture and capillary action is proposed and demonstrated. The proposed method is able to achieve alloy vias from the surface of a molten alloy pool. Two different processes were tested in experiments and the results show that one of these processes is able to achieve fully filled vias. In addition, a piece of equipment was specially made for the proposed via filling method. The via filling method studied in this paper has a potential application for TSVs in MEMS packaging.
We present a solder pump method that injects conductive material into a device wafer to form low-resistance through-silicon vias (TSVs). Building on previous work that exploits the Gibbs-Thomson effect, this pump geometry uses a reusable wafer set to produce a pattern of U-shaped reservoirs into which solder balls are loaded. After introduction of the device wafer with a corresponding pattern of through-wafer-etched holes, reflow results in the complete transfer of the solder from the reser- voirs into the device structure to produce the vias. This approach forms the basis of a rapid low-cost batch-fabrication process for TSVs. (2010-0335) Index Terms—Microelectromechanical devices, semiconductor device packaging, through-silicon via (TSV).
Through wafer interconnection is a critical technology for advanced packaging. Previously, we have proposed a solder pump technology which could complete the via filling through solder reflow. Here, an improved vertical solder-pump structure is presented and successfully demonstrated. This technology allows producing an arbitrary array of highly conductive vias in seconds.
The surface tension and density of the liquid Sn60Pb40, Sn90Pb10, Sn96.5Ag3.5 and Sn97Cu3 solder alloys (wt%) have been determined experimentally over a wide temperature interval. It is established that the surface tension of liquid Sn90Pb10 is about 7% higher than that of a traditional Sn60Pb40 solder and that the surface tension of Sn96.5Ag3.5 and Sn97Cu3 alloys is about 12% higher than that of Sn60Pb40. The analytical expressions for the temperature dependences of the surface tension and density are given.
Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on-insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.
This paper presents wafer-level packaging (WLP) solution for RF-MEMS applications based on through-wafer via (TWV) technology in high-resistivity silicon (HRS). A pre-processed HRS capping wafer containing recesses and vertical Cu-plated TWV interconnect is, after alignment, bonded to the RF-MEMS wafer providing environmental protection and easy signal access. Optionally, cavities can be formed simultaneously with TWV in the capping wafer, which allows hybrid co-integration of additional IC dies while maintaining overall thickness of the resulting SMT compatible package. This cavity can also be used for a first-level wafer-to-wafer alignment accuracy check. After bonding, the s-parameter measurement at giga hertz level shows little influence introduced by the capping substrate.
This paper presents a novel technology for copper electroplating in high aspect ratio silicon vias. The described approach is based on the bottom-up technology with the use of a new specifically designed electroplating holder for local sealing and filling of the vias. The technological steps are described and demonstrated for 20mum wide vias with an aspect ratio of 15. Moreover, a simplified simulation model is presented in order to explain the local sealing phenomenon and the subsequent electroplating.
Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results.
In this paper, we present the detailed fabrication process, high-frequency characterization, and modeling of through-wafer copper-filled vias ranging from 50- to 70- $mu$ m-in diameter on 400- $mu$ m-thick silicon substrates. The high aspect ratio via-holes were fabricated by carefully optimizing the inductively coupled plasma deep reactive ion etching process. The high aspect ratio via-holes are completely filled with copper using a bottom-up electroplating approach. The fabricated vias were characterized using different resonating structures based on which the inductance and resistance of the filled via-holes are extracted. For a single 70- $mu$ m via, the inductance and resistance are measured to be 254 pH and 0.1 $Omega$ , respectively. In addition, the effect of the physical arrangement and distribution in multiple-via configurations on the resulting inductance is also evaluated with double straightly aligned quadruple and diagonally aligned quadruple vias. Physical mechanisms of the dependence was depicted by electromagnetic simulation. An equivalent-circuit model is proposed and model parameters are extracted to provide good agreement.
The use of lead-free solders requires new fundamental information for flow soldering. Parameters, approved for many years with the solder SnPb, for wave height, flow speed and also the tear-off angle must be defined again for lead-free solders. In addition, the corrosion of substrate metallization and especially of machines (crucible and other parts in liquid solder) is under discussion for lead-free soldering today. A new combined measurement method for analyzing the characteristics of new solder in a relatively short time was developed at IZM. Therefore, the surface energy as a value for tear-off behavior, the viscosity as a value for the flow behavior and also the corrosion rate were measured. A comparison between different solders or solder alloys provides the solder manufacturers as well as the solder machine manufacturer with important data for the application and further development of new technologies
This paper presents an ultra-low resistance, high wiring density, through-wafer via (TWV) technology that is compatible with standard silicon wafer processing. Vias as small as 30 µm by 30 µm are fabricated through a 525 µm thick wafer. This results in an aspect ratio for the via that is greater than 17:1. Furthermore, the dc resistance of a single via is less than 50 mOmega. Key fabrication steps, including the silicon dry etch, copper metallization, and photoresist electroplating, are described in detail. As a demonstration of the potential applications of the TWV technology, a novel three dimensional inductor is designed and fabricated. For a 0.9-nH inductor, a quality factor of 18.5 is measured at 800 MHz.
In this paper, we present detailed fabrication process and high-frequency characterization of through-wafer copper-filled via holes ranging from 40 μm to 70 μm in diameter on 400 μm-thick silicon substrates. The high aspect ratio via holes are achieved by carefully tuning the inductively coupled plasma (ICP) etching process and the high aspect ratio via holes are filled completely using a bottom-up electroplating approach. The fabricated via holes were characterized using different resonating structures and the measured inductance and resistance of the 70 μm via are 409 pH and 0.154Ω respectively. In addition, the effect of the via arrangement on the resulting inductance are also evaluated.
This study presents a novel system architecture to implement SOG (Silicon-on-Glass) MEMS devices on Si-glass compound substrate with embedded silicon vias. The silicon vias connecting to the pads of device are embedded inside the Pyrex glass. Parasitic capacitance for both vias and microstructures is decreased and mismatch of coefficient of thermal expansion (CTE) is reduced. In applications, the glass reflow process together with the SOG micromachining processes were employed to implement the presented concept. Successfully driving of resonator through the silicon vias is demonstrated. The wafer-level hermetic packaging can be further achieved by anodic bonding of a Pyrex7740 wafer. Hermeticity of the packaging device which performed by helium leak test satisfied the MIL-STD-883E. The packaged SOG device is SMT (Surface Mount Technology) compatible and ready for 3D microsystem integration.
The Through Silicon Via (TSV) process developed by Silex offers sub 50 mum pitch for through wafer connections in up to 600 mum thick substrates. The via process enables MEMS designs with significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. With several companies using the process already today and a line-up of potential users, the process is becoming a standard in the MEMS industry. This paper gives a brief introduction to the via formation process and focuses in more detail on the novel solutions made available by this enabling technology.
A pressing challenge to the commercial implementation of prototype
microsystems is the reduction of package size and cost. To decrease
package size, a process was developed for the fabrication of
high-aspect-ratio, through-wafer interconnect structures. These
interconnects permit device-scale packaging of microsystems and are
compatible with modern surface mount technology such as flip chip
assembly. To minimize package cost, a modular wafer-level silicon
packaging architecture was devised. Low temperature bonding methods were
used to join package components, permitting integration of driving
circuitry on the microsystem die. The reconfigurable architecture allows
standard package components to serve a wide variety of
applications
A novel micro-electromechanical system (MEMS) package has been developed based on modular, reconfigurable components such as substrate, cap, bond region and through-wafer electrical interconnect (TWEI). The paper presents the details of the process for the fabrication of high density, high aspect ratio TWEIs that includes deep dry etching holes through the substrate, depositing an insulation layer and depositing a conductive layer. Two different processes to make the TWEI have been developed: Post-Process where the TWEI is fabricated after the fabrication of MEMS devices and Pre-Process where the TWEI is fabricated before the fabrication of MEMS device. For both processes, the interconnect holes are created by an anisotropic etching process-inductively coupled plasma (ICP) etching. For the post-process, a silicon dioxide layer was deposited in a plasma enhanced chemical vapor deposition (PECVD) chamber to insulate the interconnect holes. For the pre-process, the PECVD process was replaced with a thermal oxide growth step to ensure a more conformal oxide coating. Three different ways to deposit a conductive layer after deposition of an insulation layer have been practiced: sputtering Cu, electroplating Cu and low-pressure chemical vapor deposition (LPCVD) of phosphorus doped polysilicon. The electrical performance of the TWEIs achieved in each way was measured, analyzed and discussed.
In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight. The inductance of vias with nominal aspect ratios between three and 30 approach the theoretically expected values. This interconnect technology was exploited in a novel Faraday cage structure for substrate crosstalk suppression in system-on-chip applications. The isolation structure consists of a ring of grounded vias that surrounds sensitive or noisy portions of a chip. This Faraday cage structure has shown noise suppression of 30 dB at 10 GHz and 16 dB at 50 GHz at a distance of 100 μm when compared to the reference structure.
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A through-wafer interconnects in silicon for rfics Electron. Devices IEEE Trans
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pp 974-7