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74 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007
VLSI Design of High-Throughput
SISO-OFDM and MIMO-OFDM Baseband
Transceivers for Wireless LAN Networks
Shingo Yoshizawa 1,Yoshikazu Miyanaga2,Nobuo Hataoka 3,Baiko Sai 4,
Norihisa Takayama 5,Masaki Hirata 6,
Hiroshi Ochi7,and Yoshio Itoh 8, Non-members
ABSTRACT
This paper describes a VLSI design of high-
throughput OFDM transceivers targeted to future
wireless LAN systems. The optimum parameters
composing a new packet OFDM frame are discussed
by expanding the IEEE802.11a standard. The pro-
posed system provides a maximum transfer rate of
600 Mbps by use of an 80-MHz occupied band-
width and a MIMO technique. The SISO-OFDM
and MIMO-OFDM transceivers have been designed
according to the proposed OFDM format. A low-
latency and full-pipelined architecture enables a real-
time processing of OFDM modulation/demodulation
and MIMO detection. In the MIMO detection,
the circuit structures of zero-forcing and MMSE-
V-BLAST algorithm in a 2 ×2 MIMO configura-
tion are presented. The SISO-OFDM and MIMO-
OFDM transceivers have been implemented to a 90-
nm CMOS technology. It performed small implemen-
tation logic size and low power consumption after
a real LSI evaluation. The circuit behavior of the
OFDM transceivers has been verified by using the
FPGA prototyping platform that executes both dig-
ital and analog OFDM baseband transmissions.
Keywords: Wireless, OFDM, MIMO, VLSI Design,
Digital Circuit
Manuscript received on January 30, 2007 ; revised on May 7,
2007.
1,2The authors are with Graduate School of Informa-
tion and Science Technology, Hokkaido University, Sapporo
060-0814, Japan, Emails: yosizawa@csm.ist.hokudai.ac.jp and
miya@ist.hokudai.ac.jp
3The author is with the Central Res. Lab., Hitachi Ltd.,
Tokyo 185-8601/Tohoku Institute of Tech., Sendai 982-8577,
Japan, Email: hataoka@tohtech.ac.jp
4The author is with the LSI Product Development Head-
quarters, Rohm Co.Ltd., Kouhoku-ku, Yokohama 222-8575,
Japan, Email: Baiko.Sai@dsn.rohm.co.jp
5The author is with the SANYO Semiconductor Co.,Ltd.,
Oizumi-machi, Ora-gun, Gunma 370-0596, Japan, Email:
Norihisa.Takayama@sanyo.co.jp
6The author is with the SANYO Semiconductor Co.,Ltd.,
Oizumi-machi, Ora-gun, Gunma 370-0596, Japan, Email:
ma.hirata@necel.com
7The author is with the Dept. of CSE, Kyushu Inst.
of Tech., Kawazu, Iizuka, Fukuoka 820-8502, Japan, Email:
ochi@cse.kyutech.ac.jp
8The author is with the Dept. of Electrical Electronic Eng.,
1. INTRODUCTION
Wireless technologies, such as digital broad cast-
ing, wireless LAN, and wireless PAN, have enabled
high-speed data transmission in home and personal
networks. The IEEE802.11a standard supports a
maximum of 54 Mbps at a 20-MHz frequency band
by using orthogonal frequency division multiplexing
(OFDM) [1]. For the standardization of next genera-
tion wireless LAN networks proceeded by IEEE802.11
Task Group n (TGn), the Enhanced Wireless Consor-
tium (EWC) group sets a goal to achieve data rates
of more than a few hundred using a multiple-input
and multiple-out (MIMO) technique [2].
The EWC proposal indicates four main modifi-
cations from the IEEE802.11a standard to achieve
a 600-Mbps data rate, i.e., the adoption of a 40-
MHz occupied bandwidth, a 400-ns short guard in-
terval, a 5/6 coding rate and a 4 ×4 MIMO con-
figuration. On the other hand, our research project
supported by STARC1has developed a comparable
wireless OFDM system where this project mainly has
focused on establishing high-speed wireless data links
between information home appliances, e.g., digital
data transmission of advanced high-definition digital
video graphics. The proposed system achieves the
same maximum data rate of 600 Mbps by use of an
80-MHz occupied bandwidth and a 2x2 MIMO con-
figuration. The proposed system occupies the double
signal bandwidth of the EWC proposal in frequency
utilization. However, the EWC proposal has the
following technical difficulties to transmit the above
600-Mbps data: First, it was difficult to build up a
hardware that performs real time frequency-domain
MIMO channel estimation and coding because of the
large hardware complexity and high power consump-
tion. Second, the use of a 5/6 coding rate is not
sufficient for error correcting in a Viterbi decoder.
Low density parity check code (LDPC) and turbo de-
coders improve transmission performance as alterna-
tive decoding schemes, however increase complexity
and must deal with their increased power.
Tottori University, Koyama-minami, Tottori 680-8522, Japan,
Email: itoh@ele.tottori-u.ac.jp
1Abbreviation of Semiconductor Technology Academic Re-
search Center in Japan.
VLSI Design of High-Throughput SISO-OFDM and MIMO-OFDM Baseband Transceivers for Wireless LAN Networks 75
Table 1: Principal parameters in a packet OFDM
system.
KDFT size
FbBandwidth (Hz)
FnGuard carrier bandwidth (Hz)
TgGuard interval (s)
NsNumber of data subcarriers
NbCoded bits per subcarrier
RCoding rate
20 3 0 40 50 6 0 70 80
0
50
10 0
15 0
20 0
25 0
30 0
35 0
K=6 4
K=1 28
K=2 56
K=5 12
K=1 02 4
K=2 04 8
Bandwidth (MHz)
Data rate (Mbps)
DFT size
Fig.1: Data rate estimate by a function of a DFT
size and a bandwidth.
This paper describes the total VLSI design of
the proposed OFDM system, i.e., SISO-OFDM and
MIMO-OFDM transceivers. Their results indicate
that our proposed system can provide realistic in-
stances in transmission performance and implement-
ing hardware.
A new OFDM frame format in the proposed sys-
tem is discussed in Section II. Section III reports
the simulation results in transmission performance
comparing the EWC proposal with the proposed sys-
tem. Section IV and V indicate a low-latency and
full-pipelined architecture in order to enable real-
time operations of OFDM demodulation/modulation
and MIMO detection, respectively. The MIMO de-
tection circuits based on zero-forcing and MMSE-
V-BLAST techniques are described. Section VI re-
ports the VLSI implementation results of the de-
signed transceivers in a 90-nm CMOS process, where
circuit size and power dissipation are evaluated. Sec-
tion VII introduces the FPGA prototyping platform
that performs both digital and analog OFDM base-
band transmissions to verify circuit behaviors of the
OFDM transceivers. Section VIII summarizes the key
points and mentions a future work.
2. PROPOSED OFDM SYSTEM
The optimum parameters composing a new OFDM
frame format are discussed in this paper. In order
to realize a 600-Mbps data rate system, we first con-
sider the OFDM parameters of a SISO-OFDM system
Table 2: Frame format in the proposed OFDM sys-
tem.
Sampling period 12.5 ns
Number of FFT/IFFT points 512
Number of data subcarriers 480
Number of pilot subcarriers 20
PLCP duration (short & long preambles) 16 µs
Symbol duration 7.2 µs
FFT/IFFT window duration 6.4 µs
Guard interval duration 0.8 µs
Subcarrier frequency spacing 0.1563 MHz
Table 3: Transmission modes and data rates of the
STARC-SISO and the STARC-MIMO.
Mode Modulation Coding SISO 2 ×2 MIMO
Rate (Mbps) (Mbps)
1 QPSK 1/2 67 133
2 16-QAM 1/2 133 266
3 64-QAM 1/2 200 400
4 64-QAM 3/4 300 600
with a 300-Mbps data rate. The 2 ×2 MIMO-OFDM
system processes two data streams and doubles the
above date rate. For the SISO-OFDM system, we
presented the data rate estimate for variable OFDM
parameters by expanding the IEEE802.11a standard
in [3]. The final representation is given by
D(K, Fb, Fn, Tg, Nb, R) =
K³1−Fn
Fb´·Nb·R·Fb
K+Fb·Tg
.(1)
Table 1 enumerates the parameters in the above
equation. For the four parameters of Fn,Tg,Nb, and
R, we adopt the same values used in the IEEE802.11a
standard: The guard carrier bandwidth Fnis 4 ×106
(Hz). The guard interval Tgis 8 ×10−7(s). The
coded bits per subcarrier is Nb= 6 (bits). The cod-
ing rate is R= 3/4. By substituting for above pa-
rameters, the estimate equation is transformed into
a function given by a DFT size and a signal band-
width. Figure 1 shows the estimates of data rates
for variable DFT points and signal bandwidths. A
64-point DFT reaches around 60 Mbps in a 20-MHz
bandwidth. However, the 64-point DFT is not suffi-
cient in increasing the data rate for an 80-MHz band-
width. A 512-point DFT achieves 300 Mbps in an
80-MHz bandwidth. Therefore, the proposed OFDM
system employs the 512-point FFT/IFFT used for
OFDM modulation/demodulation. Table 2 shows
the proposed OFDM frame format. The subcar-
rier frequency spacing is about a half of that in the
IEEE802.11a standard. The principal transmission
modes and their data rates are depicted in Table 3,
where the “STARC-SISO” and the “STARC-MIMO”
modulate/demodulate one and two data streams, re-
spectively.
76 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007
Table 4: Simulation parameters of the EWC pro-
posal and the STARC-MIMO.
1000 bytesPacket Size
2160
Data Bits per
Symbol (DBPS)
800 ns400 nsGI Length
4
Number of the
OFDM symbols
512128FFT/IFFT Size
64-State Viterbi Algorithm Decoding
Convolutional CodingCoding
80 MHz40 MHzBandwidth
Maximum Data
Rate
Coding Rate
MIMO Detection
Antenna Structure
(Tx, Rx)
600 Mbps
3/45/6
Zero-
Forcing
MMSE-V-
BLAST
MMSE-V-
BLAST
2, 22, 24, 4
STARC-MIMO
EWC
Proposal
Table 5: Channel Environments.
Modulation 64-QAM
Channel model 18-path Rayleigh fading
Doppler frequency 20 Hz
Delay profile TGn Channel D
RMS delay spread 50 ns
3. TRANSMISSION PERFORMANCE
BER performance is compared the proposed sys-
tem with the EWC proposal by baseband simulation.
The simulation parameters in the 600-Mbps transmis-
sion modes listed in Table 4. The EWC proposal uses
a 128-point FFT and a 5/6 coding rate. The proposed
system is evaluated by taking the 2×2 MIMO-OFDM
systems based on zero-forcing (ZF) and MMSE-V-
BLAST detection techniques. Data bits per sym-
bol (DBPS), the number of OFDM symbols, and a
packet size is the same between the EWC proposal
and the STARC-MIMO. The conditions of multipath
fading environments are listed in Table 5. The multi-
path delay profile is based on the TGn Channel D [4].
Figure 2 shows the simulation results of BER perfor-
mance. The 2×2 STARC-MIMO systems outperform
the EWC proposal by 6 to 7 dB and more than 10 dB
in SNR for BER=10−2and BER=10−3, respectively.
The use of a 5/6 coding rate is considered to be insuf-
ficient to remove bit errors by Viterbi decoding under
multipath fading channels, as is observed from these
results.
4. TRANSCEIVER ARCHITECTURE
Since the number of data subcarriers is ten times
large as that of IEEE802.11a standard, a new VLSI
architecture is to be discussed to deal with such an
10
-4
10
-3
10
-2
10
-1
10
0
15 20 25 30 35 40 45 50
4x4 MIMO-OFDM IEEE802.11n (BLAST-MMSE)
2x2 STARC-MIMO (V-BLAST-MMSE)
2x2 STARC-MIMO (Zero-Forcing)
SNR (dB)
BER
Fig.2: BER performance in the EWC proposal and
the STARC-MIMO systems.
(A) Encoding
& Mapping
(C) FFT/IFFT
& Channel
Equalization
(B) Frame
Synchronization
(D) GI/PLCP
Generation
(G) Soft-Out
Demapping
(H) Viterbi
Decoding
(F) Post-FFT SRAM(E) Pre-FFT SRAM
Transmitter
Receiver
(A) Encoding
& Mapping
(C) FFT/IFFT
& Channel
Equalization
(B) Frame
Synchronization
(D) GI/PLCP
Generation
(G) Soft-Out
Demapping
(H) Viterbi
Decoding
(F) Post-FFT SRAM(E) Pre-FFT SRAM
Transmitter
Receiver
Fig.3: Block diagram in the SISO-OFDM
transceiver.
(C) FFT/IFFT
(G) MIMO
Detection
(F) Post-
Transform
Memory
(E) Pre-
Transform
Memory
Transmitter
Receiver
(A)
Encoding
& Mapping
(B) Timing
Synchronization
(D) GI/PLCP
Insertion
(H) De-
Mapping (I) Viterbi
Decoding
(C) FFT/IFFT
(G) MIMO
Detection
(F) Post-
Transform
Memory
(E) Pre-
Transform
Memory
Transmitter
Receiver
(A)
Encoding
& Mapping
(B) Timing
Synchronization
(D) GI/PLCP
Insertion
(H) De-
Mapping (I) Viterbi
Decoding
Fig.4: Block diagram in the 2×2MIMO-OFDM
transceiver.
increased complexity. The proposed system has a
sampling rate of 80 Msps. A recursion procedure is
not suitable for a real-time processing because a high
clock rate makes it difficult to design an application
specific circuit and consumes large power. We apply
a full-pipelined architecture which processes one data
per cycle at the minimum frequency of 80 MHz.
Figure 3 shows a overall block diagram in the
SISO-OFDM transceiver consisting of processing
blocks (A) to (H). The two SRAM blocks adjusts data
communication timing between adjoined processing
blocks. For instance, while the block (A) sends
mapped data to the neighbor SRAM block (E), the
FFT/IFFT block (C) reads out mapped data in the
previous symbol. As long as the blocks of (A) and (C)
finish their own processing within symbol duration,
VLSI Design of High-Throughput SISO-OFDM and MIMO-OFDM Baseband Transceivers for Wireless LAN Networks 77
T12 T22 D12 D22 DK2
S
from
FFT
21,TT
H
G
1−
=
Η
G
D
y
Channel
Estimation
Inverse
Matrix Memory
MIMO
Detection
Latency
Short Preamble Long Training
Symbols Data Symbols
T11 T21 D11 D21 DK1
MIMO Detection
Channel
Estimation and
Pre-processing
Fig.5: OFDM frame structure, block diagram and
processing timing chart in the MIMO detection block.
Table 6: MIMO detection complexity in the EWC
proposal and the STARC-MIMO.
22
Zero-Forcing2, 2
MMSE-V-BLAST
MMSE-V-BLAST
Algorithm
43
4, 4EWC Proposal
23
2, 2
STARC-MIMO
Complexity
Antenna
(Tx, Rx)
no data collision occurs between these blocks. The
start timing in each block is given by the start point
of FFT/IFFT period and determined by the frame
synchronization block (B). In the FFT/IFFT block,
a pipeline FFT using a hybrid Radix-2 and Radix-22
Single-path Delay Feedback (R2SDF and R22SDF)
architecture [5] is implemented to the system. The
Viterbi block decodes parallel data sequences by 3
bits per clock. The three Viterbi decoders perform
their decoding for supporting the maximum data rate
of 64-QAM demodulation, where they were designed
in the previous research [6]. The 2×2 MIMO-OFDM
transceiver is shown in Fig. 4. The processing blocks
from (A) to (I) are duplicated except the time syn-
chronization block and the MIMO detection block.
5. MIMO DETECTION
5. 1 Required timing constraint
The OFDM frame structure, the block diagram,
and the processing timing chart in the MIMO de-
tection block are illustrated in Fig. 5. The MIMO
frame consists of the short symbol, the long training
symbols, and the data symbols. The long training
symbols Tij with the i-th symbol index and the j-th
stream are used for the estimation of a MIMO channel
matrix. The channel matrix His obtained from an
orthogonal training where this equation is described
11
T12
T
21
T
22
T
11
H
12
H
21
H
22
H
21122211 HHHH
−
=
δ
11
H
22
H
*
δδ
*
1
δδ
11
G
12
G
21
G
22
G
*
δ
12
H
−
21
H
−
*
*
δ
HH ′
=
′′
H
′
*
1
*
δδ
HG ′′
=
Channel Estimation
(1 stage)
Inverse Matrix Calculation
(7 stages)
Fig.6: Circuit structure in the ZF algorithm.
Channel Estimation
and Pre-processing
(10 stages)
MIMO Detection
(6 stages)
1
T2
T
H
1
Ga2
G
b2
G
ka
Wb
W
D
a
yb
y
a
ˆ
αb
ˆ
α
a
r
′
b
r
′
a
y
ˆb
y
ˆ
y
Fig.7: Modified processing procedure in MMSE-V-
BLAST algorithm.
as:
H11 = (T11 −T21)/2 (2)
H12 = (T11 +T21)/2 (3)
H21 = (T12 −T22)/2 (4)
H22 = (T12 +T22)/2.(5)
The MIMO detection block performs the channel es-
timation and the inverse matrix calculation given by
G=H−1(called as “pre-processing”) at receiving the
long training symbols. At receiving the data symbols
of D, the MIMO block decodes the transmitted data
by y=GD. If the MIMO decoding is immediately ap-
plied to the first data symbol, the channel estimation
and the MIMO detection should be completed before
receiving the first data symbol. Hence, the permit-
ted latency duration is within the guard interval (see
“Latency” in Fig. 5).
The challenging work is to realize a real-time
MIMO detection which performs a large complex-
ity of inverse matrix calculation so that the MIMO
channels for all the sub-carriers can be calculated
78 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007
on time. Table 6 shows the MIMO detection com-
plexity per subcarrier in the EWC proposal and the
STARC-MIMO, where QR decomposition algorithm
is utilized for calculating an inverse matrix. We have
developed the 2x2 MIMO-OFDM detection blocks in
zero-forcing and MMSE-V-BLAST techniques. As
well as the other processing blocks, a full-pipeline
architecture is introduced. The designed circuits
tend to increase circuit area; however they satisfy
the above timing constraint and indicate practical in-
stances in developing hardware.
5. 2 Zero-forcing
The zero-forcing (ZF) algorithm is simply achieved
by computing an inverse matrix G. The inverse for-
mula is given by
µg11 g12
g21 g22¶=1
h11h22 −h12 h21 µh22 −h12
−h21 h11 ¶,(6)
where hij and gij are factors of the channel matrix
Hand the inverse matrix G, respectively. The QR
decomposition is generally utilized in the inverse ma-
trix calculation in order to reduce a complexity. How-
ever, the complexity is not large as for a 2x2 MIMO
configuration. Figure 6 shows the circuit structure
of the ZF algorithm. This circuit operates a 8-stage
pipeline including a complex divide operation. The
total latency is 11 cycles including memory access. It
can satisfy the above timing constraint for the guard
interval of 64 cycles (12.5-ns clock period ×64 cy-
cles = 800 ns). The numbers of real and complex
multipliers are 8 and 11, respectively.
5. 3 MMSE-V-BLAST
The original V-BLAST is expressed as a recursive
procedure [7]. In our architecture, the procedure is
modified to introduce pipeline and concurrent pro-
cessing. In the 2x2 MIMO, the modified procedure is
described as follows:
G1=H+(7)
G2a= (H)2
+(8)
G2b= (H)1
+(9)
wa= (G1)1(10)
wb= (G1)2(11)
¯ya=waTr(12)
¯yb=wbTr(13)
ˆαa=Q[¯ya] (14)
ˆαb=Q[¯yb] (15)
´
ra=r−ˆαa(H)1(16)
´
rb=r−ˆαb(H)2(17)
ˆya=G2a´
ra(18)
ˆyb=G2b´
rb(19)
k= arg min
jk(G1)jk2(20)
Table 7: Circuit performance of the SISO-OFDM
Transceiver.
2326811
804624
3315
285576
285576
13854
838144
80573
10143
5006
Circuit Area
(μm2)
775603
268208
1105
95192
95192
4618
279381
26858
3381
1668
No. Logic
Gates
0.110.11System Control
35.883.81Viterbi Decoder
100.5864.48Total
0.180.01Soft Demapper
9.369.12SRAMs for Post-FFT
9.6410.06SRAMs for Pre-FFT
0.130.34GI・PLCP Signals
39.9239.30FFT/IFFT & Equalizer
5.261.44Timing Synchronization
0.100.29Coder & Mapping
Power
RX (mW)
Power
TX (mW)
Table 8: Circuit performance of the zero-forcing
MIMO-OFDM Transceiver.
26.385.053715371114612MIMO Detection
4256008
1600206
6480
573584
573584
50928
1166008
81967
20286
118353
Circuit Area
(μm2)
1418669
533402
2160
191195
191195
16976
388669
27322
6762
39451
No. Logic
Gates
1.330.01System Control
71.207.36Viterbi Decoder
205.68113.06Total
0.350.02Soft Demapper
14.0614.02SRAMs for Post-FFT
14.0013.76SRAMs for Pre-FFT
0.100.43GI・PLCP Signals
73.3270.50FFT/IFFT
4.841.42Timing Synchronization
0.100.49Coder & Mapping
Power
RX (mW)
Power
TX (mW)
y=((¯ya,ˆyb)Tif k=1
(ˆya,¯yb)Totherwise ,(21)
where (H)jis the j-th column of Hand +denotes
an inverse matrix operation based on a MMSE crite-
rion. The inverse matrices of G2aand G2bare pre-
computed before the MIMO detection at Eqs. (8) and
(9). This pre-computation converts a recursive proce-
dure into a one-time procedure. It prepares both can-
didates of (¯ya,ˆyb) and (ˆya,¯yb) for optimal detection
ordering. Figure 7 depicts the modified procedure in
MMSE-V-BLAST algorithm, which is applied to the
MIMO detection block. While the two candidates
are calculated at Eqs. (10) to (19), the channel order
information of kis simultaneously computed at Eq.
(20). The channel estimation and the pre-processing
finish within a 13-cycle latency including memory ac-
cesses. The numbers of real and complex multipliers
require 16 and 27, respectively.
6. VLSI IMPLEMENTATION
In the VLSI implementations of the SISO-OFDM
and the 2x2 MIMO-OFDM transceivers, their mini-
mum wordlengths have been explored by using a fixed
point simulation [8]. The transceivers have been de-
signed by using Verilog in RTL level design and im-
plemented to logic gates on a 90-nm CMOS standard
cell library. The operating clock frequency is 80 MHz,
VLSI Design of High-Throughput SISO-OFDM and MIMO-OFDM Baseband Transceivers for Wireless LAN Networks 79
Table 9: Circuit performance of the MMSE-V-
BLAST MIMO-OFDM Transceiver.
79.987.0511600923480276MIMO Detection
7814592
1600206
6480
573584
573584
50928
1166008
224887
20286
118353
Circuit Area
(μm2)
2600364
533402
2160
191195
191195
16976
388669
74962
6762
39451
No. Logic
Gates
1.330.01System Control
71.207.36Viterbi Decoder
266.23119.66Total
0.350.02Soft Demapper
14.0614.02SRAMs for Post-FFT
14.0013.76SRAMs for Pre-FFT
0.100.43GI・PLCP Signals
73.3270.50FFT/IFFT
11.796.02
Timing Synchronization
and SNR Estimation
0.100.49Coder & Mapping
Power
RX (mW)
Power
TX (mW)
Fig.8: Photographs of the FPGA board and the RF
modules.
which is common to the transceivers. The power volt-
age is 1.1V for all devices. Circuit area, logic gate
counts, and power dissipation are reported in Table
7, 8 and 9. The SISO-OFDM transceiver was de-
signed in 0.78 millions of logic gates with 110 mW of
maximum power consumption. The Viterbi decoder
has been re-designed to reduce both circuit area and
power dissipation, compared to the previous work [9].
The zero-forcing MIMO-OFDM transceiver has 1.42
millions in logic gates and dissipates 206 mW in the
maximum. The FFT/IFFT and Viterbi blocks have
impact on the overall system. The MMSE-V-BLAST
MIMO-OFDM transceiver has 2.60 millions in logic
gates and increases dissipated power to 266 mW.
The circuit size of the MIMO detection block in the
MMSE-V-BLAST becomes about three times of the
zero-forcing, However, it does not increase power con-
sumption as much as circuit area because the MIMO
detection is executed by a short period.
7. FPGA VERIFICATION
Figure 8 shows the FPGA verification board used
to verify circuit behavior of the OFDM transceivers
and RF modules. Figure 9 shows the block diagram
of the FPGA board in the SISO-OFDM system. The
FPGA board activates three chips of the transmitter,
the receiver, and the Viterbi decoder, which is based
on Xilinx Vertex II-Pro XC2VP70. We have added
an interpolator, a decimator, a random signal gener-
ator, and bus interfaces to communicate with a PC.
The interpolator and the decimator require 100-MHz
DACs DACs ADCs
Rand om Signal
OFDM
Receiver
OFDM
Transmitter
Dem appe r
Viter bi
Deco der
Decim ate & FIR
Inter pola te & FIR
Tes t Da ta
IDE Cable
Receiver
Deco der
Transmitter
Transmit
Receive
Test
PC IF
DACs DACs ADCs
Rand om Signal
OFDM
Receiver
OFDM
Transmitter
Dem appe r
Viter bi
Deco der
Decim ate & FIR
Inter pola te & FIR
Tes t Da ta
IDE Cable
Receiver
Deco der
Transmitter
Transmit
Receive
Test
PC IF
To RF From RF
Fig.9: Block diagram of the FPGA board.
clock frequency and the other modules operate at its
half clock speed. The current FPGA board enables
baseband transmission via ADCs and DACs. BER
and PER can be obtained from this baseband trans-
mission.
8. CONCLUSION
This paper has described the VLSI design of
the SISO-OFDM and the MIMO-OFDM transceivers
achieving a 600-Mbps data rate for wireless LAN net-
works. The proposed frame format is based on the
use of 512-point FFT/IFFT and an 80-MHz occu-
pied signal bandwidth. The 2x2 MIMO configura-
tion doubles the data rate of the SISO-OFDM sys-
tem. Compared to the 600-Mbps transmission mode
in the EWC proposal, the STARC-MIMO has su-
perior transmission performance and lower complex-
ity in the MIMO detection. In the hardware ar-
chitecture, the SISO-OFDM and the MIMO-OFDM
transceivers have been designed by the policy of ap-
plying full-pipeline and concurrent processing. The
zero-forcing and MMSE-V-BLAST techniques have
been implemented to hardware as practical instances.
The OFDM transceivers have been implemented to
a 90-nm CMOS process and evaluated on circuit
area and power dissipation. The FPGA board has
been presented to verify circuit behaviors and execute
baseband transmission. As a future work, the VLSI
implementation of a 4×2 MIMO configuration will be
discussed. The 4×2 MIMO-OFDM system is given by
a LSTBC system [10] which combines layered space-
time (LST) [11] and space-time block coding (STBC)
[12] techniques. The 4 ×2 MIMO has much better
transmission performance than the 2×2 MIMO. This
utilization is assumed in downlink transmission when
a wireless station has four transmission antennas.
80 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007
ACKNOWLEDGMENTS
The authors would like to thank Research and
Development Headquarters, Yamatake Corporation
and the VLSI Design Education and Research Cen-
ter (VDEC), Tokyo University for fruitful discussions.
This study is supported in parts by Semiconduc-
tor Technology Academic Research Center (STARC),
Project 308.
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Shingo Yoshizawa He received the
B.E., M.E. and Dr.Eng. degrees from
Hokkaido University, Japan in 2001,
2003 and 2005, respectively. He is an
Assistant Processor and currently work-
ing at the Graduate School of Informa-
tion Science and Technology, Hokkaido
University. His research interests are
speech processing, speech recognition,
wireless communication, and VLSI ar-
chitecture.
Yoshikazu Miyanaga He received the
B.S., M.S., and Dr.Eng. degrees from
Hokkaido University, Japan in 1979,
1981, and 1986, respectively. From 1983
to 1987, he was a Research Associate
at the Institute for Electronic Science,
Hokkaido University. From 1987 to
1988, he was a Lecturer at the Faculty
of Engineering of Hokkaido University.
From 1988 to 1997, he was an Associate
Professor there. He is currently a Pro-
fessor at the Graduate School of Information Science and Tech-
nology, Hokkaido University. His current research interests are
adaptive signal processing, non-linear signal processing, and
parallel-pipelined VLSI systems.
Nobuo Hataoka He received the
B.S.E.E. degree and the M. Sc. degree
in Electrical and Electronics Engineer-
ing from Tohoku University, in 1976 and
1978, respectively, and the Ph.D in En-
gineering in 1992 from Tohoku Univer-
sity. He joined Central Research Lab-
oratory, Hitachi Ltd. in 1978, and he
spent one year from 1988 to 1989 as
Visiting Researcher at Carnegie Mellon
University in U.S.A. From 1989 to 1993,
he was Laboratory Manager of Hitachi Dublin Laboratory in
Ireland and after returning to HCRL in Japan he took man-
agement responsibilities as Chief Research Scientist. He is cur-
rently Professor of Tohoku Institute of Technology in Sendai,
Japan. His research interests include media implementation on
microprocessors, and algorithm development on speech recog-
nition, speech synthesis, speech translation, and artificial in-
telligence. Dr. Hataoka is a member of the IEEE Acoustic,
Speech, and Signal Processing Society, the Institute of Elec-
tronics, Information and Communication Engineers (IEICE),
Japan, and the Acoustical Society of Japan. He is president-
elect in Information Systems Society of IEICE.
Baiko Sai He received the B.E. from
Shanghai University in 1985, and re-
ceived M.E. from Yokohama National
University in 1991. He worked for Space
and Science Ministry of China in Shang-
hai from 1985 to 1987. He worked
as a system engineer in Pioneer Elec-
tronic Corporation Japan from 1990 to
1996 and as a system design manager
in Philips Semiconductors from 1996 to
VLSI Design of High-Throughput SISO-OFDM and MIMO-OFDM Baseband Transceivers for Wireless LAN Networks 81
2001. The is a LSI product design man-
ager in Rohm Co,.Ltd. His research interests are signal pro-
cessing, communication, video processing and cryptogram.
Norihisa Takayama He received the
B.E. and M.E. degrees in Electrical En-
gineering from Mie University, Japan in
1981 and 1983, respectively. He joined
SANYO Electric Co., Ltd., in 1983. He
has been engaged in research and de-
velopment of VLSI design techniques
for image processing and wireless com-
munication systems. From 2006, he is
working at SANYO Semiconductor Co.,
Ltd.
Masaki Hirata He received the B.S.,
M.S. degrees in electronics engineer-
ing from the University of Electro-
Communications, Tokyo in 1972 and
1974, and Ph.D. degree in electronics en-
gineering from the University of Tokyo,
Tokyo in 1991. He joined NEC Corpo-
ration, Kawasaki, Japan in 1974, where
he has been engaged in the research of
CMOS VLSI circuits design. He worked
at STARC (Semiconductor Technology
Academic Research Center) from 2000 to 2006. He is currently
a senior manager in NEC Electronics Corporation. His re-
search interests focus on System LSI architecture. Dr. Hirata
is a member of the Institute of Electronics, Information and
Communication Engineers of Japan.
Hiroshi Ochi He received the B.E. and
M.E. degrees from Nagaoka Institute
of Technology, and Ph.D. from Tokyo
Metropolitan University, Japan in 1981,
1984, and 1992 respectively. He is a
Processor at the department of CSE,
Kyushu Institute of Technology His re-
search interests are signal processing,
wireless communication, and their VLSI
implementation.
Yoshio Itoh He received the B.E. de-
gree in electronics engineering from Os-
aka Institute of Technology, M.E. and
D.E. degrees in electrical engineering
from Osaka Prefecture University in
1979,1981 and 1991, respectively. He is
now a Professor in the Faculty of Engi-
neering, Tottori University, Japan. His
research interests are in the area of digi-
tal signal processing and communication
systems. From 2000 to 2004, He was an
Associate Editor of Trans. on Fundamentals of IEICE. He is a
member of the IEEE, IEICE and Acoustical Society of Japan.
