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A Formal Specification Model for Hardware/Software Codesign

Authors:
Massimiliano Chiodo
Massimiliano Chiodo
Massimiliano Chiodo
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Paolo Giusto at General Motors Company
Paolo Giusto
Harry Hsieh
Harry Hsieh
Harry Hsieh
  • This person is not on ResearchGate, or hasn't claimed this research yet.
Attila Jurecska at Synopsys
Attila Jurecska
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Abstract and Figures

Embedded controllers for reactive real-time applications are implemented as mixed softwarehardware systems. In this paper we present a model for specification, partitioning, and implementation of such systems. The model, called Codesign Finite State Machines (CFSMs), is based on FSMs and is particularly suited to a specific class of systems with relatively low algorithmic complexity. Pre-existing formal specification languages can be used by the designer to specify the intended behavior of the system and mapped into our model. CFSMs use a non-zero unbounded reaction delay model and hence can be indifferently implemented either in hardware or in software. The implementation only restricts the range of variation of some previously undefined delays, thus preserving formal properties of the specification across implementation refinements. The communication primitive, event broadcasting, is low-level enough to be implemented efficiently and yet general enough to allow higher-level mechanism...
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HW synthesis
Partitioning
Formal Languages
FL Compilers
SIS
C code
SW synthesis
Production
Hardware description
(BLIF−MV)
Interfaces
(BLIF−MV)
Scheduler
Template
Hardware description
(STD CELLS)
VIF
Simulation
Formal
Verification
Partitioned Specification
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... Behaviors de ne functionality, and the time of communication, whereas channels de ne how the communication is performed. 4.5. BEHAVIORAL HIERARCHY The composition of child behaviors in time is called behavioral hierarchy. ...
... In summary, behavioral hierarchy is captured by the tree of function calls to the behavior main methods. 4.6. SYNCHRONIZATION Concurrent behaviors usually must besynchronized in order to becooperative. ...
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... For instance, Esterel is used to describe specifications of Polis, a tool for hardware/software codesign of embedded systems [7]. In Polis, the specifications are translated into networks of Codesign Finite State Machines (CFSMs) [8]. Note that CFSM networks can be converted to safe 2 PNs, as shown next. ...
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... Dans [46], un réseau de Petri hiérarchique (HPN: Hierarchical Petri Net) est utilisé comme modèle de représentation : les transitions représentent les [57,58,18,34,59,60,61]. ...
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