On the ultimate limits of IC inductors-an RF MEMS perspective

Abstract

Inductors are playing an ever-increasing role in RFICs, motivating extensive work on the development of structures to achieve optimized performance. In this paper we review the different approaches being explored to achieve high inductor Q and self-resonance frequency, in the context of conventional CMOS and BiCMOS processes, and examine how the application of RF MEMS techniques may effect superior monolithic inductor performance, and at what expense.

Full text

On the Ultimate Limits of IC Inductors—An RF MEMS Perspective
Héctor J. De Los Santos
COVENTOR, Inc.
7 Corporate Park, Suite 260, Irvine, CA 92606
Abstract
Inductors are playing an ever-increasing role in RFICs,
motivating extensive work on the development of structures
to achieve optimized performance. In this paper we review
the different approaches being explored to achieve high
inductor Q and self-resonance frequency, in the context of
conventional CMOS and BiCMOS processes, and examine
how the application of RF MEMS techniques may effect
superior monolithic inductor performance, and at what
expense.
Introduction
Inductors are playing an ever-increasing role in RFICs [1-
4]. In addition to being frequently employed in passive tuning
circuits, or as high-impedance chokes, many novel
techniques to achieve low-voltage operation in advanced
silicon IC processes rely on the negligible DC voltage drop
across inductors when utilized as loads or as emitter/source
degenerators [3-4]. When fabricated in a planar process, the
trace capacitance to ground tends to lower the inductor self-
resonance frequency, and the substrate conductivity tends to
lower its quality factor (Q) [5]. While optimization of the
spiral geometry and line width [2], [5-6] is essential to tailor
the frequency of maximum Q, this exercise only addresses
minimization of the trace ohmic losses and substrate
capacitance. Thus, a number of attempts to use conventional
processing techniques to diminish the substrate losses created
by eddy currents induced by the magnetic field of the spiral
have been pursued. For instance, while [5] introduced
blocking p-n-p junctions in the path of the eddy current
flowing in an underlying p+ layer, [7] introduced a patterned
metal ground shield to also block the eddy current. These,
and similar approaches, however, only achieve modest
relative improvements and, certainly, do not achieve Qs
much greater than 10, or self-resonance frequencies greater
than a few GHz.
The fabrication flexibility afforded by
microelectromechanical systems (MEMS) technology is
expected to greatly enhance the performance of monolithic
RF passive devices but, by how much and at what expense?
In this paper, for the first time, we present an analysis of
RFIC inductors build in both conventional and RF MEMS
technologies, and establish a projection of their ultimate
achievable performance limits.
Conventional RFIC Inductors
The fundamental monolithic inductor is usually
implemented as a spiral trace disposed on the passivation
layer over a silicon substrate, Fig. 1. The connection to the
innermost turn is effected either through an underpass, or via
an airbridge. An examination of the fundamental structure
reveals the following sources of performance degradation [9]:
(1) Eddy current-induced losses, due to magnetic field
penetration into both the substrate and adjacent traces; (2)
Trace resistance, due to its finite conductivity and width; (3)
Substrate capacitance and ohmic losses, due to their shunting
of the input signal to ground and, thus, causing less than the
input signal to reach the output. These loss elements are
embodied by the circuit model of Fig. 2 [10].
Figure 1. Planar inductor [8].
CS
LSRS
RSi CSi CSi RSi
Cox Cox
CS
LSRS
RSi CSi CSi RSi
Cox Cox
Figure 2. Equivalent circuit model of planar inductor
[10].
A multitude of ways to address one or more of the above
inductor performance-limiting factors, in the context of
conventional Si processes, have been advanced. Next,
respective typical cases are reviewed.
Eddy current blocking structures are shown in Fig. 3. In
these structures, the eddy current, which flows in paths
around the axis of the spiral, is reduced by introducing
structures that increase the path resistance. In the example of
Fig. 3(a) [5], this is accomplished by inserting narrow stripes
of n+ regions perpendicular to the current flow such as to
create blocking p-n-p junctions. This blocking structure
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resulted in a Q improvement from 5.3 to 6.0 (13.2%) at 3.5
GHz on a 1.8nH inductor, obtaining an inductance-per-turn
of 0.9nH.
(a)
(b)
Figure 3 (a) Eddy-current blocking approaches: (a) p-n-p
junction perpendicular to current flow path [5]. (b)
Patterned metal ground plane with open slots [7].
In the patterned-ground approach, Fig. 3(b) [7], slots,
oriented perpendicularly to the spiral, are etched in the
ground plane. These, act as open circuits to impede the path
of the eddy currents. The slots are made with a width narrow
enough to preclude the vertical electric field from penetrating
down to the underlying silicon, and merge together at a metal
strip around the periphery. Implementation of this scheme
has resulted in a Q improvement from 5.08 to 6.76 (33%) at
2 GHz on a 7.5 nH inductor, obtaining an inductance-per-
turn of 1.07nH.
In the substrate damage approach [11], the low-resistivity
of the Si substrate is increased by disordering the lattice sites,
i.e., by damaging the lattice structure with high-energy-
implanted (200keV) +
28
Si ions. Starting with a low-
resistivity Si substrate ( cm⋅Ω− 105~
ρ
), implanting
ions in concentrations ranging from 319
101−
×cm to
319
103−
×cm , resulted in Qs between 3.8 and 5.8,
respectively, at about 2 GHz for 1.1nH to 1.25nH inductance
values, obtaining an inductance-per-turn of ~0.78nH.
Approaches to reduce metal trace losses, Fig. 4, involve
reduction of both conduction- and magnetically-induced
losses.
Figure 4. Losses in inductor metal trace [12].
From a study of the field distribution in a spiral [2], [9], it
was determined that ohmic losses are predominant in the
outer turns, while, since the magnetic field reaches a
maximum near the axis, magnetic losses predominate in the
inner turns. Accordingly, an algorithm to vary the trace
width from a small width for the inner turns, to a larger
width for the outer turns, resulted in a layout-optimized
structure, Fig. 5. For inductors realized over an etched bulk
(so as to not have substrate losses present) with metal traces
exhibiting Ωm20 sheet resistances, this approach yielded a
measured Q of 17 at 1.5 GHz for a 34nH inductor, and
predicted Q values greater than 40 for a 20nH inductor at 3.5
GHz, which represents a projected Q improvement of 60%,
with respect to single strip-width inductors operating also at
3.5GHz [9].
Figure 5. Metal loss-optimized inductor layout [9].
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Recent work [13] aimed at obtaining both increased Q and
self-resonance frequency, without process modifications, have
concluded that differentially driven inductors have the
potential to exhibit (ideally) double the Q and increased self-
resonance frequency, with respect to single-ended inductors,
due to the reduced effect of the substrate shunt parasitics in
the differential case. With the voltages and currents at Ports 1
and 2 excited 180° out of phase, when differentially excited,
Fig. 6, a useful property of the structure is that the trace
currents flow in the same directions and this increases the
inductance per unit area.
Underpass Axis of Symmetry
i2
i1
Inductor 1 Inductor 2
Common Node
Port 1 Port 2
Underpass Axis of Symmetry
i2
i1
Inductor 1 Inductor 2
Common Node
Port 1 Port 2
Figure 6. Symmetrical differentially driven microstrip
inductor [13].
The approach has resulted in Qs of 6.6 and 9.3 at 1.6 GHz
and 2.5 GHz, respectively, for an inductor of 8nH [13].
As may be surmized by examining the approaches
presented thus far for optimizing planar inductors in
conventional silicon processes, these fall into two
fundamental categories, namely, substrate insulation
techniques, and layout optimization techniques. Two other
opportunities for performance enhancement may be also
available, depending on the number of top metal interconnect
lavels and the ability to increase the thickness of the traces.
Pertaining to these, the following examples are relevant: (1)
A 1.88nH inductor with a Q of 6-10 at 4GHz fabricated on a
mcm
µ
31/10 −⋅Ω single-metal process, demonstrated
by Long and Copeland [14]; (2) A 13nH inductor with a Q of
12 at 3GHz fabricated on a mcmk
µ
2/2 ⋅Ω double-metal
process, demonstrated by Park et al. [15]; and (3) A 2.2nH
inductor with a Q of 16 at 2GHz fabricated on a
mcmk
µ
3.4/12 ⋅Ω triple-metal process, demonstrated by
Burghartz et al. [16].
Clearly, in light of the fact that most commercial silicon
bipolar and BiCMOS processes employ wafers with
resistivities in the neighborhood cm⋅Ω10 , and that to
reduce hot-electron induced substrate currents, as well as
isolate sensitive analog circuits from noisy digital circuits,
most sub-micron CMOS wafers employ substrates with
resistivities around cm⋅Ω01.0 [2], it is not difficult to
see that the substrate poses the ultimate limitation on the
performance of IC inductors. Some estimates [14], in fact, set
this limit at approximately a Q less than 10 in the 1-3GHz
range for a 1nH inductor.
The potential of RF MEMS technology to overcome the
“substrate barrier” limiting the performance of IC inductors
is presented next.
RF MEMS-Enabled Inductors
In RF MEMS technology, the power of surface and bulk
micromachining fabrication techniques [17] is exploited to
either suspend within the bulk [18], or elevate above the
wafer surface [19], inductor structures, thus eliminating the
major sources of performance degradation.
Bulk micromachined inductors, similar to that shown in
Fig. 7, are realized by removing the substrate under the
inductor spiral via top-side etching [18]. This type of
structure resulted in a self-resonance frequency enhancement
from 800 MHz to 3 GHz, upon substrate removal, and a Q of
22 at 270 MHz on an 115nH inductor, obtaining an
inductance-per-turn ratio of 5nH [1].
Figure 7. Bulk-micromachined inductor [18].
While the performance of bulk micromachined inductors
improves upon that of their conventional counterparts,
questions have been raised regarding their ruggedness to
withstand subsequent wafer processing, lack of a good RF
ground, and susceptibility of their characteristics to
electromagnetic coupling. This issues were addressed in the
elevated structure of Fig. 8 [19]. The structure consists of an
elevated inductor suspended over a m
µ
30 -deep copper-lined
cavity etched in Si bulk. The cavity depth is chosen such that
the eddy currents induced in the metal shield are small.
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Figure 8. Schematic of a copper-encapsulated polysilicon
inductor suspended over a copper-lined cavity beneath
[19].
This approach yielded a Q of 30 at 8 GHz on a 10.4nH
inductor with a self-resonance frequency of 10.1 GHz, and an
inductance-per-turn of 1.48nH.
While substrate removal and shielding, and spiral
elevation do improve inductor performance, the remaining
parasitic capacitance, between metals trace and the substrate,
poses the ultimate limitation on improvement. The solenoid
inductor, Fig. 9, addresses these issues [20].
Figure 9. SEM photograph of 20-turn, on-Si, air-core, all-
copper solenoid inductor(upper: overview, lower:
magnified view) [20].
This approach yielded a Q of 16.7 at 2.4 GHz on 2.67 nH
inductors, with an inductance per-turn of 0.136nH. One
advantage of solenoid inductors, over spiral ones, is that they
exhibit a linear relationship between inductance and number
of turns.
Another approach aimed at decoupling inductor
properties from those of the substrate is the self-assembly
principle, Fig. 10 [21].
Figure 10. 4½-turn meander inductor after self-assembly
[21].
In this approach, solder surface tension self-assembly is used
to bring planar inductor structures perpendicular to the
substrate. It has yielded improvements in the Q of 2nH
meander inductors from 4 at 1GHz, for the planar realization,
to 20 at 3 GHz for the self-assembly implementation, with
0.44nH per turn [21].
RF MEMS Perspective on RFIC Inductors
As demonstrated in the previous section, the versatility of
RF MEMS fabrication technology to decouple IC inductor
performance from substrate characteristics is unquestionable.
It might appear, however, that, to take advantage of it, one
would have to incur “extra” processing steps, and this is
indeed the case. Nevertheless, the fact that these extra
processing steps may be implemented as a “post-process
module” [22], that does not require chip manufacturers to
modify their high-volume fabrication processes, makes the
approach extremely appealing, given the enabling capability
of RF MEMS. Indeed, as the frequency capability of
advanced silicon IC processes increases to many multiples of
GHz, the concomitant manifestation of substrate losses will
become progressively more difficult to circumvent. The
future, thus, will inexorably lead to RF MEMS.
Conclusions
The performance of monolithic RFIC inductors has made
great strides, despite the limits set by poor substrate
characteristics, in particular, low resistivity. In this context, it
is expected that inductors with Qs and inductance markedly
greater than 10 and 1nH, respectively, in the 1-4GHz
frequency range will not be possible. Therefore, the extension
of silicon processes to higher frequency wireless applications
will inexorably lead to the exploitation of RF MEMS, via
post-processing techniques.
Acknowledgments
I would like to thank ECTC 2002 Program Committee
member Ms. Lei Mercado, of Motorola, Inc., for the
invitation to contribute this paper.
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