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Deterministic DEM DAC Performance Analysis
Hanjun Jiang1, Degang Chen2 and Randall L. Geiger2
Institute of Microelectronics1 Dept. of Electrical & Computer Engineering2
Tsinghua University1 Iowa State University2
Beijing, 100084, P. R. China1 Ames, IA 50011 USA2
Abstract— A rigorous and complete analysis of the
Deterministic DEM (DDEM) DAC performance is presented.
With this analysis, DDEM DAC’s equivalent linearity as ADC
static linearity test stimulus source can be precisely predicted.
Simulation result is given to validate this theoretic al analysis.
Key Words— Deterministic DEM DAC, ADC, built-in self-test,
equivalent linearity
I. INTRODUCTION
Built-in self-test (BIST) is viewed as the most promising
solution to testing today’s high-resolution high-speed ADCs,
especially those deeply embedded in SoC applications [1].
For the past decade, researchers have gained great
improvements in building cost-effective stimulus sources for
ADC BIST. [2] However, conventional types of stimulus
source, such as linear ramp generators and high performance
DACs, cannot meet the requirement of testing today’s high
performance ADCs, either due to insufficient linearity or
high implementation cost.
The deterministic dynamic element matching (DDEM)
technique was proposed as a solution to this problem [3]. In
this technique, DDEM cyclic switching control is applied on
low accuracy/linearity DACs to generate stimulus signals for
high resolution ADC static linearity BIST. Figure 1 shows
the block diagram of this solution.
Figure 1. DDEM technique for ADC BIST
The mechanism of the DDEM technique was explained
in [4] by examining the output probability distribution
function (PDF) based on the analysis of the “averaged”
DAC. This analysis answers the question why low
resolution/linearity DACs with DDEM control can be used
for high resolution ADC static linearity test. In [5], attempt
was made to evaluate the performance for a given DDEM
DAC quantitatively. A formula was given to predict the
equivalent linearity of a DDEM DAC as ADC static linearity
test stimulus source. This formula matches the simulation
results well when the DAC resolution and DDEM iteration
number are low. However, simulation results show that
remedies must be made to this formula when the DDEM
DAC resolution goes high.
In this paper, rigorous and complete analysis is presented
to inspect the performance of DDEM DACs. With both the
random element mismatching errors and quantization errors
included in this analysis, a new formula is derived to predict
the equivalent linearity of a given DDEM DAC. The
predicted performance using this formula matches the
simulation results well even for modest-high resolution
DDEM DAC with large DDEM iteration number.
This paper is organized as following. In Section II, the
DDEM method is reviewed, symbols are defined and
performance evaluation criterion is established. Rigorous and
complete analysis of the DDEM DAC equivalent linearity as
ADC static linearity test stimulus source is presented in
Section III. Simulation result is given in Section IV to
correlate the theoretical result. The work is concluded in
Section V.
II. DDEM DAC AND EVALUATION CRITERION
In this section, the cyclic DDEM switching sequence for a
current steering thermometer-coded DAC is reviewed.
A normal n-bit thermometer-coded DAC has 2n-1 current
source elements. In the DDEM DAC, one extra current
source element has been added so that an n-bit DDEM DAC
has a total of N = 2n current sources. We use
()
Nji j,...,1= to represent the j-th current source element
out of the total N elements.
For a digital word “k”, the DDEM method
deterministically picks the k current sources to be switched
on. Multiple outputs are generated for each digital word “k”
with different deterministically selected current source
combinations. The number of outputs per DAC input code is
denoted as p. p is also termed as the DDEM iteration
number. An integer q is defined by the expression q = N/p.
Figure 2 illustrates the general idea of the DDEM
technique with a 5-bit DDEM DAC as an example. To show
the switching sequence, the current sources are arranged
conceptually and sequentially around a circle, as seen in
Figure 2, to visualize a wrapping effect whereby the Nth
current source iN is adjacent to the first current source i1. p
This work was supported, in part, by Iowa State University, National
Science Foundation and Semiconductor Research Corporation.
Low Accuracy
Low Linearity
DAC
DEM
Switching
Control
ADC
Under Test
Histogram
Analysis
ADC
Performance
Low Accuracy
Low Linearity
DAC
DEM
Switching
Control
ADC
Under Test
Histogram
Analysis
ADC
Performance
3860
1-4244-0921-7/07 $25.00 © 2007 IEEE.
index current elements uniformly spaced around the circle
are selected from all the N elements. For each input code k,
the DDEM DAC generates p output voltage samples with
each obtained by consecutively switching on k current
sources starting from one of the p index current sources. In
Figure 2, p=8, and the 1st, 2nd, 5th and 8th output sample
out of all the 8 output samples corresponding to DAC code
10 are depicted. The resistor RC is ch osen so that when all of
the current sources are on, the voltage output is at the desired
maximum.
Figure 2. DDEM DAC Exa mple -- 5-bit D AC w/ 3 -bit DDEM Contr ol
The aim of a DDEM DAC is to output voltage samples
with uniform histogram for histogram-based ADC static
linearity test. Assume that the stimulus to the DUT (ADC)
has a voltage range [Vsmin, Vsmax] and the ADC input voltage
range is [Vmin, Vmax]. The stimulus voltage range should cover
the DAC input range. For an arbitrary voltage, Vt, let h(Vt)
represent the number of stimulus voltage samples that falls
into [Vsmin, Vt]. The linearity of h(Vt) with respect to Vt will
determine ADC test accuracy. [6] Define the error
expression e(Vt) as
() ( )
minmin )()( VVCVhVhVe thtt −⋅−−= (1)
in which the constant h
C is the ideal value of
()()()
minmin /)( VVVhVh tt −− . The DDEM DAC performance
will be evaluated by estimating e(Vt) .
III. DDEM DAC EQUIVALENT LINEARITY
In the following, the ADC test performance using the
DDEM DAC as th e test stimulus source will be evaluated by
deriving )(t
Ve as defined in (1), for any voltage, Vt, in ADC
input range [Vmin, Vmax].
We first expand the number of current sources virtually to
2N by letting ),...,1( Nrii rrN ==
+. Then, virtually, we have
2N current sources: NNN iiiii 21,21 ,...,,...,, +.
Let 0]0[
0=Vand )2,...,1...(][
1
0NkiRkV
k
r
rC =⋅= ∑
=
, in which
RC is the output resistance of the DDEM DAC. Note that the
first half of the sequence is the output voltage sequence of a
regular n-bit DAC. Let ][
0NVVm=, and m
Vis the maximum
output of the DDEM DAC. Define NVLSB m/=.
Now, define ][kINL and ][kDNL for the original DAC
without DDEM.
()
)2,...,0.......(/][][ 0NkLSBLSBkkVkINL =⋅−=
()
)2,...,1......(/]1[][][ 00 NkLSBLSBkVkVkDNL =−−−=
From this definition, we have:
)2,...,1......(][][
1
NkrDNLkINL
k
r
== ∑
=
(2)
),...,1......(0][
1
NkrDNL
Nk
kr
==
∑
−+
=
(3)
With the DDEM cyclic switching sequence, the DAC
outputs p·N output voltage samples. These p·N output
voltage samples can further be decomposed into p ramps
with N samples in each ramp. The 1st ramp is given
by ∑
=
=⋅
k
r
rC NkiR
1
),...,1( . The d-th (1≤d≤p) ramp is given
by ),...,1(
)1(
)1(1
NkiR
dqk
dqr
rC =⋅ ∑−+
−+=
, or rewritten as
{}
{}
NkdqVdqkVkV d≤≤−−−+= 1:)]1([)]1([][ 00
)( .
For an arbitrary voltage t
V less than m
V, let )(
)(
t
dVh
represent the number of elements less than t
V in
{}
][
)( kV d.
{}
NkVkVkVVh t
dd
t
d≤≤≤= 1,][:][)( )()()(
The definition of )(
)(
t
dVh can be explained using Figure 3.a.
In this figure, N+1 mark arrows on an axis represent the d-th
ramp sequence. The relative position of the k-th(1≤k≤N)
arr ow on the axis represents th e val ue of ][
)( kV d. By
definition, t
V is located between the [
()
t
dVh )( ]-th sample
(arrow) and the [
()
1
)( +
t
dVh ]-th sample.
…… ……
0
0NN-1N-2N- 3
123
Vm
Vt
…… ……
0
0NN-1N-2N-3
12 3
Vm
Vt
h(d)(Vt)h(0)(Vt)
h(0)(Vt)
b) Output sequence of an ideal DAC
a) Output sequence of the dth ramp of the DDEM DAC
…… ……
0
0NN-1N-2N- 3
123
Vm
Vt
…… ……
0
0NN-1N-2N-3
12 3
Vm
Vt
h(d)(Vt)h(0)(Vt)
h(0)(Vt)
b) Output sequence of an ideal DAC
a) Output sequence of the dth ramp of the DDEM DAC
Figure 3. Nonideal and ideal DAC output sequences
Let
() ( )
|}1,:{|/
)0( NkVLSBkkVVNfloorVh tmtt ≤≤≤⋅=⋅= ,
in which
()
NVh t≤≤ )0(
0.
()
t
Vh )0( is marked on the axis in
Figur e 3.b with uniformly spaced arrows, corr esponding to
the output voltages of an ideal DAC. For a non-ideal DAC,
()
t
dVh )( deviates from
()
t
Vh )0( , as shown in Figure 3. The
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1st output for code10 2nd output for code10
5th output fo r code10 8th output for code10
3861
difference between Vt and the [
()
t
Vh )0( ]-th sample in the
sequence
{}
][
)( kV d reflects the DAC INL at code
()
t
dVh )( .
This voltage difference divided by the DAC LSB can be
used to approximate the difference between
()
t
Vh )0( and
)(
)(
t
dVh . Her e, the approximation is based on the
assumption that the local DNL of the DAC sequence is not
large, and this assumption is valid for thermometer-coded
DAC design. The approximation error can be viewed as a
quantization error and is distributed over the range
of
(
]
5.0,5.0−. Denote this error as )(d
ε
. Thus, we have the
following expression for )(
)(
t
dVh :
[]
p)d(1
)(
)()( )(
)0()(
)0()( ≤≤+
−
+= d
t
d
t
tt
d
LSB
VhVV
VhVh
ε
(4)
For every d, if we apply (2), we have:
)]1([)]1()([)]([ 0
)0(
0
)0()( −−−+= dqVdqVhVVhV tt
d
()
)()]1([)]1()([ )0()0(
tt VhdqINLdqVhINLLSB +−−−+⋅=
+−+⋅= ∑
=
)()]1([ )0(
)(
)0(
1
t
t
Vh
k
VhdqkDNLLSB
Substitute this into (4), we have:
p)d(1)]1([)( )(
)(
)0(
1
)( ≤≤+−+−= ∑
=
d
t
Vh
k
t
t
ddqkDNL
LSB
V
Vh
ε
(5)
Now calculate )(t
Vh and )(t
Ve as defined in Section II.
)( t
Vh denotes the total number of DDEM DAC voltage
samples that are less than t
V.
∑∑∑
∑
===
=
+−+−=
=
p
d
d
p
d
t
Vh
k
t
p
d
t
d
t
dqkDNL
LSB
V
p
VhVh
1
)(
1
)(
)0(
1
1
)(
)]1([
)()(
ε
Let )&,0,0()(
)0( ZmtptqmmtqVh t∈<≤≤<+⋅= .
Applying (3) leads to:
∑∑∑
===
+−+−=
p
d
d
p
d
m
k
t
tdqkDNL
LSB
V
pVh
1
)(
11
)]1([)(
ε
(6)
h
Cdefined in (1) is given by
m
hV
pN
C= for this DDEM DAC.
Then by definition,
∑∑∑
===
+⋅−−+−=
p
d
d
t
m
p
d
m
k
t
tV
V
pN
dqkDNL
LSB
V
pVe
1
)(
11
)]1([)(
ε
t
m
V
V
pN ⋅is exactly
L
SB
V
pt by definition. If we change the
order of DNL[k] summation, we have:
∑∑∑
===
+−+−=
p
d
d
m
k
p
d
tdqkDNLVe
1
)(
11
)]1([)(
ε
(7)
)( t
Ve is composed of two items. The first item is a
summation of DAC DNL[k]’s, and can be treated as the INL
of an n-bit DAC. The second item is caused by the
quantization effect. We can approximately assume that
{}
)( d
ε
have a standar d deviation of 12/1 , since th e
quantization error is normally treated to have a uniform
distribution over the range of ]5.0,5.0(−with the standard
deviation equal to 12/1 . Hence, the standard deviation of
the second item is given by 12/p if )(d
ε
’s are
independent.
When p is small, the first item in (7) dominates. We can
ignore the quantization error item and approximate )(t
Ve to:
∑∑
==
−+−≈
m
k
p
d
tdqkDNLVe
11
)]1([)(
Since the full range of h(Vt) is p·N, the percentage error in
the DDEM DAC output voltage sample’s distribution is
bounded by INL/p·N. The DDEM DAC has an equivalent
accuracy of eq
nbits, where eq
nis given by:
()()
INLpnINLpNneq 222 loglog15.0//log −++≈≈
The DAC effective number of bits (ENOB) is defined by
()
5.0/log 2INLn −, giving:
pENOBn DACeq 2
log+≈
This means that eq
nincreases by 1 bit every time p doubles
when p is small. However, as p becomes very large, the
second item can become larger than the first item. When p is
adequately large, the second item ∑
=
p
d
d
1
)(
ε
dominates. Under
the situation that )( d
ε
’s are independent, the standard
deviation of ∑
=
p
d
d
1
)(
ε
is inversely proportional to pwhen
normalized to p·N. This means that, when p is large,
eq
nincreases by 0.5 bit every time p doubles. A trip point
T
p happens when 12
p is comparable to the INL of the
original DAC. For this trip point eq
n incremental speed
changes from 1 bit to 0.5 bit for doubling p. Wh en p is equal
to T
p, ∑
=
p
d
d
1
)(
ε
is comparable to the first item in (7) in
magnitude, and the summation of these two items gives
1log2−+≈ TDACeq pENOBn in the worst case that the
magnitudes of these two items are added.
In summary, we have the following formula for the
equivalent linearity of a DDEM DAC:
3862
>+−+
=−+
<+
≈
TTTDAC
TTDAC
TDAC
eq
pppppENOB
pppENOB
pppENOB
n
)/(log5.01log
1log
log
22
2
2
(8)
in which T
p is given by solving DAC
TINL
p≈
12 .
Equation (8) is obtained based on the assumption that )( d
ε
’s
are independent. The correlation among )( d
ε
’s can affect in
two aspects. First, T
p will be smaller than what is expected.
Secondly, when p is larger than T
p, we have:
)/(log1log 22 TTDACeq pppENOBn
α
+−+≈
in which
α
is less than 0.5.
IV. SIMULATION CORRELATION
To validation the analysis presented in Section III,
simulation was done to compare the 12-bit DDEM DAC
performance with different DDEM iteration numbers p, and
the equivalent linearity was quantized to draw a curve. In the
simulation, the DAC has 4096 randomly generalized current
elements with the same normal distribution, and the
normalized standard deviation is set to be 6%. The DDEM
DAC is used to test a simulated 14-bit ADC. Although the
simulation result of only one DAC-ADC pair is shown here,
the result is repeatable for all the random generalized DAC-
ADC pairs in simulation.
The original DAC’s INL is about 4 LSB. By definition,
this DAC’s ENOB is about 9 bits. The DDEM DAC’s output
samples are used as the stimulus for the 14-bit ADC linearity
test. The ADC INL[k] test errors (difference between
estimated INL[k] and true INL[k]) are compared under
different DDEM iteration number p ranging from 8 to 1024.
Figur e 4 shows ADC INL[k] test error curves when p is 8,
32, 128, and 512, respectively. It is clear that test errors
decrease when p increases.
Figure 4. ADC test errors under different p
Under each p, the DDEM DAC equivalent linearity is
calculated from the above simulation results. Basically, if we
use a 14-bit ideal DAC to test a 14-bit ADC, the maximum
INL[k] test error (absolute value) will be about 1 LSB. Based
on this, if the test error is
ε
LSB, we can claim that the test
stimulus source has an equivalent linearity of
ε
2
log14 −
bits. With this definition, the 12-bit DDEM DAC equivalent
linearity under different p is calculated and shown in Figure
5. Theoretical prediction using (8) is also drawn in Figure 5.
Note solving DAC
TINL
p≈
12 gives 192≈
T
p. Since log2p
can only be an integer, we can take 128=
T
p. It can be seen
that the theoretical prediction according to (8) matches the
simulation result quite well. The small theoretical prediction
error mainly comes from the approximation in (8).
816 32 64 128 256 512 1024
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
16.5
17
DDEM it erati on number p
Number of Bits
DDEM DAC E quivalent Lineari ty
simulation result
theoret ical predict ion
Figure 5 Simulated result and theoretical predction of DDEM DAC neq
V. CONCLUSION
The performance of a DDEM DAC as the ADC static
linearity test stimulus source has been analyzed rigorously in
this paper. A formula is given to pr edict the DDEM DAC
equivalent linearity quantitatively. The theoretical prediction
matches the simulation results well. This analytical result can
be used to determine th e DAC number of bits, element size,
and number of DDEM control bits for cost-effective DDEM
DAC implementation.
REFERENCES
[1] “International Technology Roadmap for Semiconductors,” 2003
edition, http://public.itrs.net/Files/2003ITRS/Home2003.htm
[2] B. Provost and E. Sanchez-Sinencio, “On-chip ramp generators for
mixed-signal BIST and ADC self-test”, IEEE Journal of Solid-State
Circuits, vol. 38, no. 2, pp.263 -273, Feb. 2003
[3] B. Olleta, L. Juffer, D. Chen, and R. L. Geiger, “A Deterministic
Dynamic Element Approach to ADC Testing”., Proc. of 2003 IEEE
ISCAS, vol. 5, pp. V-533-535, Bangkok, Thailand, May 2003
[4] H. Jiang, D. Chen and R. L. Geiger, “Dither Incorporated
Deterministic Dynamic Element Matching for High Resolution ADC
Test Using Extremely Low Resolution DACs”, Proc. of 2005 IEEE
ISCAS, vol. 5, pp.4285-4288, Kobe, Japan, May 2005
[5] B. Olleta, H. Jiang, D. Chen and R. L. Geiger, “A Deterministic
Dynami c Element Matchin g Approa ch for Testing High-Resolution
ADCs With L ow-Accuracy Excitations”, IEEE Trans. on
Instrumentation and Measurement, Vol.55, Iss. 3, pp. 902-915, Jun
2006
[6] IEEE standard for terminology and test methods foranalog-to-digital
converters, IEEE Standard 1241-2000, 2000
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