A fast locking DLL clock synthesizerDLL

Abstract

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. The DLL has several inherent advantages, such as no jitter accumulation, fast locking and easy integration of the loop filter. This paper proposes a new programmable DKK that includes a new PFD (phase frequency detector) and a new VCDL (voltage controlled delay line) to generate multiple clicks. It can generate clocks from 3 to 10 times of input clock with 5μs locking time. The HSPICE simulation with 0.35μm CMOS process verifies the proposed DLL operating in the frequency range of 300 MHz to 1 GHz.

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Young-Shig Choi, Hyuk-Hwan Choi, Tae-Ha Kwon KORUS’2005 830
A Fast Locking DLL Clock Synthesizer
Young-Shig Choi, Hyuk-Hwan Choi, Tae-Ha Kwon
Div. of Electronic, Computer and Telecommunication Eng., Pukyong National University,
Busan, 559-1, Korea Young-Shig Choi,
Abstract
- In this paper, a new programmable DLL
(delay locked loop) based clock synthesizer is proposed.
The DLL has several inherent advantages, such as no
jitter accumulation, fast locking and easy integration of
the loop filter. This paper proposes a new programmable
DKK that includes a new PFD (phase frequency detector)
and a new VCDL (voltage controlled delay line) to
generate multiple clicks. It can generate clocks from 3 to
10 times of input clock with 5µs locking time. The
HSPICE simulation with 0.35µm CMOS process verifies
the proposed DLL operating in the frequency range of
300MHz to 1GHz.
Keywords
: DLL, clock synthesizer, frequency
multiplication, VCDL.
I.
INTRODUCTION
As the speed performance of VLSI systems
increases, more emphasis is placed on the high-speed
clock synthesizer. High-performance system such as
CPU and DSP requires high frequency clocks to
transfer data between blocks. Therefore, a system
block that can generate high-speed on-chip clocks
from the outside clocks is required. Generally, PLL
(phase locked loop) is widely used for clock
generation [1]-[4]. However, it is not easy to design
because the PLL is a higher order closed-loop
feedback structure. The loop bandwidth is easily
influenced by the PVT (process, voltage, temperature)
fluctuations. It can cause instability in PLL operation.
Moreover, it has disadvantages such as being late for a
locking time and jitter accumulation due to closed-
loop VCO (voltage controlled oscillator). On the other
hands, the DLL using the VCDL instead of VCO is a
first order system, and then always stable. It also has
several other advantages such as no jitter
accumulation, easy integration of loop filter and fast
locking time. Table 1 summarizes the characteristics of
the PLL and DLL. Thus, DLL based clock synthesizer
has been studied to overcome the difficulty of
generating various clocks while keeping its inherent
characteristics. In this paper, a new architecture DLL is
proposed to be a clock synthesizer.
TABLE 1.
COMPARISONS OF PLL AND DLL.
PLL DLL
VCO
Jitter accumulation
High order system
Can be unstable
Hard to design
Costly to integrate LF
VCDL
No jitter accumulation
First order system
Always stable
Easier to design
Easier to integrate LF
II.
CONVENTIONAL DLL BASED CLOCK
SYNTHESIZER
A conventional DLL used as a local oscillator for
PCS (personal communications service) applications
has used an edge combiner for the frequency
multiplication [5]. However, it requires a LC tank at
the output to enhance the load impedance at the
resonant frequency, which consumes a large chip
area. Also, a low-Q inductor for low close in-phase
noise draws a large tail current to achieve the required
output swing.
Another drawback is that the frequency
multiplication ratio is fixed once the LC tank component
values are chosen. A self-correcting DLL based clock
synthesizer used AND-OR gates for the frequency
multiplication [6]. The self-correction solves a false
locking problem, and also it has advantages such as a
generation of multi-phase clocks and the fast locking.
However, it requires correct duty ratio of the input clock
because it synthesizes clocks using signals generated by
each delay cell for the required clock synthesis. It can
generate only the multiples of three. Another DLL based
clock synthesizer extracts rising edges of each delay cell
and generates multiple clocks [7]. It has an advantage that
the duty ratio of input clock should not be 50%. In this
architecture, only one fixed multiple clocks can be
generated if the number of delay cell is chosen.
III. PROPOSED DLL BASED CLOCK
SYNTHESIZER
As shown in Fig. 1, the proposed DLL comprises of
a PFD (phase frequency detector), a CP (charge
pump), a loop filter (LF), a VCDL and a frequency
multiplier. The PFD compares an external reference
clock and VCO output clock and it produces two
digital signals (UP and DN) whose width is
determined depending on the frequency and phase of
the two
signals. The CP converters the PFD output signal
into a current that is fed into the LF determining the
output LF voltage, Vc. Vc, a control voltage of VCDL,
which is connected to each delay cell, controls the delay
time of the delay cells. There is no jitter accumulation in
DLL contrary to PLL because the input signal of DLL is
used as the input signal to the VCDL. The delay range of
VCDL caused by Vc can also be widened according to
external control signals. Finally, the frequency
multiplier block produces the wanted clock with the
signals from VCDL. Multiple clocks can be determined
by the external control signal.
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KORUS’2005 Young-Shig Choi, Hyuk-Hwan Choi, Tae-Ha Kwon 831
Phase Freq.
Detector Charge
Pump Loop
Filter
Control
Block
Voltage Controlled Delay Line
Frequency Multiplier
Fref
Fout Control
MN
UP
DN
Vc
DLL
VCDLout
L
Fig. 1. Block diagram of proposed DLL based frequency synthesizer.
1. PFD with Input Buffer
It is important to lock the signal within one period of
VCDL to generate multiple clocks in the proposed DLL
based clock synthesizer. The PFD shown in Fig. 2 has
two important characteristics to satisfy the previous
condition. First, the proposed PFD has operation range of
(
π
2−~
π
2+) wider than other phase detectors of
(
π
−~
π
+) in order to solve false locking problem.
Second, the VCDL is very sensitive to capacitance
existed in circuit because it controls the delay time of
signals. To prevent from happening of unwanted delay
in VCDL, the sum of capacitance at the input of next
delay cell should be same. When the final output of
VCDL is connected to the PFD, the sum of capacitance
including the input capacitance of next delay cell and the
input capacitance of the PFD is becoming larger. Hence,
the delay time of last stage in VCDL is longer than that of
previous stages. This phenomenon continuously
generates jitters at output of clock synthesizer. To solve
the problem, the same buffer used in VCDL is added to
the input of D F/F as shown in Fig. 2. The same buffer is
also added to the input of other D F/F to make the same
condition for the two signals, Fref and VCDL output. The
buffer is made of the delay cell in Fig. 3(b). This scheme
makes the capacitance equal at each delay cell in VCDL.
reset
Fref
VCDLout
UP
DN
PFD INPUT
BUFFER
PFD INPUT
BUFFER
Fig. 2. Schematic of proposed PFD with input buffers.
2. Proposed VCDL with Variable Delay Range
The schematic diagram of the VCDL with three
features is shown in Fig. 3(a). First, the desired number
of delay cell can be chosen for the application. A
DEMUX between delay cells receives the external
control signal and chooses the number of the delay cell.
This chosen number of delay cell becomes the desired
multiplication ratio of frequency synthesis. In order
words, delay cells should be chosen so as to generate
the clock that is N multiples of the input frequency, Fref.
The input
N
signal Fref of VCDL exactly goes through delay
cells in one period. If the period of Fref is T, the delay of
each delay cell is when the DLL is in-lock. Thus,
there are clock edges at each point. Consequently,
the edge detector will produce signals at every clock
edges and those signals will be combined to generate N
multiples of Fref. Furthermore, unused delay cells
depending on the controlled signal reduce power
consumption. Second, it can control the delay range
widely by selecting the number of the MOS capacitor in
the delay cell [8]. As shown in Fig. 3(b), one side of each
MOS capacitor is connected to delay cell through switch
and the other side is connected to GND. The MOS
capacitors provide large delay in the delay cell. The
ON/OFF of the switches is controlled by the external
control signals. Once the MOS capacitor generates large
delay in the delay cell, the control voltage (Vc) provides
fine tuning delay with voltage controlled resistor (VCR).
This architecture makes the DLL has a fast locking
characteristic. Furthermore, the operating range of the Vc
when DLL is in-lock can be chosen to the range of CP
output voltage that shows no current mismatch by
carefully selecting the size of capacitors. Fig. 3(c) shows
the delay time to the control voltage Vc. As shown in Fig.
3(c), when the DLL is in-lock, Vc is between 1V and 2V.
The delay time is increased by 0.1ns between 1V and 2V
at each selected capacitor. The MOS capacitors provide
large delay and the control voltage with the VCR adjusts
VCDL within the 0.1ns range of delay. With this scheme,
the control voltage can be placed at the around of Vdd/2
that exhibits the lowest current mismatch caused by
Source-Drain voltage. It helps VCDL to have lower jitter
characteristic. Third, the proposed delay cell uses a latch
structure and inverter to prevent the distortion of the
waveform that can be caused when larger capacitors are
selected. This fact contributes to the linear delay
operation of VCDL to Vc as shown in Fig. 3(c). By using
these operating features, the frequency of N multiples of
Fref can be obtained depending on the selection of delay
cells and capacitors.
N
NT /NT /
3. Frequency Multiplier with Edge Detector
The frequency multiplier comprises an edge detector
and a logic circuit. The schematic of the edge detector is
shown in Fig. 4(a). The edge detector makes one pulse
signal by sensing the rising edge of the clock signal that
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Young-Shig Choi, Hyuk-Hwan Choi, Tae-Ha Kwon KORUS’2005 832
is received from each delay cell of VCDL. It does not
require 50% of the duty ratio of input signal Fref. As
shown in Fig. 5, pulses generated in the edge detector are
synthesized in the frequency multiplier to make one
signal. Because the VCDL is exactly locked in one cycle,
the final clock cycle of the frequency multiplier is . If
the input frequency is , the output frequency of the DLL
with N selected delay cells becomes the .
NT/
f
Nf
VCDLout
Vc
Control m1
Control m2
Control mn
Fref
S1
S2 Sn
D
E
M
U
X
D
E
M
U
X
D
E
M
U
X
Control L1
Control L2
Control Ln
(a)
vi1 vi2
vo2 vo1
MOS c apa cit or
VCR
Vc
vo2
vo1 Next delay
cell input
Next delay
cell input
(b)
1.0 1.2 1.4 1.6 1.8 2.0
0.5
1.0
1.5
2.0
2.5
Delay Time (ns)
Vc (V)
(c)
Fig. 3. (a) Schematic diagram of VCDL (b) Schematic of the delay cell
(c) Delay time by Vc depending on a selected capacitor.
Si
Fi
Si
Fi
(a) (b)
Fig. 4. Edge detector of (a) Schematic (b) Operation waveform.
Frequency Multiplier
F1 F2 Fn
Fout
F1
F2
F3
F4
F5
F6
Fout
Fref
Fig. 5. Example of operation of the frequency multiplier.
IV. SIMULATION RESULTS
To verify the proposed DLL based clock synthesizer,
HSPICE simulation has been used with a 0.35um CMOS.
Fig. 6 is the simulation results when the input frequency
is 100MHz. Fig. 6(a) shows the simulation result of
VCDL input voltage. The DLL based clock synthesiszer
demonstrates fast locking compared to the conventional
PLL, approximately 5µs. Fig. 6(b) and 6(c) show the
simulation results of 300MHz and 1GHz clock signals,
respetively. The upper and lower signals are input and
output waveforms. Fig. 7 shows simulated jitter results of
the proposed DLL. Fig. 7(a) and 7(b) represent the peak-
to-peak jitter of the VCDL output and DLL output at
900MHz are 17ps and 70ps, respectively.
V. CONCLUSIONS
The proposed DLL based clock synthesizer can
generate multiple clocks like PLL. In addition, it has
little jitter accumulation and fast locking compared to
the conventional PLL. The locking time is
approximately 5
µ
s. The VCDL has very large delay
range by using delay buffers and MOS capacitors. In
the proposed DLL based clock synthesizer, the output
clocks from 300MHz to 1GHz with 100MHz input
signal can be generated. The inherent characteristics of
DLL also make the DLL based clock synthesizer
having low jitter output signal and fast locking. To
reduce locking time, charge pump current and the
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KORUS’2005 Young-Shig Choi, Hyuk-Hwan Choi, Tae-Ha Kwon 833
capacitance in LF should be increased and
decreased, respectively. On the contrary, charge pump
current and the capacitance in LF should be changed
opposite direction to generate low jitter output clocks.
This DLL based clock synthesizer has already
achieved fast locking and low jitter characeristics with
multiple clocks. Therfeore, it can be easily modified to
satisfy the specs what applications require by trading
off locking time and low jitter characteristics.
(a)
(b)
(c)
Fig. 6. Simulation waveforms of (a) Locking time of the proposed DLL
(b) 300MHz (c) 1GHz.
(a)
(b)
Fig. 7. Jitter of (a) VCDL output without frequency multiplier
(b) DLL output at the output frequency of 900MHz
.
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