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Dither Incorporated Deterministic Dynamic Element Matching for
High Resolution ADC Test Using Extremely Low Resolution DACs
Hanjun Jiang, Degang Chen and Randall L. Geiger
Department of Electrical and Computer Engineering
Iowa State University
Ames, IA 50011 USA
jhj@iastate.edu, djchen@iastate.edu and rlgeiger@iastate.edu
Abstract—A novel Dither Incorporated Deterministic
Dynamic Element Matching (DiDDEM) approach is
proposed. With this approach, the combined output of a
DDEM DAC and a dither DAC serves as the stimulus to an
ADC under test. Theoretical analysis shows that the test
performance with the DiDDEM DAC is equivalent to that of
a DAC with an ENOB (Effective Number Of Bits) equal to
the summation of the ENOB’s of the DDEM DAC and the
dither DAC plus log2p, where p is the DDEM iteration
number. The test performance using DiDDEM is also
validated by simulation results.
I. INTRODUCTION
With the increasing conversion resolution and rate,
testing ADC (Analog-to-Digital Convert) is increasingly
challenging. Testing high-resolution high-speed ADCs is
one of the most important tasks that test engineers need to
handle. Also ADC is a critical component of the SOC’s
(System-On-a-Chip). Built-In-Self-Test (BIST) is the
most promising solution to test those deeply embedded
ADCs cost effectively. It is significant to develop
methods for BIST of embedded ADCs with affordable
hardware and computation payload.
It is the common belief that for accurate ADC test highly
accurate test signals are required. Usually it is
recommended that the stimulus to the DUT should have
accuracy 10 times or 3 bits better than ADC’s. The
consequence of this conventional idea is the ubiquitous
use of high-accuracy test equipment. It also follows that
test methods developed for the product test environments
cannot be used for BIST situations, since it is impractical
to duplicate the high-accuracy test equipments on chip
using limited die area.
To provide cost effective test approaches for ADC
production test and BIST, alternative approaches that
override this belief have been proposed. With these
approaches the requirements on the test stimulus are
relaxed by orders of magnitudes. The DDEM
(Deterministic Dynamic Element Matching) approach is
one candidate that can be applied on low
resolution/accuracy DACs to generate evenly spaced
signals for high-resolution ADC test. [2-4]
The DEM technique is widely used in
-
modulators to
improve the dynamic performance. Similar to the DEM
technique, dither is also a technique widely used in data
converter applications to improve the output performance
statistically [1]. In this work, we adopt the dither
technique in the test application, as the case of DDEM for
test purpose.
In this paper, a new approach will be proposed to provide
a highly cost effective stimulus generator for high
resolution ADC test based on both the DDEM and dither
techniques. It is capable of both production test and BIST.
With this new approach, the requirement on stimulus
generator will be relaxed further compared to the DDEM
approach. The approach will be explained, theoretically
proved and finally validated by simulation results.
This paper is organized as follows. An explanation of
histogram based ADC test is given in Section II, and a
brief review of the DDEM approach is given in Section
III. In section IV, the new approach is introduced. The
mathematical proof of this approach will be provided in
Section V, followed by simulation results in Section VI.
II. HISTOGRAM BASED ADC TEST
In this paper, we focus on the ADC static performance
test. The ADC static performance is totally determined by
the transition voltages. For an n-bit ADC, we denote Tk as
the transition voltage between code k-1 and k. Then code
width Wk for code k can be defined as Tk+1-Tk. The DNL
(Differential Non-Linear error) for code k can be defined
as the difference between the actual code width Wk and
the average code width W0. The average code width is
also known as the LSB (Least Significant Bit) step. The
INL (Integral Non-Linear error) for code k is defined as
the difference between the actual transition voltage Tk
and the ideal position for Tk. Since the DNL[k] curve can
be obtained by differentiating the INL[k] curve, we only
discuss the INL test in the following sections.
Histogram based test is usually used to test ADC INL[k]
curve. Among various types of histogram based test, the
linear ramp based test is the easiest and most commonly
adopted. As stated in [4], what is sufficient in linear ramp
based test is just a signal with uniform voltage
distribution. To achieve a uniform voltage distribution
without caring the time-located linearity is drastically
easier than to achieve a high-accuracy linear ramp.
With stimulus having ideal uniform voltage spacing, the
ADC output code bin height H[k] for each code k will be
proportional to the code width Wk. Assume the ADC test
range is [Vmin, Vmax]. The stimulus output range should
cover the DAC test range. For an arbitrary voltage Vt, let
h(Vt) represent the number of stimulus samples that fall
into [Vsmin, Vt]. It is clear that H[k] is determined by h(Tk)
and h(Tk+1). Based on that, we can evaluate the ADC test
accuracy using a given stimulus by estimating how linear
h(Vt) is with respective to Vt. For the new proposed
stimulus generator, we will validate the performance by
estimating the nonlinearity of h(Vt).
III. DDEM DAC
Before evaluating of the new approach, the DDEM DAC
will be briefly reviewed in this section. The DDEM DAC
is proposed for histogram based ADC test [2-4], where
the DDEM approach is applied to a thermometer coded
current steering DAC to generate the stimulus to the ADC.
An n-bit DDEM DAC has totally 2n current sources.
Let n
N2=. Use
(
)
Nji j,...,1= to represent the jth current
element out of the total N elements. Let p denote the
DDEM iteration number. p represents the number of
samples to be generated for each DAC input word k.
Define pNq /=. The following Cyclic DDEM switching
scheme is applied to the current elements:
1. All current sources are arranged conceptually along a
circle to visualize the wrapping effect, p index
elements that are pNq /= distanced are selected.
2. For each input code k, the DAC generates p samples of
output. Each sample is obtained by switching k current
sources consecutively starting from one of the p index
elements. The dth ( pd ≤≤1) sample is obtained by
switching k current sources starting from 1)1( +− qd
iin
the clock-wise direction.
3. The output analog signal is obtained by forcing the
selected k current elements to drive a resistor RC.
According to theoretical analysis, if a DAC has an
effective number of bits (ENOB) of nENOB, then with the
DDEM approach, the DAC can achieve test performance
comparable to an ideal DAC with nENOB+log2p bits
resolution. The DDEM approach uses a low
resolution/lineaerity DAC to test high resolution ADCs.
The DAC element mismatch is highly tolerated, and
hence minimum sized current elements can be used. The
control logic to implement this approach is simple and
easy. The total die size and design effort to implement a
DDEM DAC will thereby be greatly reduced. The DDEM
approach is capable of both production test and BIST test.
The DDEM approach greatly relaxes the stimulus
requirement for ADC test. In this work, a new approach
based on DDEM will be proposed. With this new
approach, the stimulus requirement can be further
reduced.
IV. DITHER INCORPORATED DDEM
Here, a new approach for ADC test is proposed which
incorporates the DDEM technique with dither. One low-
resolution DDEM DAC and one low-resolution dither
DAC are combined to provide the stimulus to the ADC
under test. We term the new approach as the Dither
Incorporated DDEM (DiDDEM).
DDEM
DAC
k1
s
Dither
DAC
k2
VDDEM[k1,s]
VDither[k2]
VDD[k1,s,k2]DUT
(ADC)
DDEM
DAC
k1
s
Dither
DAC
k2
VDDEM[k1,s]
VDither[k2]
VDD[k1,s,k2]DUT
(ADC)
Figure 1. DiDDEM DAC for ADC test
Assume we have one DDEM DAC with n1-bit resolution
and one dither DAC with n2-bit resolution. The DDEM
iteration number is p. As we know that the DDEM DAC
has two control words, one is the input code (denoted as
k1), and the other is the DDEM iteration code (denoted as
d). We denote the output from the DDEM DAC as
V1[k1,d] (1k1N1 & 1dp, N1=2n1). Denote the dither
input code as k2, and the output from the dither DAC as
V2[k2] (1k2N2, N2=2n2). The dither DAC’s output is
attenuated by a factor and then added to the DDEM
DAC’s output. If the maximum outputs of the two DACs
are V1m and V2m respectively, nominally is given by
m
m
V
V
p2
1
1
=
α
(1)
The summation output serves as the stimulus to the ADC
under test. It is clear that the final DAC output has 3
control words: k1,d and k2. We denote the combined
output as V[k1,d,k2]. Without repeating the control words,
the DiDDEM DAC can have N1*p*N2 output samples.
V. TEST PERFORMANCE EVALUATION
We use the output of the DiDDEM DAC as the stimulus
to the ADC. The test performance will determined by the
distribution of V[k1,d,k2] (1k1N1,1dp&1k2N2). In
the following part of this section, the test error will be
evaluated by estimating )( t
Ve defined in (1) for any
voltage Vt in [Vmin, Vmax].
A. Voltage Distribution of DDEM DAC
The DDEM DAC has N1 current elements: ij(1jN1)
Let ),..,1( 1
Njii jjN ==
+, then virtually we have 2N1
current elements 111 2121 ,...,,,...,, NNN iiiii +
Let 0]0[
1
=
Vand )2,...,1(][ 11
1
11
1NkiRkV
k
j
jC =⋅=
=
, where RC is
the output resistance of the DDEM DAC. Note that the
first half of the sequence is the output voltage sequence of
a regular n1-bit DAC. Let ][ 111 NVV m
=
.m
V1is the
maximum output of the DDEM DAC. Define
111 /NVLSB m
=
Now define INL and DNL for the DDEM DAC. Let
(
)
)2,...,0(/][][ 111111111 NkLSBLSBkkVkINL =⋅−=
and
(
)
)2,...,1(/]1[][][ 1111111111 NkLSBLSBkVkVkDNL =−−−=
With DDEM cyclic switching sequence, the DAC outputs
p ramps. Let q=N/p. The dth (1dp) ramp is given by
),...,1( 1
)1(
)1(1
NkiR dqk
dqj
jC =⋅ −+
−+=
, which is equivalent to
{
}
{
}
111111
)(
11:)]1([)]1([][ NkdqVdqkVkV d≤≤−−−+=
For any t
V less than m
V1, let )(
)( t
dVg denote the number
of elements in
{
}
][ 1
)(
1kV d that are not larger than t
V.
{
}
111
)(
1
1
)(
1
)( 1,][:][)( NkVkVkVVg t
dd
t
d≤≤≤= .
Let
(
)
(
)
mtt VVNfloorVg 11
)0( /⋅=
We have the follow approximation for )(
)( t
dVg
[
]
p)d(1 ≤≤
−
+≈ 1
)0(
)(
1
)0()( )(
)()( LSB
VgVV
VgVg t
d
t
tt
d
p)d(1 ≤≤−+−≈
=
)(
111
1
)0(
1
)]1([
t
Vg
k
tdqkDNL
LSB
V
It is clear that the number of DDEM DAC output samples
that are less than t
V is given by
= ==
−+−≈= p
d
Vg
k
t
p
d
t
d
t
tdqkDNL
LSB
V
pVgVg
1
)(
111
1
1
)(
)0(
1
)]1([)()(
If )&,0,0()(
)0( ZmtptqmmtqVg t∈<≤≤<+⋅= , finally
we have
= =
−+−≈ p
d
m
k
t
tdqkDNL
LSB
V
pVg
1 1 11
11
)]1([)( (2)
B. Test error with dither incorporated DDEM DAC
Now look at the output of the dither incorporated DDEM
DAC. We denote the n2-bit dither DAC output sequence
as
{
}
2222 1:][ NkkV
≤
≤
. Let ][ 222 NVV m=.We can also
define INL[k] and DNL[k] for the dither DAC.
The DiDDEM DAC output is expressed as
][],[],,[ 221121 kVdkVkdkV
α
+
=
The maximum output of the combined DAC is
mmm VVV 21
α
+
=
For any t
V less than m
V, let )( t
Vh denote the number of
output samples that are not larger than t
V.
{
}
tt VkdkVkdkVVh ≤= ],,[:],,[)( 2121
By definition,
( )
=
−= 2
2122 ][)( N
k
tt kVVgVh
α
Substitute (2) into it, we have
= = ==
= = =
−+−−=
−+−
−
=
2
2
2
1
2
2
2
2
2
1
1 1 1 11
11
22
1
2
1 1 1 11
1
22
)]1([
][
)]1([
][
)(
N
k
p
d
m
k
N
k
t
N
k
p
d
m
k
t
t
k
k
dqkDNL
LSB
kV
p
LSB
V
pN
dqkDNL
LSB
kVV
pVh
α
α
α
(3)
where 2
k
mis given by
(
)
22
][ 22
)0( kkt mtqkVVg +⋅=−
α
.
There are 3 items in (3). The first item is the linear part
and the second is a fixed value for any Vt. The third item
contains the nonlinearity with respective to Vt. Let
(
)
te Vh
denote this nonlinearity and change the summation order
= = =
−+−= p
d
N
k
m
k
te
k
dqkDNLVh
1 1 1 11
2
2
2
1
)]1([)( (4)
Let
= =
−+= 2
2
2
1
1 1 11 )]1([)( N
k
m
k
ted
k
dqkDNLVh (5)
If the dither DAC is ideal, then 2
k
mwill be values taken
from 1 to q when k2 varies. Each number from 1 to q will
be taken by q
N
r2
0= times. Then
= =
−+= q
m
m
k
ted dqkDNLrVh
1 1 110
1
)]1([)( (6.a)
With the non-ideal dither DAC, the 0
r in (6.a) should be
replaced by ][
0mrr e
+, where
+−=
≈qmN
qNmk
ekDNLmr
/
1/)1( 22
2
22
][][
= =+−=
−+
+≈ q
m
m
k
qmN
qNmk
ted dqkDNLkDNLrVh
1 1 11
/
1/)1( 220
1
2
22
)]1([][)( (6.b)
If the standard deviations of the DDEM DAC and dither
DAC DNL[k]’s are 1 and 2 respectively. The variance
of )( ted Vh is given by
2
)1(
)( 2
22
2
1
2
1
1
2
2
2
σσ
σσ
Nq
q
N
kVVar
q
k
ted +
=⋅
≈
=
The variance for )( te Vh is
2
)()( 2
22
2
11
σσ
NN
VVarpVVar tedte ≈⋅= (7)
The normalized )( te Vh standard deviation is given by
(
)
(
)
(
)
21221121 /2/2/2/)( pNNNNpNNVVar tee
σσσ
⋅≈=
Also usually we have
11 2/
1
σσ
N
k
INL =and 22 2/2
2
σσ
N
k
INL =.
If
1
1
21 log
k
INL
ENOB N
n
σ
=and
2
2
22 log
k
INL
ENOB N
n
σ
=
Then 5.0log
1
log 2122 −++= ENOBENOB
e
nnp
σ
.
We may ignore this -0.5 and the equivalent test
performance of the DiDDEM DAC will be equivalent to
that of a DAC with ENOB equal to
212
log
~
ENOBENOBENOB nnpn ++≈ (8)
In reality, when other non-idealities are included, the test
performance might be a little bit lower than given in (8).
VI. SIMULATION RESULTS
The test performance using the proposed DiDDEM DAC
is verified by simulation. In the simulation, the DDEM
DAC is a 9-bit DAC and the dither DAC is a 6-bit DAC,
and both have the same current element distribution with
normalized standard deviation equal to 0.1, which means
the mismatch can be up to about 30% if counting the 3
range. The DDEM iteration number p is 64. The
simulated ADCs under test are 14-bit ADCs. The
estimated INL[k] and INL with the DiDDEM DAC as test
stimulus are compared to true INL[k] and INL. The
differences are the test errors using the DiDDEM DAC.
Figure 2. ADC true & est. INL[k] and estimation error
Figure 2 depicts the ADC true INL[k], estimated INL[k]
curves and estimation error from a single simulation. The
simulated DDEM DAC has an INL of 1.89 LSB at 9 bits
level, and the dither DAC has an INL of 1.16 LSB at 6
bits level, so nENOB1+nENOB2
12 bits. According to (8), the
expected test performance is nENOB1+nENOB2+log2p
18
bits. In simulation, the ADC true INL is 3.15 LSB, and
the estimated INL is 3.25 LSB. INL estimation error is
only 0.1 LSB. The maximum INL[k] estimation error is
0.3 LSB at 14-bit level. So the test performance is at
about 16 bits level. The actual achieved test performance
is comparable to that predicated by (8).
To verify the robustness of the DiDDEM approach, 100
DiDDEM DACs are simulated to test 100 ADCs
respectively. The simulation setting is the same as
previous. Figure 3 shows the estimated INL versus the
true INL curve for these 100 DAC-ADC pairs. The
maximum INL estimation error (estimated INL – true
INL) is 0.42LSB and the minimum error is –0.15LSB.
First, the errors are quite small, which means the
DiDDEM approach is robust. Secondly, the lower bound
(-0.15) is adequately small, which means there is almost
no risk of underestimating ADC’s INL with the DiDDEM
DAC, This merit is critical for real test, since it can
guarantee no “bad” parts are delivered as “good” parts.
Figure 3. Estimated INL vs true INL for 100 ADCs
VII. CONCLUSION
A new dither incorporated deterministic dynamic element
matching (DiDDEM) approach has been proposed for
high resolution ADC test using extremely low resolution
DACs. With this approach, the outputs of a DDEM DAC
and a dither DAC are combined and serve as the stimulus
to the ADC under test. Theoretical analysis shows that the
test performance of a DiDDEM DAC is equivalent to that
of a linear DAC with ENOB equal to the summation of
the DDEM DAC ENOB and dither DAC ENOB plus
log2p, where p is the DDEM iteration number. Simulation
results show that the actual test performance is
comparable to the theoretical prediction. The robustness
and reliability of this approach are also verified by
simulation. The future work will include verifying this
new approach with experimental results and
implementing a DiDDEM DAC on-chip for BIST
environment validation.
REFERENCES
[1] M. F. Wagdy, “Effect of various dither forms on quantization
errors of ideal A/D converters”, IEEE Transactions on
Instrumentation and Measurement, Vol. 38, No. 4, August 1989
[2] B. Olleta, L. Juffer, D. Chen an R. L. Geiger, “A deterministic
dynamic element matching approach to ADC testing”, Proceedings
of the 2003 ISCAS, pp. V-533-6, vol. 5, 25-28 May 2003
[3] B. Olleta, H. Jiang, D. Chen and R. L. Geiger, “Test high
resolution ADCs using deterministic dynamic element matching”,
Proceedings of the 2004 ISCAS, pp. I-920-3, vol. 1, 23-26 May
2004
[4] H. Jiang, B. Olleta, D. Chen and R. L. Geiger, “Parameter
optimization of deterministic dynamic element matching DACs for
accurate and cost-effective ADC testing”, Proceedings of the 2004
ISCAS, pp. I-924-7, vol. 1, 23-26 May 2004
