On-chip antenna design for UHF RFID

Abstract

An on-chip antenna suitable for radio frequency identification at UHF band is presented. It is integrated with an EPC Class 1 Generation 2 compatible tag in SMIC 0.18 m standard CMOS process. The tag achieves a 1 cm communication distance with 1 W reader output power.

Full text

On-chip antenna design for UHF RFID
J. Xi, N. Yan, W. Che, X. Wang, H. Jian and H. Min
An on-chip antenna suitable for radio frequency identification at UHF
band is presented. It is integrated with an EPC Class 1 Generation 2
compatible tag in SMIC 0.18 mm standard CMOS process. The tag
achieves a 1 cm communication distance with 1 W reader output
power.
Introduction: Cost and size reduction of radio frequency identification
(RFID) tags is one of the keys to the wide adoption of RFID systems.
A revolutionary way for low-cost small-size tag implementation is to
use the on-chip antenna (OCA). Integrating an OCA with RFID tags
has significant advantages not only in saving a major portion of the
tag assembly cost but also in enhancing system reliability, and allows
for applying small tags to various applications, especially item-level
tagging.
There have been several publications on RFID tags with an OCA
embedded [1–4]. However, many existing OCA implementations
need extra procedures in addition to the standard fabrication process,
such as gold plating [2] and thick oxide [3]. Also their communication
distances are short, e.g. 4 mm [4]. In addition, there is very little descrip-
tion of OCA design methodology, which is necessary for performance
optimisation. In this Letter, a method of OCA design is presented. It
is successfully demonstrated by one fully-integrated EPC Class 1
Generation 2 (C1G2) compatible tag fabricated in SMIC 0.18 mm
standard CMOS process.
Tag model: In the tag model shown in Fig. 1, R
L
and C
L
model the input
impedance of the tag circuit at the operation frequency. For the tag pre-
sented, they are 5.8 kV and 465.2 fF, respectively, at 0.9 GHz. An OCA
at UHF band can be regarded as an electrically small loop antenna
immersed in a sandwich-type dielectric. In Fig. 1, all elements excluding
R
L
and C
L
form a model of one single-ended OCA. L
s
and R
s
represent
the series inductance and conductor loss, respectively. C
s
represents the
parasitic capacitive coupling between the two terminals of the OCA. R
p
and C
p
represent the substrate loss and the capacitive coupling between
the OCA and the substrate, respectively. R
p
and C
p
are particular para-
sitics, stemming from stacked dielectric layers in CMOS process.
These elements can be extracted from results of simulation or measure-
ment. An induced voltage V
ind
is generated when the OCA is exposed to
an oscillating magnetic field, and it can be calculated by Lenz law.
R
s
L
s
V
ind
C
L
C
s
C
p
R
L
+
–
V
L
R
p
Fig. 1 Tag model
OCA design: An optimised OCA should deliver as much voltage and
power as possible to a given tag circuit at the operation frequency.
Owing to the parallel-connection of R
L
and C
L
, the voltage across the
tag circuit V
L
and the power into the tag circuit maximise at the same
time. By studying the transfer function from V
ind
to V
L
and taking its
first order-derivatives with respect to L
s
and R
s
, it can be found that
when R
s
is kept as small as possible and L
s
satisfies (1), the OCA can
deliver a maximum V
L
expressed by (2). It should be mentioned that
the maximum power transfer theorem which requires a conjugate match-
ing cannot be applied here since the OCA works as a source.
L
s
¼
C
t
v
2
C
2
t
þ 1=R
2
t
ð1Þ
V
L
¼
ffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1 þ Q
2
t
p
1 þ Q
t
=Q
s
V
ind
ð2Þ
where
C
t
¼ C
s
þ C
p
þ C
L
; R
t
¼ R
p
kR
L
; Q
s
¼
v
L
s
=R
s
; Q
t
¼
v
C
t
R
t
Equation (1) implies that the OCA needs to be resonated with the tag
circuit in order to maximise V
L
. L
s
is the key element from the perspec-
tive of OCA design, since the OCA geometry is easy to be derived
according to it with the Greenhouse method [5]. However, L
s
cannot
be solved directly by (1), because R
t
and C
t
contain the OCA parasitics
which are unknown at the beginning of design. The key of predicting L
s
lies at the estimation of the OCA parasitics. An optimised OCA can be
found as follows. First, substituting C
L
and R
L
for C
t
and R
t
, respectively,
in (1) leads to an overestimated L
s
as a start. Secondly, given L
s
, possible
OCA geometries can be derived and the OCA parasitics can be estimated
by simulation in a full wave simulator accordingly. Thirdly, to update the
values of C
t
and R
t
, then to check whether or not the current L
s
satisfies (1).
If not, to reduce L
s
and repeat the above procedure. This search process can
be automated by programming.
With the help of (2), the influences of the two main loss mechanisms
of the OCA, i.e. metal loss and substrate loss, upon its power capturing
capability can be learned intuitively. On the one hand, V
L
increases
monotonously as Q
s
increases. However, Q
s
of the OCA at UHF band
is limited by its DC loss, and is small compared with its off-chip
counterpart due to the limited conductivity and cross-section of metals
in the standard CMOS process. On the other hand, V
L
also increases
monotonously as Q
t
increases. This is bad news since R
p
decreases Q
t
dramatically, and good news regarding C
s
and C
p
because they increase
Q
t
to some extent. For low-power tag designs in the standard CMOS
process, the total influences of R
p
, C
s
and C
p
make a smaller Q
t
,
which further degrades the OCA performance.
It is worth mentioning the differences between the design of the OCA
at UHF band and that of on-chip spiral inductors. First, the optimum
operation frequency of the OCA at UHF band is slightly lower than
its self-resonant frequency (SRF), while an on-chip spiral inductor
works better in the frequency band where its equivalent inductance
keeps stable and its equivalent quality factor maximises, normally
fairly lower than its SRF. Secondly, the optimisation of an on-chip
spiral inductor focuses on the improvement of its equivalent quality
factor. However, for the OCA at UHF band, a maximised equivalent
quality factor does not guarantee a maximised V
L
. These differences
are rooted in the appearance of V
ind
, which requires insight into the
OCA instead of regarding it as a black box or a macro model.
Results: As shown in Fig. 2, one prototyping OCA is integrated with an
EPC C1G2 compatible tag in SMIC 0.18 mm standard CMOS process.
The single-layer four-turn OCA is in a 1  1 mm square form with
11 mm wire width and 2 mm wire space. The tag presented includes
an RF/analogue front end, digital base band and 640-bit EEPROM
memory.
1 mm
1 mm
Fig. 2 Tag microphotograph
ELECTRONICS LETTERS 1st January 2009 Vol. 45 No. 1

Estimated parasitics of the presented OCA are compared with the
measurement as shown in Fig. 3. R
p
estimated at 0.9 GHz is 1.3 kV,
and agrees well with the measured. C
p
estimated at 0.9 GHz is 420.5
fF, about 10% smaller than the measured, mainly due to the intrinsic
narrow band feature of the OCA model. Besides, C
s
is frequency-
independent and estimated to be 12.9 fF. The agreement between esti-
mation and measurement demonstrates that the estimated OCA parasitics
are reliable and the parasitic-aware OCA optimisation is promising.
Substituting the above estimated parasitics into (1), an optimised L
s
at
0.9 GHz needs to be 33.7 nH, which is well approached by the measured
one, 36.1 nH. The prototyping fully-integrated UHF RFID tag is tested
with one near-field reader antenna which is a 1  1 cm single-turn
square loop antenna printed on an FR4 board. The reader antenna is
matched to 50 with 1 W reader power amplifier output. Test results
show that the communication distance of the tag presented is up to
1 cm. The reader command transmitted and the tag response received
are shown in Fig. 4.
40
30
R
p
, kW
20
10
0
10
–1
10
0
frequency, GHz
10
1
200
300
400
C
p
estimated
C
p
measured
R
p
measured
R
p
estimated
C
p
, fF
500
600
Fig. 3 Measured and estimated values of R
p
and C
p
reader
command
tag
response
details of tag
response
Fig. 4 Measured reader command and tag response
Conclusion: An OCA is designed by properly incorporating the OCA
parasitics into a tag model and thoroughly analysing the condition
under which the maximum voltage and power transfer occur. It is inte-
grated with one EPC C1G2 compatible tag in SMIC 0.18 mm standard
CMOS process. The tag achieves a 1 cm communication distance with 1
W reader output power.
# The Institution of Engineering and Technology 2009
9 September 2008
Electronics Letters online no: 20092033
doi: 10.1049/el:20092033
J. Xi, N. Yan, W. Che, X. Wang, H. Jian and H. Min (State Key
Laboratory of ASIC & Systems, Department of Microelectronics,
Fudan University, Shanghai 201203, People’s Republic of China)
E-mail: jtxi@fudan.edu.cn
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