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Analog Baseband Channel for
GSM/UMTS/WLAN/Bluetooth Reconfigurable
Multistandard Terminals
Nicola Ghittori
1
, Andrea Vigna
1
, Piero Malcovati
2
1
Department of Electronics,
2
Department of Electrical Engineering
University of Pavia, Pavia, Italy
Email: {nicola.ghittori,andrea.vigna,piero.malcovati }@unipv.it
Stefano D’Amico, Andrea Baschirotto
Department of Innovation Engineering
University of Lecce, Lecce, Italy
Email: {stefano.damico,andrea.baschirotto}@unile.it
Abstract— This paper presents a reconfigurable analog base-
band channel for multistandard receivers. The circuit, consisting
of two variable gain amplifiers and a low-pass filter, fulfills
the requirements of GSM, WCDMA (UMTS), WLAN (IEEE
802.11a/b/g), and Bluetooth. The gain, bandwidth and power
consumption of the circuit are changed through a digital control
word depending on the selected standard. Simulation results,
including all of the tests prescribed by the different standards,
confirm the validity of the proposed solution. The in-band
IIP3 evaluated with maximum gain (68dB/39dB) is 5dBm/1dBm
for UMTS/WLAN respectively, while the power consumption is
51.7mW/55mW in the two cases.
I. I
The growing economic and social impact of mobile telecom-
munication devices, together with the evolution of protocols
and interoperability requirements among different standards
for voice and data, is currently driving worldwide research
towards the implementation of fully-integrated multistandard
transceivers [1]. The most advanced fully integrated solutions
in the scientific literature and on the market do not cover
the four most important telecommunication standards, namely
GSM, WCDMA, Bluetooth, and wireless LANs (WLANs). In
order to allow the user to switch seamlessly among different
standards, achieving so-called “global roaming“, for both voice
and data applications, all these standards have to be supported
by an integrated transceiver. GSM and WCDMA (UMTS)
are the dominant standards for voice and mixed voice/data
mobile services, while WLANs based on the IEEE 802.11a/b/g
protocols are the most important standards for high data
rate wireless internet access. Finally, Bluetooth enables the
terminal to be wirelessly connected with other devices at
low data rates over a short distance. Implementation of an
integrated multistandard transceiver that is competitive with
solutions based on separate devices for the different standards
must take various points into account. First of all, both silicon
area and static power consumption must be minimized, thus
requiring the maximum possible hardware sharing among the
transceivers for the different standards. In order to reach this
goal, one must define which standards can be used at the
same time. We assumed that only two standards among the
supported ones can operate concurrently at a given time (e.g
WLAN with Bluetooth or voice with Bluetooth or voice with
WLAN) and that no handover is supported for Bluetooth.
From these considerations, we defined the receiver architec-
ture shown in Fig. 1. This paper presents the analog baseband
channel of such a receiver (dashed box in Fig. 1).
The challenges in designing the analog baseband section
of a reconfigurable receivers are mainly related to the very
different specifications of the different standards. In particular,
bandwidth, gain, noise, resolution and linearity requirements
are quite different from one standard to another. One “brute
force” approach to design could be to select the most stringent
requirement for each parameter, thus deriving a set of spec-
ifications valid for all standards. This approach, however, is
definitely not efficient, especially in terms of power consump-
tion. A more reasonable approach, which has been adopted
for the design of the circuits reported in this paper, is to adapt
the circuit performance, and hence the power consumption,
to the standard considered. This adaptation of the analog
devices is performed through a digital control which either
adjusts the biasing conditions of the active building blocks
(e.g. operational amplifiers) or turns on or off entire stages.
II. A B C A
The input spectrum of the receiver baseband block typ-
ically includes adjacent channels, in-band and out-of-band
blockers, that can dominate (by up to 40-60dB) the signal
to be processed. For this reason analog baseband blocks are
required to exhibit not only a target in-band dynamic range,
but excellent linearity for out-of-band signals. This is because
a non-linear behavior with out-of-band-signals would result
in an intermodulation whose product components would fall
in the signal band, corrupting the signal quality. Usually,
the analog baseband section of a receiver is composed of
a series of Voltage Gain Amplifiers (VGA) and Low-Pass
Filters (LPF). The VGAs increase signal amplitude, while the
LPF reduces the power of the out-of-band blockers in order
to increase the swing available for the useful signal. This
functionality is shown in Fig. 2.
The design of the receiver baseband channel implies a trade-
off between LPF selectivity (higher filter selectivity would
4301
ISCAS 20060-7803-9390-2/06/$20.00 ©2006 IEEE
Phone
BP-filter
WLAN
BP-filter
LNA
IQ
Demodulator
LNA
IQ
Demodulator
VGA
LP-filter
VGA
A/D
Phone/Bluetooth RX
WLAN/Bluetooth RX
LP-filter
VGA
A/D
Digital Processor
RF
Analog Baseband
Digital Baseband
Fig. 1. Reconfigurable multistandard receiver block diagram
g
ni
ws elba
lia
vA
VGA LPF VGA LPF VGA LPF VGA
Si
g
nal Blocker
Fig. 2. Receiver baseband analog signal processing
result in a lower number of stages) and circuit complexity. In
the design considered in this paper, we used a basic structure
with two VGAs and one LPF, as shown in Fig. 3. Due to
the reduced total required gain, in the WLAN/Bluetooth RX
channel the first VGA is not present.
-10/29 dB 0/35 dB
ADCVGA1 FILTER
VGA2
4 dB
+
-
Fig. 3. Block diagram of the developed analog baseband signal processing
channel
A. VGA1 Block
For the channel devoted to cellular application, the signal
is amplified with a gain up to 68dB. This is because the input
signal can be very low. The VGA1 (with a gain programmabil-
ity in the -10dB-29dB range) hence requires a reduced linear
range, while it must have a very low Input Referred Noise
(IRN ≈ 5nV/
√
Hz). This constraint was satisfied by using an
open loop approach implemented by a resistively-degenerated
and resistively-loaded differential stage, whose dc-gain is fixed
by a resistive ratio, as shown in Fig. 4.
In this scheme we used an open-loop architecture to reduce
the power consumption. For small input signals, a large gain
is required. This is achieved by minimizing the degeneration
resistance, which also reduces the IRN, as required by the
Fig. 4. Schematic diagram of the VGA1 block
low input signal amplitude. On the other hand, for large input
signals, a reduced gain is required. This is achieved by max-
imizing the degeneration resistance, which also increases the
linear range, as required by the large input signal amplitude.
B. Low-pass Filter Block
Several solutions for the filter are proposed in literature.
Active-RC structures exhibit excellent linearity at the cost of
high power consumption [2]. On the other hand, g
m
-C filters
feature a reduced linear range but with low power consumption
[3]. In this design we developed a novel structure that is the
merging of the two solutions above and is called “active-g
m
-
RC” [4]. Fig. 5 shows the 2
nd
order low-pass active-g
m
-RC
cell structure in its single-ended form.
The operational amplifier (op-amp) has a single-pole trans-
4302
R
1
C
1
v
i
R
2
v
o
A
DC
1+s·
Fig. 5. Active-g
m
-RC biquadratic cell
fer function (in the frequency range of interest) that is taken
into account in the transfer function synthesis. An Adjusting
Circuit controls the op-amp frequency response in order to
track the time constant of the passive components (R and C).
This has the effect to transform the dependence of the filter
frequency response on the transistor parameters into a depen-
dence only on the passive component values (R’s and C’s). The
active-g
m
-RC cell exhibits the following features, which make
it preferable for the implementation of the baseband filter of
portable multistandard terminals:
• low power consumption (a key issue for portable ter-
minals): one op-amp is used to synthesize a 2
nd
order
transfer function, halving the power consumption com-
pared with standard two-op-amps active-RC biquadratic
cells. In addition, the op-amp frequency response is used
to synthesize the filter frequency response. Thus the op-
amp unity-gain-bandwidth is comparable with the filter
pole. This reduces its power consumption with respect to
other closed-loop structures (active-RC or MOSFET-C),
in which the op-amp unity-gain-bandwidth f
u
> 50 ÷100·
f
LP
is used, requiring a large power consumption;
• high-linearity: a very large linear range is achieved due
to its closed-loop structure. Moreover, out-of-band signals
are first filtered by the very linear R
1
-C
1
low-pass filter
at the input. This gives a very high out-of-band IP3 (3
rd
order intercept point), which is particularly interesting in
telecom systems where the higher amplitude of out-of-
band blockers requires a large out-of-band linearity;
• frequency response accuracy: the Adjusting Circuit makes
the op-amp frequency response independent of the passive
component values (R and C) spread, which is the only
spread to be compensated.
The 4
th
-order reconfigurable filter is realized by the cascade
of two active-g
m
-RC biquadratic cells. The filter can be re-
configured to adjust the bandwidth to the selected standard by
two bits that control the values of the resistors (this keeps the
overall noise constant). In addition, in the lower bandwidth
cases the power consumption is reduced by controlling the
input stage device sizes and their current level. For all the
standards, the capacitors are grounded in order to be seen by
the common-mode signal as well. Otherwise, a high frequency
resonance for the common-mode signals would be present.
This implies that the capacitance dominates the overall filter
area. However, sharing the capacitors for all the standards
configurations minimizes the area occupation. The capacitors
values are finally adjusted by the tuning circuit to compensate
for technology variations. A key feature of this structure is the
limited power consumption due to the use of low f
u
op-amps.
In fact, the f
u
/ f
LP
ratio is less than two.
The full filter design has been optimized in order to min-
imize the power consumption using a specifically developed
automatic design toolbox, which for a given set of constraints
(noise, linearity, transfer function) and device models, directly
defines all the device sizes in order to minimize power.
C. VGA2 Block
The amplitude of the input signal of the second VGA is very
large (after the previous amplification), so that for this stage
linearity is more important than noise performance. For this
reason we used a closed loop architecture, with two 17.5dB
gain stages and a 2.5dB gain resolution, as shown in Fig. 6.
The first stage is bypassed when a lower gain (0-17.5dB) is
needed. The block also implements an additional 1
st
order
LPF, on the second stage. Finally since the offset may be
significant at this stage, due to the large amplification of the
previous stages, it includes an offset compensation circuitry.
The block power consumption of 10mW is comparable with
state-of-the-art performance [5].
III. S R
The complete analog baseband channel has been simulated
at a fully-transistor level. Single-tone tests as well as two-tones
intermodulation tests have been performed to verify that the
block satisfies the linearity requirements for all the considered
standards.
Even if in the WLAN mode the number of active blocks is
reduced with respect to the other functional modes (the VGA1
is not present), this represents the most critical situation as the
maximum input signal frequency can be as high as 10MHz.
The reported simulation results refer to this case. Fig. 7 shows
the spectrum of a two-tones signal at the VGA2 output when
the receiver baseband chain is set with maximum gain (39dB
in the WLAN case). The power of each of the two tones at
the input is equal to -46dBm. The resulting IMD3 is equal to
105dB. Fig. 8 shows the output spectrum when a single tone is
applied at the input and the maximum gain is set. The power
of the third harmonic is under the fundamental tone of more
than 100dB.
Tab. I reports the overall simulated baseband channel fea-
tures for the two most critical settings (WLAN and UMTS).
The achieved linearity and noise performance satisfies the
requirements imposed by the standards for all the possible
gain settings. Moreover the block fulfills the typical receiver
tests of adjacent channel, in-band blockers and out-of-band
blockers.
IV. C
In this paper we presented a complete analog baseband
channel for a multistandard reconfigurable receiver supporting
4303
SEL
SEL
SEL
SEL
SEL
SEL
10-17.5 dB
0-17.5dB
V
in
V
out
+
-
S
1
S
5
R
in
R
1
R
2
V
in
V
ou
t
+
-
+
-
R
o
ff
V
o
ff
-
+
O
ff
se
t
c
o
m
p
e
n
sa
tion
Fig. 6. Schematic diagram of the VGA2 block
0 2 4 6 8 10 12 14 16
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
Frequency (MHz)
Power (dBm)
Fig. 7. Spectrum of the signal at the VGA2 output for a two-tones input
(WLAN setting, maximum gain)
TABLE I
S
Parameter Value
UMTS WLAN
Filter order 5
th
Power supply 2.5V
Power consumption 51.7mW 55mW
VGA1 19mW —
LPF 22.7mW 45mW
VGA2 10mW 10mW
Gain range −6dB÷68dB 4dB÷39dB
In-band IIP3 @ Max gain 5dBm 1dBm
Out-of-band IIP3 @ Max gain 30dBm 26dBm
IRN @ Min gain 9.6µV
RMS
51µV
RMS
GSM (with Edge), WCDMA (UMTS), WLAN and Blue-
tooth. The channel is composed by three functional blocks:
a first variable gain amplifier, a low-pass filter whose cut-
off frequency is digitally controlled and a last stage with
a programmable gain. In the UMTS mode the maximum
0 2 4 6 8 10
−160
−140
−120
−100
−80
−60
−40
−20
0
Frequency (MHz)
Power (dBm)
Fig. 8. Spectrum of the signal at the VGA2 output for a 1MHz single tone
input (WLAN setting, maximum gain)
achievable gain is 68dB, while in the WLAN mode it is
reduced to 39dB. Transistor level simulations of the developed
section validate the proposed design, as the main receiver tests
imposed by the standards are fulfilled with a maximum total
power consumption limited to 55mW.
R
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