1
Survey of Scan Chain Diagnosis
Yu Huang
Mentor Graphics Corporation, 300 Nickerson Rd., Marlborough, MA, 01752, USA
Tel: 1-508-303-5513, Fax: 1-508-480-0882, Email: Yu_Huang@mentor.com
Ruifeng Guo
Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR, 97070, USA
Tel: 1-503-685-0724, Fax: 1-503-685-1654, Email: Ruifeng_Guo@mentor.com
Wu-Tung Cheng
Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR, 97070, USA
Tel: 1-503-685-1078, Fax: 1-503-685-1654, Email: Wu-Tung_Cheng@mentor.com
James C.-M. Li
EE Building 2, Rm. 339, Department of Electrical Engineering, National Taiwan
University, 1, Sec. 4, Roosevelt Road, Taipei, Taiwan 106
Tel: 886-2-23635251 ext. 339, Fax: +886-2-23687664, Email: cmli@cc.ee.ntu.edu.tw
Abstract
In this paper, we reviewed various techniques of scan chain diagnosis. The reviewed paper and patents
are classified into different categories. The advantages and disadvantages of each category of technologies
are discussed. We also proposed several future research directions in this area.
Keywords: Scan Chain, Chain Diagnosis, Survey, Chain Pattern, Scan Pattern
1. Introduction
Scan-based testing has proven to be a cost-effective method to achieve good test coverage in digital
circuits. The Achilles’ heel for the application of scan-based testing is the integrity of the scan chains. The
amount of die area consumed by the scan elements, chain connections, and control circuitry may vary with
different designs. [KUN93] reported that scan elements and clocking may occupy nearly 30% of a chip area.
The percentage of scan chain defects could also vary with different designs. [GUO01] reported that 10-30%
defects cause scan chains to fail, while [YAN05] reported that chain failures account for almost 50% of
chip failures. Therefore, scan chain failure diagnosis becomes an important topic.
Typically each scan cell in a scan chain is given an index, as shown in Figure 1(a). The cell connected to scan-
output is numbered 0 and the cells in the chain are numbered incrementally from scan-output to scan-input
sequentially. A chain pattern is a pattern consisting of shift-in and shift-out without pulsing capture clocks. The
purpose of chain patterns is to test scan chain integrity. In some prior art, chain patterns are also called flush
patterns [STA01]. A scan pattern is a pattern consisting of shift-in, one or multiple capture clock cycles, and shift-
out. The purpose of scan patterns is to test system logic. So scan patterns and logic test patterns have the same
meaning and are used interchangeably. The scan cells between the scan chain input and the scan input terminal of a
scan cell are called the upstream cells of this scan cell, while the scan cells between the scan chain output and the
scan output terminal of a scan cell are called the downstream cells of this scan cell.
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The scan chain fault models include stuck-at faults (stuck-at-0/stuck-at-1), slow faults (slow-to-
rise/slow-to-fall/slow) and fast faults (fast-to-rise/fast-to-fall/fast) [GUO01]. Slow faults are caused by
setup-time violations while fast faults are caused by hold-time violations. Slow and fast faults are also
called timing faults. With a specific fault model, a scan chain defect can also be modeled with permanent
fault (the fault happens for all shift cycles) and intermittent fault (the fault only happens for a subset of
shift cycles) [HUA03a]. Identifying faulty chains and modeling chain defects by chain patterns are
illustrated by an example in Table 1. Suppose a scan chain with 12 scan cells is loaded with a chain pattern
001100110011, where the leftmost bit is loaded into cell 11 and the rightmost bit is loaded into cell 0.
Column 2 gives the unloaded faulty values for each type of permanent fault. Column 3 gives examples of
the unloaded faulty values for each type of intermittent fault. The underlined values show the difference
between the expected unloaded values and the observed values. By looking up this table, one can identify
the chain fault model to be used.
Chain patterns alone are sufficient to determine the fault type, but insufficient to pinpoint the index of the
failing flip-flop. This is the fundamental motivation for doing chain failure diagnosis, which is the process of
identifying one or multiple defective scan cell(s) in a scan chain or defective scan enable/clock signal(s). In this
paper, we will survey chain fault diagnosis techniques that have been investigated in the past. These techniques can
be classified into three categories: tester-based, hardware-based, and software-based diagnosis techniques.
Table 1: Scan Chain Fault Models and Their Effects
(Fault-Free Unloaded Values Are
001100110011)
Fault Models Unloaded Values
with One Permanent
Faults
Unloaded Values with
One Intermittent Fault
(Examples)
Slow-to-Rise 00100010001X 00110010001X
Slow-to-Fall 01110111011X 01110011011X
Slow 01100110011X 00100111011X
Fast-to-Rise X01110111011 X01110110011
Fast-to-Fall X00100010001 X00100110001
Fast X00110011001 X00100111001
Stuck-at-0 000000000000 001000010000
Stuck-at-1 111111111111 101111111011
2. Tester-based chain diagnosis
Tester-based diagnosis techniques use a tester to control scan chain shift operations and physical
failure analysis (PFA) equipment to observe defective responses at different locations to identify a failing
scan cell. These techniques normally provide very good diagnosis resolution. However, the major problems
of this technology are that (1) it requires expensive, time-consuming, and often destructive sample
preparation, and (2) it provides visibility through a small peephole only. Hence, you have to know where to
look with your PFA equipment.
In [DE95], De and Gunda
applied a chain pattern with alternative “0”s and “1”s and used electron beam
probing to detect the toggles. Binary search scheme was applied to detect the stuck-at fault at a cell where the
toggles start to disappear.
In [SON04], a diagnostic method was proposed based on Light Emission due to Off-State Leakage
Current (LEOSLC). Two chain patterns were applied. One chain pattern was with all “0”s and the other
was with all “1”s. Two emission images of a cell were compared for both chain patterns. If there was no
difference, a stuck-at fault could be on this cell or its upstream cells. This procedure was repeated until the
first cell that shows a different emission images for all “0”s and all “1”s chain patterns. A binary search
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could be applied to speed up the procedure. In [STE04], LEOSLC combined with Picosecond Imaging
Circuit Analysis technology can further enhance the efficiency and effectiveness of chain diagnosis.
If passing/failing of scan shift operating conditions, such as power supply, reference voltages, or clock
speed etc, can be identified, one can use passing (or failing) condition to shift-in a chain pattern and change
the test environment to the opposite condition for shift-out. The location where failures start to appear (or
disappear) is the defect location. [MOT03], [MOT06] and [KON05] belong to this category. In [MOT03],
they identify the passing/failing shift speed to diagnose slow faults. In [MOT06], by varying operating
parameters, one or more latches in the downstream of the fault location may be triggered to change state
from the stuck-at fault value. In [KON05], a Shmoo plot logging the result of the chain test results with
respect to voltage, frequency and temperature was performed to identify the passing and failing test
conditions.
In [HIR99], IDDQ testing was used for chain diagnosis. Taking the stuck-at-1 fault for example, if
“0111...” was shifted in, when the “0” was shifted to the cell with a stuck-at-l fault, the IDDQ current
would have an abnormally high value.
3. Hardware-based chain diagnosis
Hardware-based methods use some special scan chain and scan cell designs to facilitate the diagnosis
process. These techniques are effective in isolating scan chain defects. However, they typically require
special design of scan chains/scan cells with extra hardware overhead which may not be acceptable in
many realistic products. In addition, if the defects happen at the extra control hardware, diagnosis becomes
more complicated.
In [SCH92], it was proposed to connect the output of each scan cell to a scan cell (called partner shift
register) in another scan chain such that its value can be observed by the other scan chain in diagnostic
mode. For example, assume there is one stuck-at-0 at the output of cell 2 of chain 1 and chain1 has 4 cells.
After shifting in “1111”, chain 1 should have “1100”. Then the circuit was turned into “diagnostic mode”
and the data in chain 1 was transferred to its partner chain. Assuming the partner chain is a good chain,
“1100” is observed from this chain and it can be deduced that the defect must be in the middle of chain 1.
In [EDI95a], XOR gates were inserted between scan cells to enhance chain diagnosis. In case of
multiple faults, the proposed scheme will always identify the fault closest to the scan-output. There is a
trade-off between the number of XOR gates added and the diagnostic resolution. A dictionary-based chain
failure diagnosis technique based on this special scan chain design was discussed in [EDI95b]. In this
technique, a fault dictionary was created for each scan cell fault and the responses with XOR gates along
the scan chain were analyzed to identify the failing scan cell.
In [NAR97] and [NAR99], Narayanan and Das proposed to add simple circuitry to a scan flip-flop to
enable its scan-out port to be either set or reset. Based on this set/reset feature, the authors presented a
global strategy to take into account disparities in the defect probabilities and controllability/observability
attributes of flops in a scan chain. An algorithm to optimally modify a subset of the flops to maximize
diagnostic resolution is also described. One solution is that each adjacent pair of flip-flops consists of a
flip-flop whose scan output can be reset to a 0 and a flip-flop whose scan output can be set to a 1. Hence
any single stuck fault can be diagnosed down to a pair of flip-flops.
In [WU98], a special circuit was proposed to flip or set/reset scan cells to identify defective cells. After
shifting in a chain pattern, the state of each flip-flop can be inverted/set/reset. Based on the observed
unloading value, the faulty cell can be located.
In [SON00], a bidirectional scan chain architecture was proposed, where the scan fault can be
diagnosed by re-configuring scan chain to perform both forward and backward scan shift.
In [MOT05], an on-chip controller was applied for scan chain diagnosis. Each chain was divided into
multiple shorter sub-chains through multiplexers. The IOs of each sub-chain are controlled independently
by the controller. Each sub-chain can be observed by the MISR while other sub-chains are masked by the
controller. [TEK07] proposed to bypass portions of scan chain that have hold-time violations. The scan
chains were also partitioned into segments. When a hold-time violation was located on a scan chain
segment, the segment containing that flip-flop was bypassed and new test patterns were derived.
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4. Software-based chain diagnosis
Software-based techniques use algorithmic diagnosis procedures to identify failing scan cells. Compared with
the hardware-based methods, software-based techniques are more widely applied in industrial for general designs
due to the fact that no design modification is required. The software-based chain diagnosis techniques can be
classified into two categories: (1) using production scan patterns and (2) generate special chain diagnostic patterns.
4.1 Production scan pattern based chain diagnosis
In this category, the diagnosis methods can be further classified into 3 sub-classes: (1) simulation-
based, (2) probability-based and (3) dictionary-based.
In [STA01], fault injection and simulation were used to find the faulty scan cell. One fault was injected
at a cell for each run. Because all scan cells on a faulty chain were candidates, for a scan chain with a large
number of scan cells, this method could be time consuming. To speed up the diagnosis procedure, several
techniques were proposed.
In [GUO01], an algorithm was proposed to identify an upper bound (UB) and lower bound (LB) for a
faulty cell. Figure 1(a) illustrates an example to explain this algorithm. First the simulated loading values of
the faulty chain are changed to all “X”s. After pulsing the capture clock, assume on this faulty chain the
simulated captured values are ‘XX10
XXX0XX1X’. It means cells 8 and 4 will capture “0”s no matter what
values were really loaded to the faulty chain. Suppose the observed values on ATE are actually
‘1111
11001010’. Because the observed value at scan cell 8 is “1”, a stuck-at-1 fault must be in the
downstream of cell 8. So cell 8 is UB. Meanwhile, because the observed value at cell 4 matches the
simulated value, the stuck-at-1 fault must be in the upstream of cell 4. So, cell 4 is LB. The diagnosis
resolution is further improved by ranking the suspect cells within the bounded range. In [GUO02], the same
group of authors provided experimental results on applying the technique on industrial designs. More
details of this diagnosis method and its application to production test fallouts with several real case studies
were given in [GUO06].
In [KAO06], “jump simulation” was proposed to diagnose a single chain fault. For each failing pattern,
multiple simulations were performed to quickly search multiple segments of UB/LB of the fault. After the
range was finalized, a detailed simulator performed parallel pattern simulation for every fault in the final
range. Figure 1(b) demonstrates an example of “jump simulation”. Suppose there is a stuck-at-1 fault on a
scan chain and the current UB=27 and LB=20. The scan cells from UB to LB were evenly divided into
three parts and the boundary scan cells (22, 24, and 26) are chosen as jump bits. When searching for a new
UB, the fault is assumed upstream to the jump bit. All zeros downstream to the jump bit are changed to
ones; all zeros between the jump bit and UB are changed to ‘X’s. If a simulation mismatch occurs in the
second jump bit (24), it can be deduced that the stuck-at-1 fault is actually in the downstream to the jump
bit. The new UB is therefore moved to scan cell 23. The lower bound can be searched in a similar way.
In [HUA07a], a dynamic-learning based chain diagnosis methodology was proposed. This algorithm
was based on several learning rules. The rules analyzed the circuit, patterns, and mismatched bits and back-
traced the logic cones to figure out what cell(s) should be simulated in the next iteration. Therefore instead
of simulating every cell within a range, it may only need simulation of a few cells to find out suspects.
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Figure 2(a) illustrates one example to tighten LB. A fault is injected at current LB at cell 1. If a simulation
mismatch is on the gray cell of a good chain, it can be back-traced from the mismatched cell. Assume this
cell is driven by cells 4 and 3 on the faulty chain, it can be learnt that either scan cell 4 or 3 or both carried
wrong loading value(s) in the previous simulation. Therefore, the new LB is updated to scan cell 3. This
process can be iterated several times until the real defective cell is found.
In [HUA03b], diagnosis of intermittent hold-time faults was discussed. An algorithm based on X-
simulation was proposed, in which the intermittent loading/unloading behavior was modeled with ‘X’s. In
[HUA05a], case studies were given to illustrate the problems when using a fault model to diagnose real
chain defects. They proposed a fault model relaxation flow. Chain fault models will be adaptively selected
based on fault model relaxation rules and simulation results.
Chain diagnosis on devices with embedded compression techniques becomes a challenge. In
[HUA05b], a methodology that enables seamless reuse of the existing chain diagnosis algorithms with
compressed test data was proposed. In [HUA05c], an algorithm was proposed to locate the defects on the
scan enable tree for Mux-DFF scan architecture. The algorithm was based on simulation and post-
processing of diagnosis results by tracing scan enable tree. The algorithm was extended to diagnose clock
tree defect in [HUA06a]. For the LSSD scan architecture, an algorithm was proposed in [SAR92] to
diagnose scan clock defects.
The total number of failing bits that can be logged is restricted by the ATE fail buffer capacity and test
time, which will negatively impact the diagnosis resolution. In [HUA06b], three methods were proposed to
run chain diagnosis with limited failures: (1) static pattern reordering (2) dynamic pattern reordering and
(3) per-pin based diagnosis.
Sometimes, diagnosing real defects is challenging when scan chain defects and system logic defects
coexist on the same die, which was called compound defect [HUA07b]. In [HUA04b] discussed a special
compound defect such that one defect could impact both chain and system logic simultaneously. They
proposed to use per-shift-cycle simulation to identify the defect locations. In [HUA07b], a new algorithm
was described for diagnosing more general compound defects. It first partitions the failures to separate
failures caused by faulty chain(s) and faulty system logic. It then masks the faulty scan chain(s) to diagnose
system logic defects and masks the system logic defects to diagnose scan chain(s) defects. In [AHM06], a
real case study of yield enhancement was presented, which was due to successful diagnosis of scan chain
hold-time faults and system logic fault simultaneously.
Probability-based chain diagnosis algorithms primarily target intermittent chain faults. In [HUA03a], a
statistical diagnosis algorithm was proposed based on Bayes Theorem to calculate the probability of a cell
being faulty. In [HUA04a], an algorithm that incorporates signal probability calculation was proposed. It
injected one fault at a time to the faulty scan chain and searched the most matching candidate based on
probabilities.
In [GUO07a], a dictionary-based technique was proposed for scan chain failure diagnosis. Differential
signatures were stored in fault dictionaries to reduce the redundancy of fault signatures of adjacent scan cell
faults. Based on the differential signatures, the authors proposed a diagnosis technique that can diagnoses
single stuck-at fault, timing fault and some multiple stuck-at faults in a single scan chain.
4.2 Chain diagnostic pattern generation
When the failures of production scan patterns cannot provide good diagnosis resolution, special
diagnostic patterns are desired to achieve better diagnosis resolution.
In [KUN93] and [KUN94], a scan chain diagnosis algorithm was proposed such that it focuses on generating
test patterns for stuck-at fault diagnosis in a scan chain. Test patterns were created either to capture desired values
into target scan cells or to propagate the fault effect to good scan chains for failure observation. Similar methods
were utilized in [FOR01] [BRU06] and [AND05] to generate chain diagnostic patterns.
Yang and Huang proposed to use functional test patterns for scan chain failure diagnosis [YAN05].
This procedure selected patterns to randomize signal probability of scan cells. By comparing the observed
signal profile on a tester and the expected signal profile along a faulty scan chain, the failing scan cell
position can be identified. In [HSU06] and [TZE07ab], the authors proposed chain algorithms that include
two parts: (1) use diagnostic ATPG to get some scan patterns that do not use scan chain loading procedures
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so that the impacts of chain defects only come from chain unloading procedures, and (2) apply heuristics to
analyze the test failures and identify the defective cells. The heuristics include signal profiling, best-
alignment, delay insertion and image recovering etc.
Li proposed a single-excitation technique to generate diagnostic patterns [LI05ab]. The single excitation
patterns have only one sensitive bit that can be flipped by the fault. This technique converts the diagnosis problem
into a single stuck-at fault ATPG problem, which can be easily solved by existing tools. Figure 2(b) illustrates such
an example. Suppose that a stuck-at-zero chain fault exists. The single excitation pattern ‘00100’ is shifted into the
faulty chain to make the sensitive bit at cell 2. Hence the fault can be detected in the same way as a stuck-at-0 fault
in the combinational logic.
Crouch suggested to propagate the fault effect to as many POs and good scan chains as possible [CRO05]. He
also proposed to add some shift cycles between capture clocks, which can be helpful for diagnosing multiple chain
faults. In [SIN07], it was proposed to generate hold-time violation immune test stimuli (like all “0”s or all “1”s) on
the faulty chain and randomly change stimuli on the good chains. In [GUO07b], a complete test set generation was
proposed for single chain fault diagnosis. This technique attempted to create test patterns such that any given faulty
scan cell can be uniquely identified. This algorithm was extended to handle multiple failing scan chains and designs
with test compression logic. During test generation process, constraints on scan cell controllability and observability
were carefully analyzed when there are logic correlations between scan cells of the same scan chain.
5. New directions
The current chain diagnosis tools and techniques still need enhancements in the following aspects:
(1) Diagnosing multiple faults per chain is important for chain failures caused by systematic defects, library
cell reliability issues or process variations.
(2) There is a gap between the fault models and real defects such that the modeled fault only shows up
under certain situations. Diagnosis resolution needs to be enhanced for intermittent fault.
(3) Need a reliable solution for diagnosis of defects on clocks/scan enables/embedded compactor logic etc.
(4) Run time needs improvement such that volume diagnosing of large quantity of chips in production can
get results faster and use chain diagnosis results for yield learning.
(5) Tester memory capacity is normally limited, while chain defects produce a large number of failure
cycles. Performing chain diagnosis with central-buffer based testers is still a challenge.
(6) All currently used chain fault models are cell-based. So diagnosis resolution is at best down to one cell.
Normally, a scan cell and its connections will spread a large area in silicon. Therefore further enhancement
of resolution down to a specific signal / pin will be much more helpful for PFA.
6. Summary
In this paper, we reviewed various techniques of scan chain diagnosis. Different technologies have
their own application scenarios, advantages and disadvantages. Tester-based diagnosis techniques are very
effective, but they are time consuming and costly. Special scan designs for chain diagnosis are also helpful,
but are not available in most real designs. Software-based diagnosis can be easily automated for quick fault
diagnosis, but they still need enhancements with regards to diagnosis resolution and run time. The reviewed
paper and patents are classified in Table 2. We also proposed several future research directions in this area.
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Table 2: Classification of Chain Diagnosis in the Reviewed Paper and Patents
Software-based chain diagnosis
Use production scan patterns
Tester-
based
chain
diagnosis
Hardware-
based
chain
diagnosis
Simulation-
based
Probability-
Based
Dictionary-
based
Diagnostic ATPG
[DE95]
[SON04]
[STE04]
[MOT06]
[HIR99]
[MOT03]
[KON05]
[SCH92]
[EDI95ab]
[NAR97, 99]
[WU98]
[SON00]
[MOT05]
[TEK07]
[STA01] [GUO01]
[GUO02] [GUO06]
[HUA03b] [HUA04b]
[HUA05abc]
[HUA06ab] [HUA07ab]
[SAR92] [AHM06]
[KAO06]
[HUA03a]
[HUA04a]
[GUO07a] [KUN93, 94]
[FOR01] [BRU06]
[AND05] [YAN05]
[HSU06] [TZE07ab]
[LI05ab] [CRO05]
[SIN07] [GUO07b]
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[TEK07] R.C. Tekumulla and D. Lee, “On Identifying and Bypassing Faulty Scan Segments,” Proc. North
Atlantic Test Workshop, 2007, pp. 134-143.
[TZE07a] C.-W. Tzeng and S.-Y. Huang, “Diagnosis by Image Recovery: Finding Mixed Multiple Timing
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9
Yu Huang’s Bio
Yu Huang received his Ph.D. degree in Electrical and Computer Engineering from the University
of Iowa, USA. Dr. Huang is currently working as a Senior Member of Staff in the Advance Research
Group within the DFT division at Mentor Graphics. His primary interests are focused on VLSI testing and
diagnosis. He is a member of IEEE.
Ruifeng Guo’s Bio
Ruifeng Guo is a R&D engineer at Mentor Graphics Corp. He received a Ph.D degree in ECE
from the University of Iowa, Iowa City. He received a Master degree at Peking University, Beijing, China
and a Bachelor degree (with honor) from Nankai University, Tianjin, China. He also worked at Intel Corp
as a CAD development engineer. His research interests include VLSI testing, diagnosis and yield
improvement. He is a member of the IEEE and the IEEE Computer Society.
Wu-Tung Cheng’s Bio
Wu-Tung Cheng received his BS and MS degrees in electrical engineering from National Taiwan
University in 1978 and 1982, respectively, and his Ph.D degree in Computer Science from the University of
Illinois at Urbana-Champaign in 1985. His current positions are Chief Scientist and Advanced Test
Research Director in Mentor Graphics to lead a team to develop new DFT solutions for future
semiconductor quality and yield issues. Dr. Cheng has been an IEEE fellow since 2000.
James Chien-Mo Li’ Bio
James Chien-Mo Li received his BSEE degree in 1993 from National Taiwan University, Taipei,
Taiwan. He received his MSEE and PhD degrees in electrical engineering from Stanford University in
1997 and 2002 respectively. He is currently an associate professor of Graduate Institute of Electronics
Engineering, National Taiwan University, Taipei, Taiwan. His research interest includes design for
testability, built-in self test, low power testing, and fault diagnosis. He is a member of IEEE.
