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Chapter 11
Wafer Bonding
Shawn J. Cunningham and Mario Kupnik
Abstract Wafer bonding is an integral part of the fabrication of MEMS, opto-
electronics, and heterogeneous wafer stacks, including silicon-on-insulator. Wafer
bonding can be divided into two technological groups: direct bonding and interme-
diate layer bonding. Direct bonding relies on the cohesive bond that is formed when
the surfaces of two wafers are brought together under specific temperature and pres-
sure conditions. Direct bonding relies on critical parameters such as surface energy,
surface roughness, and surface morphology. Intermediate layer bonding relies on
the cohesive bond that is formed when the surfaces of two wafers are mated with an
intermediate layer. The intermediate layer can be an adhesive, polymer, solder, glass
frit, or metal. Surface roughness and topography are less critical for bonding with
an intermediate layer. Wafer bonding has found application in MEMS to fabricate
MEMS devices, to encapsulate the MEMS device in an hermetic environment, and
to transfer bond a complete MEMS device to a wafer with integrated circuits. Wafer
bonding has found its earliest applications for pressure sensors and accelerometers,
but the applications remain boundless.
11.1 Introduction
Without having access to the toolbox “wafer bonding,” the realization of micro-
electromechanical systems (MEMS), with its broad range of applications, would
be unimaginable. Wafer bonding is broadly classified as a bulk micromachining
method in contrast to a surface micromachining fabrication method, which so far
can be seen as the main method for the silicon integrated circuit (IC) industry. The
S.J. Cunningham (B)
WiSpry, Inc., Irvine, CA, USA
e-mail: shawn.cunningham@wispry.com
M. Kupnik (B)
Chair of General Electrical Engineering and Measurement Techniques, Brandenburg University of
Technology, Cottbus, Brandenburg, Germany
e-mail: kupnik@tu-cottbus.de
817
R. Ghodssi, P. Lin (eds.), MEMS Materials and Processes Handbook,
MEMS Reference Shelf, DOI 10.1007/978-0-387-47318-5_11,
C
Springer Science+Business Media, LLC 2011
818 S.J. Cunningham and M. Kupnik
reason to classify wafer bonding as bulk micromachining (i.e., in the same cat-
egory as etching deep feature into substrates) is that during wafer bonding two
entities, such as two wafers or individual dies and a substrate are brought into
contact. In surface micromachining mostly thin-films are deposited, grown, pat-
terned, and selectively etched. This categorization is not flawless, ofcourse, because
sometimes wafer bonding is used to transfer a thin-film only, such as the device
layer of a silicon-on-insulator (SOI) wafer on top of another wafer or the recently
emerging techniques in ultrathin wafer handling.
Wafer bonding can undoubtedly be counted as an enabling technology for the
field of MEMS, in the same way one would count high-aspect-ratio micromachining
of silicon using deep reactive ion etching (DRIE) [1] or selectively etching sub-
strates with liquid etchants, just to give two examples. Wafer bonding provides us
with the ability to fabricate sophisticated structures; it allows sealing and encap-
sulating devices or parts of a wafer; it enables us to transfer layers of various
materials from one wafer to another wafer; or it simply provides support for a device
fabrication itself during a sequence of fabrication steps.
The latter example is probably the one the reader already might be familiar with,
in particular when she or he has some hands-on experience in microfabrication. Very
often it is helpful to spin photoresist on a carrier wafer and then press a device wafer,
or pieces of such a wafer, against it. By heating this stack, one has performed wafer
bonding with an intermediate layer, photoresist in this example. Even though most
of the time1this bond will be separated at some later point (e.g., by resist remover
or acetone), it is a first simple example of its usefulness. The carrier wafer can be
used for mechanical support as a protection layer, or it can act as a holder for pieces
for further fabrication steps.
In general terms, wafer bonding aims to put two wafers (whole substrates or
pieces) together. This can be achieved either in a very nonintuitive way without
any intermediate material (direct bonding) or with an intermediate material (bond-
ing with intermediate material), as we explain later. In either case, the wafers can
be of the same material or of different materials. The range of possibilities of how
to achieve this goal, as we describe in this chapter, is extensive. The bond can be
required to be of a permanent nature (irreversible) for the realization of a particular
3-D MEMS structure, or of an impermanent nature (reversible) in the case where
a fabrication process requires or benefits from such a step, as in the example men-
tioned before. There can be only one bonding step, or more than one for a multiwafer
stack (lamination).
The requirements for the bond are as versatile as the possibilities of how to per-
form the bond. In some applications one needs hermetic sealing capability, such as in
device encapsulation or devices that require vacuum cavities (e.g., pressure sensors,
capacitive micromachined ultrasonic transducers (CMUTs) [2], micro resonators
[3], or devices that need to be sealed in a certain ambient. In other applications an
electrical contact at the bonding interface might be required or the resilience against
liquid etchants might be essential for subsequent fabrication steps. The cleanliness
1A good example for an exception where the resist (SU-8) is used as a permanent intermediate
layer for a MEMS device fabrication is described in [4].
11 Wafer Bonding 819
state of the wafer during a certain stage might limit the usage of certain materials
required for the bond, as well as the targeted bond strength that should be achieved
for reliable device operation and robustness in terms of humidity, thermal expansion
effects, or other influences.
There might be a certain thermal budget available that the wafers or materials
used can handle. A good example is the thermal limit a CMOS substrate can han-
dle (∼400–450◦C), which is an actual topic of importance for several applications
where sets of arrays of MEMS devices benefit from the integrated circuitry beneath,
with all its advantages (low parasitic capacitance, low-power consumption, etc.).
Such thermal limitation can be for performing the bond itself or to strengthen the
bond (irreversibility) in a subsequent annealing step. A good example for the advent
of such an application is the monolithic integration of capacitive micromachined
ultrasonic transducer (CMUT) arrays for volumetric imaging probes and therapeutic
applications.
Another aspect of the thermal budget is the thermal expansion effects. The
thermal expansion effects are not significant when bonding similar materials
together as in silicon–silicon direct bonding. The thermal budget and materials
are very important when bonding dissimilar materials or similar materials with
an intermediate layer. A good example is the anodic bonding of silicon to Pyrex.
Silicon and Pyrex do not have the same coefficient of thermal expansion (CTE)
but in fact they do have the same CTE at two temperatures (316 and 528◦C). With
knowledge of the bonding temperature and the material CTE, the user can select
the optimal temperature to minimize stress in the bond interface or to minimize die
warpage. The thermal mismatch is subsequently important if the bonded assembly
is mounted to a first-level package.
At this stage the reader might already recognize the breadth of the topic of wafer
bonding. Before describing the structure of this chapter, we would like to recom-
mend literature for further reading on the topic of wafer bonding. A good start
are the books Bonding in Microsystem Technology by Dziuban [5] (which con-
tains a lot of material for anodic wafer bonding), Semiconductor Wafer Bonding:
Science and Technology by Tong and Gösele [6], and Wafer Bonding: Applications
and Technology by Alexe and Gösele [7]. Furthermore, the excellent review articles
from Plößl and Kräuter [8] (focused on direct wafer bonding), Niklaus et al. [9],
and Schmidt [10] are highly recommended. In addition, we recommend the excel-
lent MIT thesis “Wafer Bonding: Mechanics-Based Models and Experiments” from
Turner [11].
In this chapter, our focus is on providing an overview on wafer bonding for
MEMS, and we discuss all the main techniques for wafer bonding suitable for
MEMS in general.
As mentioned earlier, wafer bonding can be done directly or by using an inter-
mediate material between the wafers. In fact, all wafer bonding techniques can be
classified based on this observation, as outlined in Fig. 11.1. A similar structure is
used for this chapter:
The first part of the chapter is focused on direct wafer bonding, which is consid-
ered as the more difficult bonding technique. As shown in Fig. 11.1, we list three
bonding techniques in the category of direct wafer bonding:
820 S.J. Cunningham and M. Kupnik
Wafer Bonding with
Intermediate Material
Direct Wafer Bonding
Wafer Bonding
Fusion Bonding:
High Temperature
Fusion Bonding:
Low Temperature
Silicon-Glass
Laser Bonding
Thermo Compression
Bonding
Anodic Bonding
Eutectic Bonding
Polymer Bonding
Metal-Metal Bonding
Solder Bonding
Glas Frit Bonding
Chemical Activation
Plasma
Activation
Fig. 11.1 Overview of various wafer-bonding techniques, classified by direct wafer bonding and
wafer bonding with intermediate materials
First, we have temperature-assisted direct wafer bonding at high or low tempera-
tures, often called fusion bonding. Because in both cases the activation is essential,
the two most frequently used techniques (i.e., chemical and plasma activation) are
listed as well. After providing some background information, we briefly explain the
physics involved and define the key parameters required to quantify and verify the
requirements for successful temperature-assisted direct wafer bonding. Then some
general recommendations are given, which the reader might find useful when plan-
ning a MEMS process that is based on direct wafer bonding. We then describe in
detail how a direct wafer bonding step is embedded in a MEMS device fabrication
process. In addition, we discuss how a wafer bonding tool works in principle, and
define when the usage of such a tool is inevitable.
Second, we list an electrochemically assisted direct wafer bonding technique at
lower temperatures (<500◦C), called anodic bonding. We count anodic bonding in
the direct bonding category, albeit there are cases (e.g., see Section 11.2.5), where
11 Wafer Bonding 821
an intermediate material such as Pyrex is sputtered on a wafer before the anodic
bonding step. However, for most cases two substrates, such as silicon and glass,
are anodic bonded without such an intermediate sputtered material. We explain the
basic principles and discuss an anodic-bonding-based MEMS fabrication process
for an accelerometer (wafer-level encapsulation).
The third technique that we list in the direct bonding category is silicon–glass
laser bonding, which is a laser-assisted direct wafer bonding technique.
The second part of the chapter is focused on wafer bonding with intermediate
materials. As shown in Fig. 11.1, there is large choice of techniques available. In this
chapter we only briefly describe thermocompression bonding and eutectic bonding.
Then polymer bonding is discussed in more detail including some example MEMS
processes.
After comparing some of the main wafer bonding techniques in Section 11.4,we
briefly discuss the bonding of heterogeneous compounds.
This is followed by a section about wafer bonding process integration focused
on localized wafer bonding and through wafer via technology, including several
process examples. The localized wafer bonding technique is one of the approaches
used to limit the temperature exposure of the full wafer or device(s). The through
via technology may not seem to belong in this chapter, which is true for many
applications. When we use direct bonding to form SOI or other heterogeneous struc-
tures, the through wafer vias are not important. When we apply wafer bonding to
encapsulation of a MEMS device, we have two alternatives: traverse the bond inter-
face with the electrical interconnect, or fabricate through wafer vias to achieve an
uninterrupted bond interface. Both scenarios have been successful.
In Section 11.7 we describe the main techniques to characterize the quality of
wafer bonding techniques in general, and then we provide information about the
existing wafer bonding infrastructure. At the end of the chapter, we list wafer bond-
ing service providers and introduce the wafer bonding tool vendors with examples
of their products suitable for MEMS applications.
11.2 Direct Wafer Bonding
As outlined in Fig. 11.1, there are several techniques for direct wafer bonding. In
microelectronics and the MEMS industry, direct wafer bonding is considered the
most difficult wafer bonding technique. In addition to strict requirements in terms of
cleanliness (particle-free environment), the uncertainty might be related to the lack
of availability of specific metrology tools during fabrication process development,
such as for surface roughness and wafer curvature. Another aspect related to this
might be proper surface activation before the direct bond. As we show at the end of
the chapter, in the last couple of years a healthy infrastructure of equipment vendors
and bonding service providers has developed, which will help to feature the full
potential of wafer bonding for MEMS in future.
822 S.J. Cunningham and M. Kupnik
11.2.1 Background and Physics
Direct wafer bonding describes the process of bonding two wafers together without
any intermediate material. Because wafers are composed of brittle material, direct
wafer bonding is fascinating: it contradicts our everyday experience. We are not
used to scenarios that two bodies just stick together without some assistance, such
as by glue or other malleable layers in between. In direct wafer bonding, however,
this is exactly the case, as demonstrated in Fig. 11.2.
For malleable materials it is easier to imagine that two surfaces can be brought
into close enough proximity so that forces between molecules or atoms start to play
a role, resulting in adhesion large enough that bonding occurs. Plastic deformation
provides enough mutual conformity on both sides that short-range forces can more
easily start to act.
In the case of brittle materials, such as silicon wafers, there is much less con-
formity between the two surfaces and bonding can occur only under very specific
conditions. It is exactly these conditions one needs to keep in mind when developing
a fabrication process for a MEMS device based on direct wafer bonding, as we later
show.
As outlined in the excellent review article from Plößl and Kräuter [8], which
contains a lot of material about the historic perspective on direct wafer bonding as
well, Galileo Galilei (1564–1642) had already hypothesized that two plane polished
surfaces of marble, metal, or glass, would adhere to each other whereas two rough
surfaces would not. Galilei postulated that it is the vacuum between the surfaces
that is the driving mechanism behind this adhesion. In the mean time, it is now well
known that this is not the case.
For direct wafer bonding, the short-range surface forces based on weak inter-
atomic bonds, such as van der Waals forces and hydrogen bonds are the dominant
ones. Van der Waals forces are attributed to fluctuations in the electron distribution
around atoms resulting in polarization (dipoles) of neighboring atoms, which leads
to small but finite attraction forces [12]. They are much weaker, but act over slightly
larger distances, than strong chemical bonds (covalent bonds), in which pairs of
electrons are shared between atoms. The effect of van der Waals forces is best visu-
alized by a force-separation curve (Fig. 11.3). In terms of the given numbers, this
curve is only valid for van der Waals forces; that is, the effect of hydrogen bonds
is neglected. Such a curve can be understood as a result of the combination of two
force components. First, the forces of attraction fall off rapidly with separation as
expected. Second, there must be a repulsive force component that starts to domi-
nate at a certain distance (<∼0.2 nm), because otherwise the attractive forces alone
would let the material collapse into virtually zero volume.
The shaded area in Fig. 11.3 corresponds to the work of adhesion (W) available
for the bonding (energy per unit area), the total work done by the surface attraction.
Before bonding two identical surfaces, both surfaces provide half of W, that is, the
free surface energies γ1and γ2. When the bonding wave propagates, the area in
contact increases (Fig. 11.2), resulting in increasing the interface energy γ12. Thus,
the surface energy available for the remaining nonbonded area decreases.
11 Wafer Bonding 823
Before contact Contact 10 ms 20 ms 30 ms
50 ms 70 ms 80 ms 90 ms
110 ms 120 ms
60 ms
140 ms 150 ms
170 ms 180 ms 190 ms
130 ms
210 ms
220 ms 240 ms 250 ms 260 ms
200 ms
280 ms 290 ms 300 ms 310 ms 330 ms
270 ms
Fig. 11.2 Sequence of frames from a video that shows two 4 in. silicon wafers bonding together
without any intermediate material. The wafers were illuminated by an IR light source from the bot-
tom and an IR-sensitive camera was used. The wafers were placed on top of each other, separated
by 150 μm thick spacers at the perimeter and then the direct bond was initiated by gently pushing
in the center with the backside of plastic tweezers. At locations where the two surfaces are already
in intimate contact, more IR light can pass through, which results in a brighter illumination for this
area. Within 330 ms the “bonding wave” propagated over a distance of 9 cm (visible diameter of
wafers in this setup)
824 S.J. Cunningham and M. Kupnik
Attractive forceRepulsive force
Force
Separation
~ 0.2 nm
~ 1 nm
~ 0.4 nm
Fig. 11.3 Typical
force-separation curve valid
for van der Waals forces
between two surfaces. In
terms of the given numbers,
this curve is only valid for
van der Waals forces; that is,
the effect of hydrogen bonds
is neglected. See, for
example, [11–13]
11.2.2 Parameters for Successful Direct Wafer Bonding
The concept of work of adhesion provides a basic understanding of the parameters
one needs to focus on during the development of a MEMS process that requires
direct wafer bonding. The goal of this section is to provide a guideline for the
development of a MEMS fabrication process that contains a direct wafer bonding
step.
Before further discussing all relevant parameters for such a guideline, we define
important topographical parameters of wafers in general. As Turner [11] describes in
his thesis, three different flatness deviations may be loosely defined for that purpose
(Fig. 11.4), which are based on their spatial wavelengths.
< 100 nm < 10 nm
(a) (b) (c)
Roughness Waviness Wafer shape
0.1 – 20 mm
10 – 100 nm
100 – 300 mm
10 – 200 um
Fig. 11.4 Typical types of flatness variations on typical wafer, after [11]
11.2.2.1 Surface Roughness
The flatness variation with the smallest spatial wavelength is described by roughness
parameters (Fig. 11.4, leftmost) such as the root-mean-square (RMS) value of the
roughness depth. This important parameter is calculated by taking the root mean
square of the series of measurements of deviations from the centerline. The best
tool for carrying out such measurements is an atomic force microscope (AFM) [14].
Having access to an AFM for the development of a MEMS fabrication process that
includes a direct wafer bonding step is invaluable. The AFM enables checking the
wafer surface for the presence of particles and it delivers the surface roughness
11 Wafer Bonding 825
(a) (b)
(c) (d)
3.5 nm RMS
0.18 nm RMS0.18 nm RMS
Fig. 11.5 Atomic force microscope measurements of three different samples: (a) wafer contam-
inated with particles; (b) silicon wafer with rough surface (has been exposed to plasma), which
would fail to bond via direct wafer bonding; (c) fresh prime quality wafer with smooth surface; (d)
rescaled (z-axis) view of the same data from (c). These wafers direct bonded successfully. For all
three samples an area of 5 ×5μm was scanned
information directly as a first indication of whether this wafer can be direct bonded.
Figure 11.5 shows exemplary results of such AFM measurements for three different
silicon samples.
On the first sample (Fig. 11.5a), five particles have been detected by the AFM.
The grooves, before and after each particle, are related to the dynamics of the AFM
cantilever and can be ignored for this context. Because for all of these measurements
only a small area of 5 ×5μm was scanned, this wafer can be assumed heavily
contaminated by particles, and, thus, requires proper cleaning (see Section 11.2.4.1)
prior to direct wafer bonding.
The second measurement result (Fig. 11.5b) is from a silicon wafer that was
exposed to a plasma-etching tool (resist removal tool). The surface roughness is
significantly larger than from the fresh prime quality silicon wafer (Fig. 11.5c, d).
These two samples were used for direct wafer bonding tests. The intentionally
roughened wafer did not bond and the smooth wafer bonded well.
The roughness of the surface is an important parameter, but it is not the only
one, as we show later. Therefore, only a quantitative upper limit of the RMS sur-
face roughness number for the direct “bondability” of a wafer can be given as a
826 S.J. Cunningham and M. Kupnik
guideline. This limit is around 0.25 and 0.5 nm for hydrophobic2and hydrophilic
silicon wafers, respectively. These numbers are based on our own experiments and
reported in the literature; see, for example, [8].
11.2.2.2 Waviness or Nanotopography
The waviness or nanotopography is found on a scale about three orders of magni-
tude larger than roughness (Fig. 11.4, center). In addition to AFM measurements
over a larger scan area, a good indicator of the wafer quality is the total thickness
variation (TTV), because it quantifies the wafer topography on that range of spatial
wavelength as well. It is defined as the maximal height difference between the high-
est and lowest elevation of the top surface of the wafer. Off-the-shelf prime grade
wafers exhibit TTV values of around 2 μm.
11.2.2.3 Wafer Shape
The wafer shape has the largest spatial wavelength and reflects the radius of cur-
vature and warp of the wafer. Direct wafer bonding in particular requires that both
wafers merge into the exact same curvature state, which requires energy to over-
come the strain energy present in the wafers before the bond. Note that depending
on the fabrication steps before the bonding step, the wafers can be flat, concave, or
convex. Certainly, the worst-case scenario is the situation where a concave and a
convex wafer are supposed to be direct bonded. The bond wave will only advance,
as it does in Fig. 11.2, when the surface energies for the nonbonded area are large
enough to overcome the strain per unit area [11]. As example, Fig. 11.4 (rightmost)
shows a concave wafer shape. Such a shape can be due to a compressive layer, such
as a thick thermally grown silicon dioxide layer on the backside, for example.
11.2.3 Recommendations for Successful Direct Wafer Bonding
As mentioned at the beginning of this section, our goal is to provide a guideline
with recommendations for those parameters one needs to focus on while planning a
MEMS fabrication process that utilizes a direct wafer bonding step:
•Ensure a particle-free bonding surface, that is, a clean environment. This is
absolutely necessary for a good bonding yield.
•Protect the bonding surface during all fabrication steps prior to direct wafer
bonding. Any exposure of the bonding area to plasma or liquid etchants must
be avoided or minimized to the absolute minimum. For example, Miki and
2A hydrophobic (in Greek hydro means water and phobos means fear) surface is characterized by
a high contact angle of water on that surface; that is, a hydrophobic surface has a low wettability.
Hydrophilic (in Greek philia means friendship) surfaces have low contact angle of water, that is,
high wettability.
11 Wafer Bonding 827
Spearing [15] investigated the effect of buffered oxide etch (BOE) and/or potas-
sium hydroxide solutions (KOH) on the surface roughness of silicon wafers.
Their experiments showed a clear decline of the effective work of adhesion
(bond energy) with the BOE and/or KOH treatment time due to increased sur-
face roughness. The immediate conclusion is that too long an overetch during a
silicon dioxide strip step, using BOE, can prevent successful direct wafer bond-
ing. Without proper AFM measurements such an increase in surface roughness
would stay undiscovered.
The protection of the bonding surface can be achieved with different tech-
niques, such as by using photoresist, thermally grown oxide, silicon nitride, or
other protective layers. This ensures low surface roughness values, assuming
the layer can be removed after certain fabrication steps without harming the
wafer surface. This is also valid for removing photoresist. Instead of using a
plasma-based resist-removing tool (ashes the resist by heat), as commonly found
in MEMS and CMOS foundries, one should rather use a regular piranha solu-
tion (H2O2:H2SO4) for removing the photoresist to avoid any extensive plasma
exposure of the wafer surface. Maintaining a low surface roughness is purely
motivated by the goal to maximize the available work of adhesion. The larger the
free surface energies, the more energy is available to overcome the strain in the
wafers. Based on this observation more recommendations can be given.
•Keep the wafers as flat as possible before the direct wafer bonding step in terms of
their radius of curvature. In case you have a MEMS process that includes several
fabrication steps before bonding, such as DRIE of cavities and/or the deposi-
tion of tensile or compressive films, try to monitor the radius of curvature of the
wafer. The exact knowledge of these changes in curvature allows planning steps
for stress state compensation of the wafer. For example, a MEMS fabrication pro-
cess requires an etch step (DRIE), but also the thermal growing of thick silicon
dioxide, for electrical insulation. By monitoring the curvature of the wafer, we
can selectively reduce the thickness of the compressive oxide on the backside
with the goal of reducing the radius of curvature before the direct bonding step.
This minimizes the required energy to overcome the strain energy present in the
wafers before the bond, and, this increases the likelihood of a successful direct
bond with good yield.
•In addition, avoid using thick wafers when not required in your MEMS process.
Where you have the choice between thicker and thinner substrates, choose the
thinner one. For example, in the fabrication process of a MEMS device a direct
wafer bonding step is required for transferring the active layer of an SOI wafer.
After that transfer the handle and buried oxide layer (BOX) need to be removed.
In this case it is better to order the SOI wafer with a thinner handle wafer and
with a thinner BOX layer when possible. This makes it easier to perform the
direct wafer bonding step, because there is less energy required to overcome the
strain in the wafers. The reduced energy to deform thin wafers is because the
stiffness of the wafer scales to the cubic power of thickness (αt3), which means if
the wafer thickness is reduced by a factor of 2 the stiffness is reduced by a factor
of 8. This is a very advantageous scaling for bonding.
828 S.J. Cunningham and M. Kupnik
•The overall integration of your MEMS process should consider a proper surface
activation method. This again has the goal of maximizing the available free sur-
face energies. There are several choices available, such as chemical-assisted and
plasma-assisted activation (see Section 11.2.4.1).
•While planning the layout of your MEMS fabrication process, keep the propa-
gation of the bonding wave in mind. Basically all wafer bonding tools initiate
the first contact between the two wafers in the center and then apply a defined
force on the wafer stack to support the bonding step. Before the tool applies the
force, the bonding wave propagates fairly symmetrical to the outside, as visible
in Fig. 11.2. In case your MEMS fabrication process contains an etch step before
the direct wafer bonding step for things such as fluid channels or cavities, the etch
pattern plays a significant role. A larger bonding area will provide more free sur-
face energy for the bond. Hence, for the same curvature and roughness situation,
it will always be easier to bond a nonpatterned wafer or a wafer with a pattern
that provides more bonding area. In addition, a good layout choice that supports
stable bond wave propagation might be helpful as well. Such a pattern could be
a spoke pattern, that is, a bonding area between the MEMS devices that provides
continuing outwardly radial stripes, as investigated by [11] in great detail.
11.2.4 Procedure of Direct Wafer Bonding
This section gives a detailed overview of how wafers are direct bonded. The struc-
ture of the section is based on Fig. 11.6, which outlines how a direct wafer bonding
step is embedded in a MEMS fabrication process.
11.2.4.1 Surface Preparation for Direct Wafer Bonding
Planarization Step
Sometimes the bonding criteria, as described in the previous section, are fulfilled
and one does not need to polish the wafer surface by chemical mechanical polish-
ing (CMP) to achieve the surface smoothness required for direct wafer bonding.
However, for many MEMS devices, CMP is required to obtain a sufficiently smooth
and flat surface. In addition, CMP can also be seen as a cleaning step because it
can be used to remove the uppermost layer of material (few nanometers) and, thus,
eliminating all surface contaminants present on the surface. For wafers with etched
patterns or other surface topography, CMP can be challenging due to dishing and
erosion effects [8,16]. In addition to silicon and thermally grown silicon dioxide,
CMP enables preparation of many other commonly used materials in MEMS pro-
cesses for direct wafer bonding, such as polycrystalline silicon, low-temperature
oxide (LTO), tetraethoxysilane (TEOS) (low stress) silicon nitride, silicon carbide,
quartz, fused silica, aluminum oxide, certain types of polymers, and even nanocrys-
talline diamond films. Based on our own experience, we can recommend for such
cases to consult with a highly specialized CMP company, such as Entrepix, Inc.,
Tempe, AZ, CTO Dr. Robert Rhoades.
11 Wafer Bonding 829
Conditions for direct wafer
lled
Alignment required, vacuum or
c ambient required, many
wafers, individual temperature during
bond (top vs. bottom wafer) ?
Yes No
Yes No
Yes
No
Polish wafers (CMP) and/ or
reduce curvature if possible
Fabrication steps of MEMS process
before direct bonding
Clean surface (RCA), HF dip only in case
hydrophobic surface is needed
Surface Activation:
- Chemical
- Plasma assisted
- Laser assisted (in tool)
Bond at room temperature/
elevated (hot plate),
done by hand
Bonding/Alignment tool
needed, at room/elevated
temperature
Thermal treatment according thermal budget
- high temperature fusion step
- low temperature fusion step
- no further heat treatment
Inspect wafers (e.g. IR) to check
for (particle) voids. Ok ?
Continue with MEMS fabrication
Fig. 11.6 Quantitative overview of how a direct wafer bonding step can be seen embedded in
a MEMS fabrication process. Depending on the type of MEMS device there are several options
available
830 S.J. Cunningham and M. Kupnik
Cleaning of Wafer Surface
After the wafers are in the state of having a smooth surface, careful cleaning
is required. The surface of the wafers for a direct wafer bonding step requires
extra careful cleaning. The goal is to have no particle contamination, no organic
contamination (hydrocarbons from air, commonly found in high concentrations
in cleanroom environments), and no ionic contamination (from metal tweezers,
glassware, etc.).
The effect of these three types of contamination in terms of bonding is different
[8].
Particles on the surface, such as shown in Fig. 11.5, have the most severe influ-
ence on direct wafer bonding. They act as spacers and produce a separation. As a
rule of thumb, a 1 μmlargeparticleona4in.silicon wafer produces a void of
about 1 cm in diameter [8]. As shown in Fig. 11.6, particle-induced voids can be
detected by simple IR inspection after the room temperature bond has been per-
formed. Because at that stage the bond is reversible, the wafers can be separated
and cleaned again. In the case where the particle void is ignored or too small for IR
detection (the large wavelength of the IR source limits the resolution), the size of
the void will only reduce slightly during the subsequent annealing step and, thus,
reduce the yield.
In terms of organic contamination the main problem is that the quality of
adhesion becomes degraded. After the room temperature bonding step, usually
nonbonded areas do not occur or at least are not large enough to be detected by
IR, but then during the thermal treatment step, thermally induced voids can occur
(nucleation of interface bubbles).
The concerns of metallic contamination are not so much on the quality of the
direct bond itself, but on the electronic properties of the semiconductor material,
which often might not be a problem at all for MEMS devices.
In general, the cleaning step for direct wafer bonding is not different than stan-
dard cleaning procedures [17,18] in the microelectronics industry. A standard
hydrogen peroxide-based RCA13wet cleaning procedure (mixture of ammonium
hydroxide, hydrogen peroxide, and DI water, in ratio 1:1:5) can be used, fol-
lowed by an RCA2 clean (mixture of hydrochloric acid, hydrogen peroxide, and
DI water). Another alternative, which the authors of this chapter use at the Stanford
Nanofabrication Facility, is to use a hydrogen peroxide and sulfuric acid (piranha
clean) mixture instead of the RCA1, followed by a standard RCA2 step. No increase
in surface roughness has been found (surface roughness measurements by AFM)
after this cleaning procedure, even after extensive cleaning times.
As indicated in Fig. 11.6, a dip in hydrofluoric acid (HF) can be included in the
cleaning sequence. In the case of a silicon wafer this would create a hydrophobic
surface because the native oxide is removed. Using this HF dip usually is advan-
tageous, because the native oxide layer often acts as a trap for metallic or organic
contaminations. It does not prevent the option of performing a hydrophilic bond,
3Named after the company Radio Corporation of America (RCA), in which Werner Kern, the
developer of this cleaning procedure, was working at that time [17].
11 Wafer Bonding 831
because it depends on the type of surface activation step, whether a hydrophobic or
hydrophilic direct bond is made.
Activation of Wafer Surface
For direct wafer bonding the surface activation step after the wafer cleaning is prob-
ably the most important step. The goal is twofold: to maximize the available free
surface energy and to terminate the wafer surface, that is, the dangling bonds, which
would be very reactive in the case where the wafers need to be exposed to cleanroom
air before the direct bonding step can be performed.
As mentioned in the previous section, there is often the important choice of
whether the direct bonding should be performed with a hydrophobic or hydrophilic
surface. Several aspects should be considered for the decision of whether a
hydrophobic or hydrophilic surface is used. These aspects are discussed as follows
for the example of silicon wafers:
•Two silicon wafers can be direct bonded with hydrophobic surfaces by strip-
ping the native oxide right before the bonding step by means of, for example,
performing an HF dip. In this case the bonding surface provides good electrical
connection as well. However, as soon as the bare silicon surface comes in con-
tact with any oxygen-providing ambient (also from the cleaning solutions used
for the RCA clean, as discussed before), a fresh native oxide layer will grow,
and, thus, the surfaces will be hydrophilic. The same is the case for wafers with
intentionally grown oxide films, but only when there is enough time and water
available for sufficient hydration of the oxide film. Such oxide film will be rela-
tively dehydrated, in particular right after oxidation in a dry ambient, and, thus,
be hydrophobic.
•Another aspect concerns the available thermal budget for the heat treatment step,
that is, the maximum temperature the wafers can handle. In this context, the
choice between hydrophobic versus hydrophilic bonding surfaces is essential
because it affects the bond mechanism for both the room temperature bonding, as
well as the reactions during the heat treatment step with the danger of increased
void formation (interface bubbles). This is discussed in Section 11.2.4.4 in more
detail.
•For hydrophobic silicon surfaces the dangling bonds are terminated by hydrogen
and fluorine depending on the ambient conditions, except in bonding tools where
the native oxide is removed under vacuum condition (see Section 11.8.2 about
wafer bonding tool vendors for details). The dangling bonds of the hydrophilic
silicon surface are terminated by oxygen–hydrogen (OH) groups (silanol groups).
The free surface energy of this OH-terminated surface is significantly higher ∼5
times due to hydrogen bonds [8], which, in general, is the reason why it is more
difficult to initiate a direct bond with hydrophobic than with hydrophilic silicon
wafers.
Thus, in general, a surface activation that leads to hydrophilic surfaces is
preferred and commonly used for direct wafer bonding.
832 S.J. Cunningham and M. Kupnik
The activation for a hydrophilic surface can be performed by chemical activation,
that is, by simply immersing the wafers into an ammonium hydroxide solution, sim-
ilar as RCA1, at around 75◦C for 15 min, as described, for example, in [19]. Another
approach for effective hydrophilization is using oxygen plasma [20]. For example,
[19] uses a 100 W, 6 sccm oxygen gas plasma in a reactive ion etcher with a base
pressure of 15 mtorr for a duration of 10 s and reports significantly improved bond-
ing strengths, even after low-temperature annealing (∼300◦C). For both activation
methods (i.e., chemical and plasma) the goal is to have a high density of OH groups
on the bonding surfaces.
When one direct bonds two wafers that have thicker films than just native oxide,
special care must be taken. Even after a long heat treatment at high temperatures
(>1000◦C) after the bond, the silicon dioxide to silicon dioxide bonding interface
can be a significant weak point in the stack for the remaining fabrication steps in
the MEMS device and, thus, should be avoided if possible. Köhler et al. [21]inves-
tigated this for liquid HF, which produces significant damage at the oxide–oxide
bond interface. These authors report that the bond interface of silicon dioxide to sil-
icon dioxide is heavily attacked by liquid HF due to capillary forces at the interface,
which can form a void between the two silicon wafers and weaken the structure
(high stress point). This is not the case for silicon-to-silicon and silicon-to-silicon
dioxide bonding interfaces. Furthermore, for the grown interface between silicon
and silicon dioxide no such damage can be observed.
Even more dramatic is the effect when vapor HF is used, which is commonly used
in MEMS fabrication processes as well. We conducted the following experiment to
demonstrate how the silicon dioxide to silicon dioxide bonding interface is attacked
by HF vapor. We oxidized two silicon wafers (2.5 μm, wet ambient at 1100◦C) and
then performed a direct bond (chemically activated as described before, and thermal
treatment at 1100◦C for 4 h). After etching (DRIE) trenches into the silicon wafers
from one side, we exposed the silicon dioxide to HF vapor. The wafer was kept at
45◦C during this HF vapor etching step to avoid condensation. The first 2.5 μm
oxide were etched with an etch rate of ∼100 nm per minute, as expected. As soon
as the oxide-to-oxide bonding interface was reached by the HF vapor, the interface
was severely attacked (Fig. 11.7a). At the bonding interface, the horizontal etch rate
increased by a factor of ∼250 (!) (Fig. 11.7b). It seems that imperfections along the
oxide–oxide bonding interface in combination with capillary forces are responsible
for this high anisotropic etch rate. However, for intentional release steps of large
structures this can be advantageous. In the case where the oxide–oxide interface is
exposed to plasma etching, no such behavior can be observed. In addition, the same
experiment, repeated for a silicon-to-silicon oxide bonding interface, reveals that no
horizontal etch rate increase occurs.
11.2.4.2 Bonding Step – By Hand or by Using a Wafer Bonding Tool
The next decision one has to make (Fig. 11.6) depends on the type of MEMS device
that is fabricated. As previously shown in Fig. 11.2, two wafers can be direct bonded
11 Wafer Bonding 833
(a)
(b)
Silicon
Silicon
Oxide remaining
Location of bonding
interface before etch
~ 250 micron etched in 10 min
Fig. 11.7 SEMs showing that a direct bonded silicon dioxide-to-silicon dioxide bonding interface
is very vulnerable when exposed to HF vapor
by just putting them on top of each other and gently applying some force at the cen-
ter location. Then this wafer stack can be loaded in a furnace, on top of a hot plate, or
beneath an IR lamp to strengthen the bond. Therefore, in principle no complicated
bonding tool is required for the bonding step itself. A good example for such a case
is the device described by Sarioglu and Solgaard [22]. This novel AFM cantilever
was fabricated based on a direct wafer bonding step: first the room temperature bond
was performed by hand with the help of a tilted support block made of Teflon (poly-
tetrafluoroethylene, hand-bonding tool; see Fig. 11.8) and then the wafer stack was
heated up in a regular oxidation furnace to 1050◦C for 2 h to strengthen the bond.
This hand-bonding tool allows submillimeter wafer level alignment for the bond-
ing and it is used as follows. The first wafer is placed on top of the block, and one
of the flats can be aligned to one of the edges on the left side (depends on the wafer
type and location of flats). The groove on the left side provides a well-defined edge
so that the wafer alignment is improved and it collects particles. Then the second
wafer is positioned on top of the first wafer. It will float on an air cushion, which
aligns the two wafers automatically by gravity due to the tilt. Then the pin (right)
is used to apply some force at the center location of the wafer stack, which initiates
the propagation of the bonding wave.
The best results are obtained when the bonding is performed below a flow bench
(fewer particles) or even better at an oxidation furnace, because then the airflow
direction is towards the operator. The tool is heavily used for direct wafer bonding
834 S.J. Cunningham and M. Kupnik
2 cm
wafers get aligned
at these two edges
by gravity
for applying force
at the center
downward
slope
for pick-up with
tweezers
groove that collects
particles and for well
ned edges
Fig. 11.8 Very useful tool for direct hand bonding available at the Stanford Nanofabrication
Facility. This version is for 4 in. wafers and made of polytetrafluoroethylene (Teflon). It was
designed by Dr. Aaron Partridge, SiTime Corporation, Sunnyvale, CA, and machined by Karlheinz
Merkle, Machine Shop Supervisor at Department of Physics, Stanford University
at the Stanford Nanofabrication Facility. Because it is made from Teflon it can be
cleaned regularly in a diffusion clean wet bench.
However, often a commercially available bonding tool will be required or pre-
ferred. A description of commercially available tools with more information can be
found in Section 11.8.2. There are several reasons why a bonding tool is inevitable
or advantageous for many MEMS processes. For example:
•Requirement for good alignment between top and bottom wafer. Several microm-
eters down to 200 nm are possible4on 300 mm wafers between the top and
bottom wafer.
•Another reason is the necessity of evacuating cavities during the wafer bonding
step. In that case the direct bonding step needs to be performed in vacuum or in a
different atmosphere. A good example for the vacuum requirement is the fabrica-
tion of wafer-bonded capacitive micromachined ultrasonic transducers (CMUTs),
first demonstrated by [2].
•State-of-the-art bonding tools provide further advantages such as reproducible
bonding conditions (temperature, pressure, force, etc.); the ability to activate, dry,
and preclean the surfaces in the bonder itself; and high-end models support auto-
matic operation for better throughput. At the end of this chapter we discuss the
4Most customers today specify a 1–3 μm alignment requirement for their bonding applications.
Only the latest high-end tools support low alignment tolerances down to 200 nm (personal email
exchange with Jim Hermanowski, from SUSS MicroTec Inc.). The market for such systems
is focused on 3-D IC fabrication, such as high-density memories (SRAM, DRAM, Flash), RF
technologies, and the like.
11 Wafer Bonding 835
operation principle of such bonding tools, which support many different methods
for wafer bonding, in more detail.
•As a general rule, one can say that the likelihood for successful direct wafer
bonding is higher when bonding tools are used. Furthermore, a better bond qual-
ity can be expected as well. Many times, however, direct bonding by hand can
be advantageous for certain MEMS applications, because of the low cost (no
tool purchase) and the short time required to bond wafers by hand compared to
bonding tools.
11.2.4.3 Basic Operation Principle of a Wafer Bonding Tool
The basic operation principle of a bonding tool is explained (simplified) as follows
(see Figs. 11.9 and 11.10):
The first wafer, with cleaned and activated bonding surface facing upwards, is
put on the chuck of the bonding tool (Fig. 11.9a). An exemplary photograph of a
(e) (f)(d)
(b) (c)(a)
(h) (i)(g)
(k) (l)(j)
Fig. 11.9 Exemplary sequence of steps (simplified) of how a bonding tool bonds two wafers
836 S.J. Cunningham and M. Kupnik
ag)
Wafer clamp
Loading arm
Bond chuck (4 inch)
Bonding chamber
Fig. 11.10 Exemplary photograph of a chuck (hand alignment only) of a wafer bonder (Model
SB6 from SUSS MicroTec AG, Germany). Pictures were taken at the Stanford Nanofabrication
Facility, Stanford, CA. There are many different chucks (for alignment, for various wafer sizes,
and for pieces) available
chuck with spacers and wafer clamps is shown in Fig. 11.10. Then thin spacers, also
called flags (∼150 μm thick) are positioned on top of this wafer at the outermost
perimeter, that is, a few mm into the wafer area only (Fig. 11.9b). After that, the
second wafer, with the bonding surface facing downwards, is carefully placed on top
of these spacers (Fig. 11.9c), before wafer clamps are attached to hold this stack in
place (Fig. 11.9d). It can be recommended to use an N2gun, equipped with a particle
filter, before placing the top wafer to ensure that no particles are present between
the wafers. Note that the steps so far can be performed in a regular alignment tool
as well for aligned wafer bonding, but then a compatible wafer chuck is required.
The next step is to open the purged chamber of the wafer bonding tool and load in
the chuck (Fig. 11.9e).
After the chamber is closed, the pump down and heating cycle is initiated
(Fig. 11.9f). Most bonders allow heating the top and bottom fixture, which will
be in contact with the chuck and the wafer stack, inside the bonder independently
(∼up to 500◦C). After the target vacuum level (e.g., 10−5mbar) is reached a pin or
membrane is used to apply some force in the center of the wafer stack (Fig. 11.9g),
as one would do during bonding by hand as well. At that stage the bond wave can-
not propagate far because the spacers are still positioned between the wafers. The
wafers are constrained in terms of any movement, and, thus, the wafer clamps can
be removed (Fig. 11.9h). Then the spacers are pulled out (Fig. 11.9i) and the bond
wave can propagate over the entire surface, as was the case in (Fig. 11.2). The center
pin or membrane is still in contact with the wafers, but in addition, now the tool has
space to move the top fixture down (Fig. 11.9j) and can apply a considerable amount
of force (e.g., 1000 N for direct bonding), depending on the type of bonding that is
performed.
In the case of anodic bonding (Section 11.2.5), an electrical voltage can be
applied via the center pin as well. For thermal compression or metal–metal bonding,
11 Wafer Bonding 837
usually much larger forces (up to 100 kN) are used. The bonded wafer stack
will remain for a certain amount of time (minutes to hours) under these pres-
sure and temperature conditions. It is also possible to ramp up the temperature
with a certain rate for performing a thermal treatment step already inside the bon-
der. After that, the force is released by moving the top fixture up (or the chuck
is moved down) and the temperature can be reduced by nitrogen or by slowly
purging the chamber (Fig. 11.9k). After unloading the chuck from the chamber,
the bonded wafer stack can be picked up (Fig. 11.9l) and is ready for inspection
under IR.
11.2.4.4 Inspection Before Heat Treatment
The next step (Fig. 11.6) is performing a first inspection by IR whether the bond
was successful or not. An illustration of such a system can be found in, for example,
the review article by Schmidt [10] or in the paper from Liu et al. [19].
The objective is to see whether the bond wave propagated over the entire wafer
surface without the presence of any voids due to particles or contaminants. Such
an example of two successfully direct bonded silicon wafers at room temperature
is shown in Fig. 11.11a. Voids with the typical Newton’s rings pattern or unbonded
areas are not visible, which means that the wafer can be loaded in a furnace for
further heat treatment to strengthen the bond. Another goal of an IR inspection after
the room temperature bond can be the verification of alignment tolerances. In state-
of-the-art wafer bonding tools (see Section 11.8.2), the IR inspection system can be
integrated into the tool for inline quality control.
In particular for direct wafer bonding, all of this is of great value because after
the room temperature bond, the bond is still reversible; that is, the wafers can be
(a) (b)
(c) (d)
Fig. 11.11 IR images of
direct-bonded silicon wafers,
annealed at different
temperatures. (a) Room
temperature bond without
annealing; (b) bonded silicon
waver pair after thermal
treatment at 950◦Cfor7h;
(c) 235◦C anneal for 5 h; (d)
400◦C for 14 h. These
experiments were done in the
Stanford Nanofabrication
Facility, Stanford University,
Stanford, CA
838 S.J. Cunningham and M. Kupnik
separated,5cleaned, surface activated, and aligned again for a second trial. However,
there are some exceptions to mention. This is not the case when systems are used
that perform a heating treatment already in the bonding tool, which makes the bond
irreversible. In addition, with the advent of the latest bonding tools featuring special
surface activation techniques (ion irradiation or in situ radical surface activation),
the full bond strength (covalent bonds) can be achieved even without such heat
treatment.
11.2.4.5 Thermal Treatment to Increase the Bond Strength
After the IR inspection there are several choices of how to proceed (Fig. 11.6). First,
depending on the initial activation method used, full bond strength might already
have been achieved, that is, covalent bonds without any or only low heat treatment
(<500◦C). The case of no heat treatment is still more exception than rule, but it
is heavily researched at the moment and the first commercial tools with special
surface activation modules are available. Such activations can be based on chemicals
(Ziptronix technology [23,24]) or other techniques (ion irradiation developed by
Mitsubishi Heavy Industries LTD, in situ radical activation developed by Applied
Microengineering Ltd [25–27]).
However, most likely a heat treatment will be required after the room temperature
bond to increase the bond strength suitable for MEMS device fabrication. There are
basically two temperature ranges of interest. The annealing can be done at temper-
atures larger or lower than ∼500◦C, which reflects a very loose classification into
high and low temperature direct bonding. Another important classification is related
to the application of technology, that is, the limits of 400–450◦C (maximum tem-
perature a CMOS wafer can handle) and 800◦C (maximum temperature for wafers
with diffusion layers); see, for example, [28].
The heat treatment step (annealing step) is the reason why instead of direct wafer
bonding the term fusion bonding is often used. Because the bond strength (energy
of adhesion) is tremendously increased during the heat treatment (∼one order of
magnitude), the wafers “fuse” together. The mechanism when heat is applied is to
transform the weak interatomic bonds, present after performing the room tempera-
ture bond, into strong covalent bonds. A regular oxidation furnace can be used for
high temperatures up to 1200◦C.
Even though the goal of the heat treatment step is the same for hydrophilic- and
hydrophobic-activated wafer surfaces, there are several differences to consider. As
shown by Tong and Gösele [6], with a heating treatment of >500–600◦C, the same
surface energies can be achieved for the bond, but the hydrophilic-activated wafers
already reach higher surface energies at lower annealing temperatures (200◦C). Note
that the given numbers in this section are for bonding in air. In general, vacuum
allows achieving higher surface energies at even lower heat treatment temperatures.
5The thin tip of a plastic tweezers or a simple razor blade can be used to gently separate the two
wafers at the outermost edge first.
11 Wafer Bonding 839
In the rest of this section we discuss the two most studied cases, that is, heat
treatment of hydrophilic and hydrophobic silicon wafers.
Heat Treatment of Hydrophilic Silicon Wafers
The bond at room temperature for the hydrophilic wafers is formed by hydrogen
bonds between chemisorbed water molecules on both wafer surfaces. At elevated
temperatures (>110◦C[10]) the desorption of water molecules sets in and the water
molecules are driven away from the bonding interface. This happens either along
the bonding interface to the outside or through the native oxide to the bulk sili-
con, where the water molecules react with the silicon to form silicon dioxide and
hydrogen. Thus, the heat treatment ensures that as soon as the water molecules have
left the bonding interface, the opposing silanol groups can come close enough and
start forming covalent Si–O–Si bonds (siloxane bonds) [8].Theformationofcova-
lent bonds translates to increased fracture surface energies (∼1.2 J m−2), which are
lower than the cohesive strength of silicon (∼2.5 J m−2, see, e.g., [29]. Only when
heat treatment temperatures of around 700–800◦C, or even higher, are used can the
cohesive strength of silicon be reached. Plößl and Kräuter [8] attribute this partially
to the formation of microgaps, which can only be closed when the native oxide gets
viscous enough for better compliance.
For the case that one of the two wafers has a thicker oxide film and the other
one only native oxide the situation is similar. However, this case is classified by [8]
as being ideal, that is, better compared to direct bonding two wafers with native
oxide only. This is because the native oxide from the first wafer allows the diffu-
sion of water molecules out of the interface and the thick oxide film from the other
wafer can absorb the hydrogen molecules, which reduces the formation of interface
bubbles (thermal induced voids) when moderate heating treatment temperatures are
used.
For illustration of this effect we conducted the experiment shown in Fig. 11.11.
Hydrophilic-activated silicon wafers (4 pairs) have been direct bonded and then
inspected under IR. For all four pairs a void-free room temperature bond was
achieved, as shown for the first sample, which was not annealed at all (Fig. 11.11a).
The bonds were performed with the hand bonding tool shown in Fig. 11.8.The
second sample (Fig. 11.11b), was annealed for 9 h at 950◦C. This temperature was
high enough so that after the heat treatment no voids were visible under IR. The
third sample, however (Fig. 11.11a), was annealed at a very moderate temperature
of only 235◦C for 5 h. A large number of thermal induced voids are visible after
that. For the fourth sample (Fig. 11.11d) which was annealed at 400◦C for 14 h, the
number of visible thermal induced voids is significantly reduced, albeit some larger
voids remained (Newton’s rings are clearly visible).
We also performed the same experiment for the case where one of each wafer
pair has a thicker oxide film, 1 μm to be specific. For the exact same three heat
treatment conditions as described before no thermal induced voids occurred.
Furthermore, such observations also provide understanding of why bonding two
oxidized silicon wafers is more difficult, in particular when the heat treatment is
840 S.J. Cunningham and M. Kupnik
performed at moderate temperature levels (∼500◦C). The thick oxide layers on both
sides make it difficult for the water molecules to diffuse through to the silicon to
react; that is, the water molecules remain and gather together to form microcavities.
In addition to the previously mentioned weak points in terms of liquid HF or HF
vapor of such an oxide to oxide bond, this is another reason why direct oxide–oxide
bonding should be avoided.
Heat Treatment of Hydrophobic Silicon Wafers
The main difference from the previous case is that the dangling bonds of the silicon
are terminated mostly by hydrogen atoms before the bond. As mentioned earlier,
these bonds are weaker than the OH groups of a hydrophilic silicon wafer. In addi-
tion, a higher heat treatment is required to increase the fracture surface strength.
As [8] outlines, a significant increase occurs at ∼400◦C and the cohesive strength
of silicon can be reached at 700◦C, which is lower than for the hydrophilic silicon
wafers (∼900◦C). The mechanism is similar; that is, the goal again is to transform
the weak hydrogen bonds into strong covalent silicon bonds by driving out of the
hydrogen atoms in the interface.
11.2.4.6 Remaining Fabrication Process for MEMS Device
After the heat treatment, the remaining steps required for the MEMS device fabrica-
tion can be done. Note that for these steps the choice of direct wafer bonding offers
two main advantages. First, there are no limitations in terms of temperature lim-
its because the direct wafer bond is high-temperature stable. Second, direct wafer
bonding does not add any additional materials to the wafers, such as required for
bonding with intermediate layers. As a result, the cleanliness level of the wafer does
not get degraded and diffusion clean equipment can be used after the bonding step
as well.
11.2.5 Anodic Bonding
The anodic bond process has been described beginning with [30]. An electrochemi-
cal process [31,32], it is driven by elevating the temperature of the glass–silicon
wafer pair and applying an electric potential across the wafer pair as shown in
Fig. 11.12. The silicon and glass wafers are aligned and placed together on a hot
plate with the silicon against the hot plate. The potential is applied after the tem-
perature of the wafers is raised by the hot plate and allowed to reach equilibrium.
The electric potential is applied, often times in small increments relative to the total
voltage across a small region adjacent to the silicon anode, which has been depleted
of sodium ions. The electric fields are highest in this thin depletion zone. These
high electric fields are the drivers of the oxygen anions, which are transported to the
anode interfacial surface and form an oxide with the anode atoms.
11 Wafer Bonding 841
Fig. 11.12 Basis anodic bonding process
The most common implementation of the anodic bonding process uses a silicon
substrate and a Pyrex substrate. The two materials have fulfilled the roles of both lid
and substrate, but a common scenario is an insulating Pyrex interconnect substrate
to which is bonded a silicon MEMS device and subsequently a silicon lid. The two
common process parameters are substrate temperature (180–500◦C) and applied
voltage (200–1000 V). The bonding process has been demonstrated with vacuum
or inert atmospheres, such as dry nitrogen, argon, neon. The atmosphere that is
being encapsulated is driven by the product requirements such as high mechanical
Q for resonators or damped frequency response for mechanical filters or high-g
products.
As shown in Fig. 11.12, the silicon and glass wafers are aligned and maintained in
intimate contact with the silicon wafer on the hot chuck of a wafer bonder. Usually,
the backside of the glass wafer is metallized for electrical contact, in which the
silicon substrate is the anode and the glass metallization is the cathode as shown. The
resultant applied electric field drive Na (or Li) ions from the glass silicon interface.
The disassociated oxygen ions react with the silicon to form an irreversible silicon–
oxide bond. The primary variables in this process are time, temperature, and voltage.
Because of the strong electrostatic pressure [33] that is developed this process is
more tolerant of surface topography or defects. During this process, the oxygen
may not be completely consumed by the silicon in the MEMS cavity. The resulting
partial pressure of oxygen will be detrimental to the vacuum level or mechanical Q
of the MEMS device. In this case, an oxygen getter will be needed to maintain the
low vacuum levels. The partial pressure of oxygen will change the viscosity of the
encapsulated gas and will need to be included in the estimate gas damping or again
eliminated through specific oxygen getters.
One aspect of this process that requires consideration is the concept that wafers
of two different materials are being bonded together at an elevated temperature.
Because the coefficients of thermal expansion for the two wafers are different,
wafer bow and interfacial stress will develop that can lead to premature failure.
The CTE for silicon and glass will vary with temperature so an optimal operating
point may be found that will minimize the stress but it may not optimize the bond
strength.
842 S.J. Cunningham and M. Kupnik
Depending on the process parameters, it was mentioned that the elevated temper-
atures that might be associated with the anodic bonding process could be detrimental
to integrated CMOS circuits or the MEMS materials themselves. The effect of the
anodic bonding process on integrated CMOS electronics has been studied using the
MOS capacitors. The parameters studied include Nm, the measured concentration
of mobile ions; Neff,, the measured effective oxide charge; and Dit, the measured
density of interface traps. The effect on these parameters was examined for MOS
capacitors inside and outside the bond cavity.
Nm,Neff, and Dit all increased with anodic bonding and their increase was greater
for devices outside the cavity. The increase was least when the gap was large
between the gate electrode and the glass wafer (<10–200 μm). A silicon nitride
passivation layer over the gate electrodes reduced Nm. The increased Nmcaused
and increased Neff and Dit, for the capacitors outside the bond cavity. The increased
Neff and Dit inside the cavity was caused by negative bias-temperature instability
(NBTI), which is caused by a combination of high temperature and high electric
field across the oxide. A likely reaction is for hydrogenous species A (H2O) react-
ing with Si–H defects to form a positive oxide charge (AH+) and an interface trap
(Si·)(≡Si −H+A+p+↔≡Si ·+AH+).
The anodic bonding process described above has been used to bond wafers for the
formation of silicon microstructures such as pressure sensors, accelerometers, and
gyros. In addition, anodic bonding has been used to fabricate a wafer-level encapsu-
lation of a microstructure. A production process is described for the fabrication of
a MEMS accelerometer for automotive airbag deployment. The fabrication process
used anodic bonding to bond a silicon micromachined sensing element to a Pyrex
substrate with fixed capacitor plates. In addition, the process anodic bonded a second
patterned wafer to the same Pyrex substrate. The second silicon wafer encapsulated
the sensing element and provided a hermetic environment of a dry inert gas (i.e.,
nitrogen, neon, argon).
The Ford Microelectronics (FMI) waferlevel encapsulation process [34–36]isa
classic example of lateral electrical feedthroughs. Although it is not an RF device,
some of the same techniques do apply to the RF device. The goals of this process
were to provide a wafer-level, hermetic encapsulation of a silicon accelerometer
(and other products that might be developed using the same process). This elimi-
nated the coat–saw–strip process for sawing an unencapsulated device. It provided
the technology needed to put the MEMS device into a low-cost plastic package and
that was robust to the plastic packaging process. It provided an inert environment
(dry nitrogen, neon) that could be maintained for 15 years. With reference to RF
applications of this encapsulation process, the electrical feedthroughs are fabricated
on as an insulating substrate (Pyrex) that will include a thin insulator (sputtered
Pyrex) between the interconnect and a silicon lid. The design of this feedthrough
performance could address the silicon resistivity, the transmission line width, and
the thickness of the sputtered Pyrex.
On the 7740 Pyrex substrate, the DC interconnects were patterned by liftoff
and deposited by evaporation of a metal stack comprised of Cr/Au/Pt/Au/Cr
(1500 Å) (Fig. 11.13a). This thickness is acceptable for DC interconnection of the
11 Wafer Bonding 843
Fig. 11.13 Accelerometer wafer-level encapsulation process
electrostatic MEMS device, but the access resistance would be limiting on the RF
performance. In the next steps, Pyrex is sputtered (1.5 μm) over the interconnects
to provide a planarized bonding interface (Fig. 11.13b). It was found for these metal
and Pyrex film thicknesses that the surface was adequately planarized to form a her-
metic anodic bond. For thicker metal films necessary for RF performance (0.5–1 μm
or thicker), the sputtered Pyrex layer would need to be thicker and a CMP process
844 S.J. Cunningham and M. Kupnik
would need to be introduced. These are known processes that could be introduced.
Following the sputtered Pyrex deposition, electrical vias are wet etched (Fig. 11.13c)
and filled with an evaporated Cr/Au/Pt contact metallization (Fig. 11.13d). A sili-
con microstructure is fabricated in parallel (not shown) and separately bonded to
this interconnect substrate (Fig. 11.13e).
The FMI process was a three-wafer process that included the Pyrex intercon-
nect/electrode substrate and a silicon device wafer that included an n-device layer, a
p+ etch stop layer, and an n–handle wafer. Each of the three wafers included shared
unit process steps, but they could be processed independently and in parallel. During
early production, it was found that the manual anodic bonder was a bottleneck in the
fabrication production flow. This occurred because two anodic bonding steps were
performed for each completed device. The first anodic bond was formed between the
device wafer and the Pyrex substrate. The second anodic bond was formed between
the Pyrex substrate, including the bonded device, and a silicon lid. The bottleneck
was eliminated by adding an automated bonding system that included an alignment
station, robot, and bonding station. This is just a reminder as you consider moving
your wafer-level encapsulation process into production. The third wafer was a sili-
con wafer ((100) n-silicon) used as the lid (Fig. 11.13g). The first step was to deposit
SixNyon both sides of the wafer and pattern one side, such that the SixNyacted as a
masking layer for a KOH etch (Fig. 11.13h). The KOH etch formed a 100 μm deep
cavity to provide a volume for the MEMS device and to provide standoff height for
the sawing process to expose the bond pads (Fig. 11.13i).
At this point the silicon wafer could be stored until needed for a mating wafer,
when the silicon nitride is stripped so the silicon wafer can be bonded to the Pyrex
wafer. On consideration with this particular stack is the thermal mismatch between
the silicon wafer and the Pyrex wafer. This bonding process was performed at 300 V
and 315◦C, where there is only a small difference in the CTEs of the two materials.
The silicon lid is shown bonded to the Pyrex wafer including the MEMS devices
in Fig. 11.13i.InFig.11.13j, a contact is deposited and patterned on top of the lid
for electrical connection. In subsequent assembly processes, it was possible to wire
bond to the contact on top of the lid further demonstrating the robustness of the
bond. During the wafer sawing process, the first saw cuts partially saw through the
silicon wafer to expose the bond pads. With the bond pads exposed, a wafer-level
electrical test was performed to identify known the good die and verify functionality.
After the functional test, the sawing process was completed to singulate the die,
which did not affect the integrity of the bond (Fig. 11.13k).
The packaged accelerometer product is shown in Fig. 11.14 at three levels of
assembly. The wafer-level encapsulated silicon accelerometer is epoxy mounted to a
Kovar lead frame. On the same lead frame paddle and adjacent to the accelerometer
die is the Delta–Sigma modulator ASIC that is used to convert the capacitance signal
for the accelerometer to a digital signal using the airbag deployment module. The
accelerometer die is wire bonded to the ASIC for sensing purposes and the ASIC
is wire bonded to the package pins. Figure 11.14a shows a lead frame strip with
several accelerometer and ASIC die mounted to the lead frame and ready for the next
processing steps. A close-up image of the accelerometer die is shown in Fig. 11.14b,
11 Wafer Bonding 845
(a) (b) (c)
Fig. 11.14 MEMS device shown with hermetic wafer-level encapsulation and low-cost, molded
plastic package
where the silicon lid can be seen bonded to the Pyrex substrate. In Fig. 11.14c,the
lead frame, accelerometer die, and ASIC die have been plastic over molded to form
a hermetic package. The package is hermetic because the silicon lid anodic bonded
to the Pyrex substrate is hermetic. Without the ability to form a hermetic bond by
anodic bonding of a silicon wafer to a Pyrex substrate, this hermetic accelerometer
in a low cost plastic over molded package would not be possible.
11.2.6 Silicon–Glass Laser Bonding
Wild et al. [37] produced strong reproducible bonds between polished silicon and
Pyrex wafers by laser bonding. The silicon and glass wafers are compressed together
between two plates as shown in Fig. 11.15. One of the plates is transparent to the
incident laser light, which needs to impinge upon the glass–silicon interface. They
used a fiber-coupled, Nd:YAG laser (λ=1064 nm) with a power of 15–30 W
with a laser scan velocity of 100–400 mm/min. They demonstrated bond spots and
lines up to 300 μm wide. The compressive load ranged from 10 to 30 MPa. They
found the hot zone was small and self-limiting by temperature-dependent thermal
Glass
Glass
Silicon
Base
Laser
F
Fig. 11.15 Basic
silicon–glass laser bonding
process
846 S.J. Cunningham and M. Kupnik
absorption and conductivity. The absorption increases and conductivity decreases
with increasing temperature. It is typical for the temperature outside the hot zone to
be 150–250◦Cfor<2s.
11.3 Wafer Bonding with Intermediate Material
11.3.1 Thermocompression Bonding
Tsau et al. [38] have characterized the fabrication of wafer-level thermocompres-
sion bonds, which can be described and the solid-state welding of two surfaces
with applied heat and pressure. The bonding material of choice is Au because it is
oxidation resistant, has a low yield point, is corrosion resistant, has a high electri-
cal conductivity, is an hermetic seal, and SiO2can be used as a diffusion barrier
between silicon and Au. The typical bonding temperature is 300◦C, which is much
lower than fusion bonding at 800◦C and on the order of anodic bonding at roughly
300◦C. The applied pressure between the two wafers is 7 MPa. It was found that
1500 Å of SiO2provides an adequate diffusion barrier between Si and Au. The crit-
ical strain energy release rate was determined to be 22–67 J/m2, which is largely
independent of the Au bond layer thickness for a thickness range of 0.23–1.4 μm.
A simple view of the process is shown in Fig. 11.16.
Fig. 11.16 Waf er -l evel
thermocompression bonding
11.3.2 Eutectic Bonding
The most common eutectic bond formed is between Au and Si as described by
Wolffenbuttel and Wise [39], but Au–In eutectic bonds are being developed for
lower temperature bonding. The Au–Si eutectic point is 363◦C, which is maintained
for about 40 min. The Au usually includes an adhesion layer such as Cr or Ti and
a diffusion barrier such as Pt. In Fig. 11.17, two examples of Au–Si eutectic bond
constructions are shown. In the first flow an SOI wafer with a silicon handle wafer,
SiO2isolation layer, and a silicon device layer is bonded to a silicon wafer with a
11 Wafer Bonding 847
Fig. 11.17 Au–Si and Au–In eutectic bonding
5000 Å Au layer. In a second implementation, the first wafer is a silicon wafer with
aSiO
2diffusion barrier (prevent diffusion between Au and Si), and a 5000 Å Au
layer (including a 150 Å Cr adhesion layer). The second silicon wafer includes a
SiO2isolation layer, a 150 Å Cr adhesion layer, 1100 Å Au (AuIn2) layer, followed
by a 6 μm indium bonding layer, and concluding with a 1500 Å (AuIn2) layer to
prevent indium oxidation. The Au–In bonding process is performed at 250◦Cfor
15 min with a 2 kgf force. The Au–In bonding temperature of 250◦C is significantly
lower than the Au–Si eutectic of 363◦C.
11.3.3 Polymer Bonding
Niklaus et al. [9,40–42] have written an excellent review of adhesive wafer bond-
ing and demonstrated the general application of adhesive bonding. Their purpose
was to describe the importance of adhesive wafer bonding that uses an intermediate
polymer layer to bond two substrates. The adhesive is applied to a surface of one
or both wafers. The typical method of application is by spin coating for thickness
uniformity. The wafers are joined together by the application of pressure. Finally,
heat or UV light is applied to convert the adhesive from a liquid or viscoelastic state
to a solid state. Adhesive bonding is often chosen for the following advantages: low
bonding temperature (RT to 450◦C); compatibility with CMOS wafers; compati-
bility with a high degree of surface roughness or topography; compatibility with
various wafer materials, including silicon, GaAs, glass (Pyrex, Hoya), Sapphire,
and InP to InGaAsP [43], compatible with various surface conditions relative to
cleanliness. Because adhesive bonding can accommodate various degrees of sur-
face roughness, topography, and even contamination, it does not require special
treatments such as planarization, chemical-mechanical polishing, or cleaning. On
the other hand, the polymers are not stable over a wide temperature range, cannot
848 S.J. Cunningham and M. Kupnik
survive in various harsh environments that include solvents, and do not provide
hermetic bonds against gases or moisture. In many cases the polymer or adhesive
bond materials are used for temporary bonds [44].
A list of polymers used in adhesive bonding is given in Table 11.1 showing
four general material classes including thermoplastics such as Parylene [45–47],
thermosets, elastomers, and hybrids. A thermoplastic has the characteristics of solid-
ifying upon cooling and can be remelted. Thermoset materials experience significant
cross-linking that forms a three-dimensional bond network and cannot be remelted
or reshaped. The elastomeric materials can sustain a large deformation with low
stress (5–10x the unstretched dimension).
Table 11.1 Polymers used in wafer bonding
Polymer material Characteristics
Epoxies Thermosetting
Thermal and two component curing
Strong and chemically stable
UV epoxies (Su8) Thermosetting
UV curable (if one substrate is UV transparent)
Strong and chemically stable
Bondable with patterned films
Positive photoresists Thermoplastic
Hot melt
Void formation at the interface
Weak bonds
Negative photoresists Thermosetting
Thermal and UV curable
Weak bond
Low thermal and chemical stability
Bondable with patterned films
BCB (benzocyclobutene) Thermosetting
Thermal curable
High assembly yield
Strong bond
Thermally and chemically stable
Bondable with patterned films
Flare Thermosetting
Thermal curable
High assembly yield
Bondable with patterned films
PMMA (polymethylmethacrylate) Thermoplastic
Hot melt
PDMS (polymethylsiloxane) Elastomeric materials
Thermal curing
Fluoropolymers Thermoplastic and thermosetting
Thermal curable or hot melt
Chemically stable
Bondable with patterned films
11 Wafer Bonding 849
Table 11.1 (continued)
Polymer material Characteristics
Polyimides Thermosetting and thermoplastics
Thermal curing and hot melt
Voids form during imidization process
Wafer/chip scale process
Bondable with patterned films
MSSQ (methylsilesquioxane) Thermosetting
Thermal curing
Strong
Chemically and thermally stable
Void formation during curing
PEEK (polyetherketone) Thermoplastic materials
Hot melt
ATSP (thermosetting copolyesters) Thermosetting
Thermal curing
PVDC (thermoplastic copolymers) Thermoplastic
Hot melt
Parylene Thermoplastic
Hot melt
LCP (liquid crystal polymer) Thermoplastic material
Hot melt
Very good moisture barrier
Waxes Thermoplastic
Hot melt
Low thermal stability
Temporary bonding
From Niklaus et al. [9]
The typical process steps for adhesive wafer bonding include: (1) cleaning
and drying the wafers; (2) treating the wafer surface with an adhesion promoter;
(3) application of the polymer adhesion layer to one or both of the wafers; (4) a
soft bake for partial curing of the adhesive; (5) wafers are placed in a bond chamber
where they are aligned and contact established; (6) an external load or pressure is
applied to the wafer stack; (7) the adhesive is remelted or cured during the pres-
sure loading; and (8) the wafers are cooled, the pressure removed, and the wafers
removed from the bonding chamber.
The cleaning and drying process is intended to remove particles, surface contam-
inants, and moisture from the wafer surfaces. Adhesion promoters may be needed
with some polymers and some materials. They are intended to change the surface
state of the wafer and enhance adhesion between the wafer and the polymer. The
polymer is applied to the wafer surfaces by spraying, electrodeposition, stamping,
screen printing, brushing, and dispensing of liquid precursors. The most common
method in MEMS and electronic fabrication is spin coating. The viscosity of the
liquid precursor and the spin speed of the wafer determine the resulting thickness
and will result in highly uniform thickness and smooth surfaces. Polymer adhesive
thicknesses have been achieved between 0.1 and 100 μm. In addition, the polymer
850 S.J. Cunningham and M. Kupnik
can be patterned so that the polymer bonds to a limited area of the mating wafer.
A softbake is performed to remove solvents and other volatiles from the polymer
material. Thermosetting materials are not or partially polymerized during the pre-
bake. Thermoplastic materials can be completely polymerized because they can be
remelted during the bonding process.
The wafers are commonly joined in a vacuum chamber to prevent voids and
trapped gases from being formed at the bond interface. It is necessary to be able
to pump away the trapped gases before the bond is initiated. During the pressure
loading steps, thermosetting polymers should be at the bonding pressure before
the curing temperature is reached because the polymerization is not reversible.
With thermoplastic materials, the bond pressure can be reached after the bonding
temperature is achieved. The remelting and curing of the adhesive occurs at the
bonding temperature. At the end of the bonding process, the sequence of chamber
purge, release of bonding pressure, and cooldown depend on the type of poly-
mer. With thermoplastics, the wafers should be cooled before the bonding pressure
is released so that the polymer is hardened and solidified before the pressure is
released. In Table 11.2, a process is outlined for the thermosetting polymer BCB
(benzo-cyclo-butene) [48].
Table 11.2 Typical BCB bonding process
Process step Processing parameters
Cleaning
Adhesion promoter
Polymer application Spin coating on one or both wafers
Softbake T=100 −170◦C, t=few minutes
Atmosphere 10−3mbar
Bonding pressure PB=0.2 −0.5 MPa
Curing temperature TB=200 −300◦C
Bonding time t=t(TB)−t=1 h at 250◦C
In the continued pursuit of lower temperature encapsulation processes, bonding
processes have been developed using epoxy or BCB bonding. This type of bonding
is consistent with many IC packaging alternatives. Some of the advantages of epoxy
bonding include low cost, an established process for packaging, and low tempera-
tures (60–200◦C). It is insulating so that it can be bonded directly to RF circuits or
transmission line. Because it is insulating it can work with through wafer or surface
transmission lines, which pass through the bond area. Two concerns associated with
organic bonds are hermeticity/leak rates and outgasing contamination. Leak rates of
10−7cc/sec have been achieved with epoxy and gross leak by BCB. The outgasing
can change the encapsulated environment, leave films that cause in-use stiction and
reduce lifetime, or more specifically reduce the reliability of switch contacts.
A simple example of BCB bonding is shown where the substrate and lid wafer
can be either silicon or glass, with the BCB applied to one of the wafers as shown
11 Wafer Bonding 851
Fig. 11.18 BCB bonding schematic
in Fig. 11.18. The BCB is a photosensitive, patternable material. It has a low loss
tangent: 8 ×10−4to 2 ×10−3for 1 MHz to 10 GHz. It has a high resistivity and
low dielectric constant of 2.65. During the processing, pressure and temperature are
needed. A typical bonding pressure is 250 gf. The BCB flows at a temperature of
170◦C and cures at 250◦C.
Jourdain et al. [49] demonstrated wafer-level packaging of RF MEMS devices
using BCB bonding with both thick and thin (<100 mm) lid wafer processes.
Using the BCB material allowed the implementation of coplanar RF transmission
lines under the BCB seal ring rather than developing through wafer intercon-
nect/transmission line processes. The BCB process is a low temperature process
where the BCB reflows at 150◦C and cures at 250◦C. To achieve the RF perfor-
mance, low-loss, high-resistivity lid materials are used and the cavity height should
exceed 1/3 CPW width with the high resistivity silicon. The BCB process was
demonstrated with a thick lid wafer that was formed from silicon or glass. A cavity
is etched 10–80 mm into the lid wafer that is approximately 650 mm thick as shown
in Fig. 11.19a. The BCB is spin coated and patterned on the wafer to a thickness of
3–10 mm. The lid wafer can be diced into individual die and bonded to a device die
or the lid wafer can be bonded to the device wafer (Fig. 11.19b). In this case, a die
level bond is described using standard flip-chip bond equipment. The lid is flipped
to mate the BCB seal ring to the device wafer as shown in Fig. 11.19c. The BCB
bond was formed with an applied force of 250 gf, at a reflow temperature of 170◦C,
and a cure temperature of 250◦C.
The thin lid wafer process was developed as a low-profile encapsulation process.
The lid wafer is less than 100 μm thick and is handled by bonding the thin lid wafer
to a handle wafer using wax (Fig. 11.19d). With the lid wafer bonded to the handle
wafer, the BCB is spin coated and patterned to form the seal ring at a thickness of
3–10 μm. As in the previous case, the thin lids are sawn into individual lids that are
flip-chipped onto the MEMS die to form the seal (Fig. 11.19e). The wafer is heated
to 150◦C to melt the wax to remove the handle wafer and cure the BCB material as
shown in Fig. 11.19f. The lidded MEMS device wafer is sawn into individual die
after lidding.
852 S.J. Cunningham and M. Kupnik
Fig. 11.19 BCB bonding for thick and thin wafers
A second example of low-temperature organic bonding for micropackaging is
the microcap packaging process described by Pan [50]. In this process a silicon car-
rier wafer (100) is used as a lid form, which typically has a thickness of 525 μm
with a 1.5 μm thick thermal oxide (Fig. 11.20a). The microcap form is etched into
the silicon using a 30% wt solution of KOH at 70◦C using the thermal oxide as
an etch mask as shown in Fig. 11.20b. The thermal oxide etch mask is removed
before a 1500 Å Ni seed layer and passivation layer are sputter deposited as shown
in Fig. 11.20c. A thick photoresist is deposited and patterned for electroplating the
thick Ni (15 mm) cap structure shown in Fig. 11.20d.InFig.11.20e, a photopat-
ternable bonding material is deposited, solvents evaporated and developed, and the
electroplating template is stripped. The cap wafer is now ready to be flip-chipped
onto the device wafer as shown in Fig. 11.20f. The bond was formed using a com-
bination of force, temperature, and materials. Once the bond is formed the carrier
wafer is removed to leave the Ni cap bonded to the device wafer (Fig. 11.20g). The
Ni seed layer passivation is needed to be able to separate the carrier wafer from the
Ni cap.
The bonding strength was measured and found to be maximized between 80 and
120◦C. SU8 had the highest bond strength rated at 213 kg/cm2and 90◦C. Other
bonding layers included AZ-4620 (86 kg/cm2at 90◦C), SP-341 (100 kg/cm2at
90◦C), and JSR (88 kg/cm2at 90◦C). The bond strength increased with increasing
bond force and the authors recommended a minimum bond force of 50 N. The glass
11 Wafer Bonding 853
Fig. 11.20 Microcap packaging process using Ni cap and photodefinable bonding material
transition temperature of the bond material limits the bonding temperature from 115
to 180◦C.
A final example of an encapsulation process using epoxy and other organic mate-
rials has been developed. The process begins with a completed MEMS device and
substrate that can be 8–10 in. glass, silicon, or GaAs wafers. The MEMS device die
is flipped (device down as shown in Fig. 11.21a) and bonded to Kapton film using
a B-stage epoxy. The Kapton has a cavity to house the MEMS device and includes
the transmission lines for the RF signals. At this point the MEMS die is encapsu-
lated in polyimide. The polyimide is etched to create vias for interconnection of the
RF I/O and DC control lines. The vias are metallized with Ti/Cu/Ti as shown in
Fig. 11.21 Encapsulation process using Kapton, polyimide, and vertical feedthroughs
854 S.J. Cunningham and M. Kupnik
Fig. 11.21b. This process produced low-loss feedthroughs at <0.1 dB at 10 GHz.
Finally, the polyimide encapsulated, Kapton substrate passed an 85% RH, 85◦C,
10,000 h test with air bridges.
11.4 Direct Comparison of Wafer Bonding Techniques
The type of bonding that is used will be determined by many factors: materials,
surface roughness and topography, temperature or pressure limitations, and product
requirements. In Table 11.3, a summary of wafer bonding techniques is presented.
11.5 Bonding of Heterogeneous Compounds
The bonding of heterogeneous materials includes wafer bonding of lattice mis-
matched materials, which is important because these heterogeneous devices cannot
be formed by other methods. Wafer bonding enables the integration of GaAs/InP,
InP/Si [51], GaAs/Si, and GaAs/GaN. Eom et al. [52] have described the forma-
tion of YBa2Cu3. The integration of these heterogeneous structures has allowed the
production of light-emitting diodes, vertical cavity lasers, avalanche photodiodes,
vertical couplers, and heterojunction bipolar transistors (HBTs). It is possible to
wafer-bond GaAs to another GaAs wafer or other material [53–55], which increases
the technological opportunities. This provides the flexibility to design enhanced
optoelectronic systems. The bonding of wafers to sapphire has been described by
Kopperschmidt et al. [56] and the construction of strained layers is described by
Taraschi et al. [57–59].
The bonding of GaAs wafers has been described by Akatsu et al. [60], who have
pursued more moderate direct bonding conditions to improve the bonding process
for GaAs. In a typical direct bonding process, high anneal temperatures are used to
increase the bond strength between two wafers. But this approach with GaAs can
compromise the integrity of the interface such that gallium or arsenic oxides may
be enclosed by bubbles that form as part of the decomposition of absorbates. The
high temperatures have been between 400 and 975◦C for a few hours to 20 h in an
inert or reducing atmosphere. Another issue with the high anneal temperatures is
the thermal mismatch between dissimilar materials such as GaAs and silicon. The
high mechanical load will cause structural damage and make it difficult to scale the
process to whole wafers. Typical mechanical loads of up to 40 kg/cm2have been
used.
A major challenge for GaAs bonding is cleaning the surfaces because of the
complexity of removing the oxides of Ga and As at the same time. The native oxides
of Ga and As exist on the wafer surface when exposed to air and coexist with carbon
contaminants and absorbed water. The water can be removed by low-temperature
heating and the oxides can be desorbed above 580◦C. The carbon contaminants are
not removed by thermal cleaning but can be removed by atomic hydrogen in an ECR
(electron cyclotron resonance) plasma.
11 Wafer Bonding 855
Table 11.3 Wafer bonding methods, conditions and applications
Wafer bonding
method Bonding conditions
Advantages
disadvantages Applications
Direct bonding RT-1200◦C
No-small pressure
+ High bond strength
+ Hermetic
+Hightemperature
compatibility
– High surface flatness
requirements
–Hightemperature
incompatible with
integrated CMOS
process
SOI wafer fabrication
Heterogeneous
structures
Anodic bonding 150–500◦C
200–1500 V
Electrostatic pressure
No mechanical
pressure
+ High bondstrength
+ Hermetic
+ Resistant to high
temperature
– Bond temperature and
high voltage are not
compatible with CMOS
wafers
Sensor packaging and
fabrication
Solder bonding 150 – 450◦C
Low bond pressure
+ High bond strength
+ Hermetic
+ Compatible with CMOS
wafers
– Solder flux
Flip-chip bumping
Hermetic sealing
Eutectic bonding 200–400◦C
Low to moderate
bonding pressure
+ High bond strength
+ Hermetic
+ CMOS compatible
– Native oxide sensitivity
Hermetic sealing
Thermocompression
bonding and
metal–metal
bonding
350–600◦C
100–850 MPa (high
bond pressure)
+ Hermetic
+ CMOS compatible
– High bonding pressure
– High surface flatness
Hermetic sealing
Wire bonding
Flip-chip bumping
3-D ICs
Ultrasonic bonding RT – 250◦C
High bond pressure
+ CMOS compatibility
– Only small bond area
demonstrated
Wire bonding
Low temperature
melting glass
bonding
400–1100◦C
Low–moderate
bonding pressure
+ High bond strength
+ Hermetic
– CMOS compatibility
Hermetic sealing
Adhesive bonding RT–400◦C + High bond strength
+ Low bond temperature
+ Substrate material
diversity
+ CMOS compatible
– Not hermetic
– Temperature stability
3-D ICs
Temporary bonding
MEMS packaging
856 S.J. Cunningham and M. Kupnik
The cleaning of GaAs wafers begins with the desorption of arsenic oxides by
heating to produce a Ga-rich surface. The arsenic oxide can be removed by the heat-
ing but also by the hydrogen cleaning. The hydrogen cleaning follows the process
As2Ox+2xH·→xH2O↑+As2(1/2As
4)↑, where x=1, 3, or 5 representing
the various arsenic oxides. The Ga oxide is decomposed in the following process
Ga2+4H·→Ga2O(↑)+2H2O↑. The remaining Ga2O is volatile at temperatures
above 200◦C but temperatures above 350–400◦C are preferred so the Ga2O is reli-
ably desorbed. In Table 11.4, a preferred direct bonding process is provided. The
preferred process of Table 11.4 includes the thermal cleaning with atomic hydrogen
and a low bonding temperature of 150◦C. When the wafers were thermally cleaned
(400◦C for 30 min) in a H2or UHV (ultrahigh vacuum) process, the wafers had low
bond strength or formed no bond with a bonding temperature of 350◦C.
Table 11.4 GaAs direct bonding process
Process step Process parameters
Wafer cleaning Thermal and hydrogen clean >350◦C
Cleaning time 30 min
Bonding temperature 150◦C
Bonding force 0 N/m2
Bond energy 0.7–1.0 J/m2
11.6 Wafer Bonding Process Integration
11.6.1 Localized Wafer Bonding
A key requirement of the bonding process to achieve a strong and hermetic bond
is the temperature. In a conventional bonding process the entire wafers (substrate,
lid, and interface) are raised to a uniform temperature. The temperature depends
on the process: 1000◦C for silicon-to-silicon fusion bonding, 300◦C for silicon-to-
glass anodic bonding, 363◦C for Au–Si eutectic bonding, or 450◦C for glass frit
bonding. These temperatures are too high for many MEMS material systems or
when the MEMS process includes integrated electronics. The integration of MEMS
and CMOS using wafer bonding has been described by Farrens et al. [61], Lin et al.
[62], Parameswaran et al. [63], Sedkey et al. [64], Van der Groen et al. [65], Frazier
[66], and Ghodssi et al. [67]. This means the global temperature of the bonding
process needs to be lowered or that the high temperature needed for bonding should
remain localized to the bonding interface so that temperature-sensitive structures are
not heated to a high temperature. In this section, we discuss the processes that have
been developed with localized heating and bonding to encapsulate MEMS devices.
Cheng et al. [68–70] describe both direct and indirect localized heating and bonding.
In direct bonding, the heater material also acts as the bonding and sealing material
[71–74]. In indirect bonding, the heating element is preserved during the heating
11 Wafer Bonding 857
and bonding process because a separate material is used as the bonding and sealing
material [75].
Cheng et al. [68,70] have demonstrated localized silicon fusion bonding between
an insulated silicon substrate and a glass wafer (7740 Pyrex). The insulated silicon
substrate will contain the MEMS devices and could contain integrated electronics.
Electrical and thermal isolation are provided on the silicon substrate by a nominal
0.8 μm silicon dioxide layer. For fusion bonding, polysilicon is used as the micro-
heater and seal material. It is nominally 1.0 μm thick, 5 μm wide, and forms a closed
ring that defines the bond region. Two electrical taps are made from the microheater
to provide connection to the current source. The microheater is provided an input
current of 31 mA to develop a local temperature of about 1300◦C, which is above
the Pyrex softening point of 820◦C and close to the polysilicon melting point. This
process takes about 5 min and is performed witha1MPapressureapplied to the
parts. In a conventional fusion bonding process, where the entire substrate is heated,
the bonding temperature is typically over 1000◦C for approximately 2 h. In a sec-
ond experiment Cheng et al. [68] found that raising the local temperature to 1000◦C
for 30 min, when the current was 29 mA resulted in a bond of lower strength and
quality.
In addition, Cheng et al. [68,70] demonstrated a localized Au–Si eutectic bond-
ing process between the insulated silicon device substrate and a silicon lid. In this
case, the microheater material was Au, and 5 μm wide and 0.5 μm thick. It is
provided a current of 0.27 A for 5 min, which raised the local temperature to an esti-
mated 800◦C. During the bonding process, the Au diffused into the silicon to form
the bond and seal. The diffusion and solubility of Au in Si increase with increasing
temperature. The local heating process provides a higher temperature (800◦C) than
a more conventional Au–Si eutectic process performed at about 410◦C for 20 min.
The local heating process was shown to provide a more uniform, higher strength,
and higher quality bond than the conventional process.
11.6.2 Through Wafer via Technology
Why are we discussing through wafer via technology in this chapter on wafer bond-
ing? The answer depends on the reason for using the wafer bonding process. If the
wafer bonding process is being utilized to fabricate a heterogeneous wafer stack,
such as SOI or InGaAs/Si, or to transfer one thin-film to another wafer or hetero-
geneous wafer stack then the through wafer via technology does not need to be
considered, which is not to say that the through wafer via technology does not apply
to these heterogeneous wafers. The through wafer via technology should be consid-
ered whenever electrical connections are required for a multitude of active electrical
devices. We discuss the important considerations when integrating wafer bonding
and through wafer vias (TWV), which have been referred to as TSV (through silicon
via, which is rather limiting) and TWI (through wafer interconnects).
Why are we developing through wafer interconnect technologies? One reason is
to increase the density of devices on the MEMS substrate. One of the reasons for
858 S.J. Cunningham and M. Kupnik
developing through wafer interconnects is to achieve high-density interconnections
with a smaller footprint. This is because the dies rapidly become bond pad limited
or wire bond limited, if all of the bond pads are placed at the perimeter of the die.
With the through wafer interconnects, the electrical connection can be made directly
to the bottom of the MEMS device for the purpose of actuation or to the RF ports of
the RF MEMS component. The die can now be directly bonded to a substrate using
a solder reflow or thermo-compression process.
Another case for through wafer interconnects was described in the Ford
Microelectronics process, which describes perimeter bond pads that are exposed
by wafer dicing following the wafer-level encapsulation process. The wafer saw
exposure of the bond pads is eliminated by using the through wafer interconnect
technology. A second reason is reliability. The through wafer interconnect process
is associated typically with a wafer-level encapsulated MEMS device. Because of
the through wafer interconnect process, the MEMS device is protected during any
and all backend processes, such as wafer saw, wafer grinding, plastic encapsulation,
flip-chip mounting and underfill, solder reflow, shipping, and handling. This means
fewer opportunities to introduce contaminants (e.g., photoresist protect films and
other particles).
As discussed previously, the electrical interconnects or transmission lines can be
fabricated across the wafer and pass through a space defined as the bond/seal region
between the substrate and the lid or can be fabricated through the wafer as described
in this section. The through wafer interconnects take on two basic configurations.
The first configuration fabricates the TWI through the substrate upon which the
MEMS devices are built. This process in theory can be implemented by fabricating
the TWI before or after the MEMS fabrication. The second configuration fabricates
the TWI through the lid wafer. In this latter case, the TWI can be fabricated before or
after the lid is bonded to the device wafer. Whether the TWIs are fabricated through
the lid or the substrate, there are many different ways to implement the various
processes.
Surface interconnects/transmission lines pose many challenges beyond the sim-
plicity of their deposition and patterning. The first challenge is topography created
by the interconnect that may have a thickness of 0.5 μm for a standard CMOS AlCu
layer. The topography poses greater challenges for the direct bonding methodologies
because these require low topography and low surface roughness. The topogra-
phy will need to be addressed by the deposition of a dielectric film to encapsulate
the electrical interconnect. In a subsequent step, a chemical-mechanical polish-
ing is performed to eliminate the topography of the interconnect. The next step
is the preparation of the polished surfaces and finally direct bonding of the wafers.
Because the interconnect will be encapsulated in a dielectric material for electri-
cal isolation from the bonded wafers, this will determine the selection of dielectric
materials and the selection of the direct bonding technique. The surface topogra-
phy is more easily addressed by wafer bonding with intermediate layers, which will
eliminate the need for planarization by CMP. If the intermediate layer is a dielectric,
such as a glass frit, polymer (BCB), or adhesive, the intermediate layer will provide
the dielectric isolation between the interconnect and the bonded wafer.
11 Wafer Bonding 859
If the intermediate layer bonding is based on a metal eutectic or a solder, the
topography will need to be addressed in a similar manner. Solder bonding will
accommodate the surface topography easily, but the solder will form an electri-
cal contact to the interconnect unless it is encapsulated in an insulating layer. In
some cases it may be desirable to form an electrical contact to the seal ring such as
grounding the seal ring for some RF applications. If electrical isolation is required,
the interconnects can be encapsulated in an insulating film that is planarized as we
described for the direct bonding process. This process sequence will be required for
intermediate bonding by eutectic formation, because the eutectics (e.g., Si–Au) do
not accommodate the surface topography. If the interconnect is encapsulated in the
dielectric it is still possible to form an electrical connection of the conductive seal
ring by forming a short via through the thin dielectric to the interconnect.
The second challenge for surface interconnects is the electrical isolation or con-
tact, which has been described in the previous paragraph as part of the solution to
bond over the surface topography.
The third challenge is the formation of an hermetic seal because it is possible the
interconnect will provide a leakage path, moisture, or gas. It is important that the
dielectric isolation layer, solder, or glass frit form a conformal coverage of the inter-
connect topography, which means an absence of voids parallel to the interconnect
sidewall between the sidewall and the intermediate layer.
The fourth challenge is the exposure of the electrical contact pads for wirebond-
ing or solder bumping. This process has been described earlier as part of the Ford
Microelectronics process. This involves providing a cavity on the bonded wafer that
aligns to the electrical pad on the base wafer. Once the bond is formed the pads can
be exposed by the use of a wet chemical etch, a plasma etch, or DRIE, or by saw
exposure. These have all been used successfully, but the DRIE and sawing enable a
well-controlled high-aspect-ratio exposure. The wet etch is usually isotropic which
leads to very large pad openings and therefore die.
We have described electrical interconnects that are patterned on the surface of
the wafer and through the bonded area and that are fabricated through the wafer. We
next describe the similar challenges that relate to TWIs that are fabricated through
the device wafer or through an encapsulation wafer. The first challenge of surface
interconnects is the surface topography, which is not a typical challenge for the
TWIs. The second challenge is the electrical isolation of the TWIs. The isolation
of the TWI from the bonded wafer or seal ring is easily accomplished by blanket
dielectric films that may not require CMP. If it is necessary to connect a TWI to a
conductive seal ring, this can be fabricated with a short damascene via described
above. The isolation of the TWI from the via sidewalls is often accomplished by
deposited dielectric that provides the best isolation for a greater thickness. Because
the dielectric constant (4 for silicon oxide) is relatively large, the coupling can
be high depending on the thickness. Air isolated TWIs have been developed, that
replace the silicon oxide with air that has a dielectric constant of approximately 1.
The air isolated TWIs will reduce parasitic capacitance coupling by a factor of 4.
A through wafer interconnect process was developed at Stanford so that they
could create a high density array of cantilevers as demonstrated by Chow et al. [76].
860 S.J. Cunningham and M. Kupnik
Without the through wafer interconnects, the cantilever density is limited because of
the need for area to place bond pads and route electrical interconnects. Additional
goals included flip-chip integration of MEMS device die and integrated circuit die,
low parasitic capacitance using reverse-biased PN junctions, and low resistance
achieved with high-conductivity polysilicon.
This process was demonstrated on 400 μm thick n-type, <100> silicon wafers.
A2μm thick thermal oxide is used as a mask on both sides of the wafer for etch-
ing the through wafer vias (Fig. 11.22a). The deep silicon etch is performed by
etching halfway through the wafer from both sides. In this manner, it is possible to
achieve a via with a 20:1 aspect ratio (Fig. 11.22b). With the oxide mask remaining
in place, the silicon is boron doped to fabricate a pn-junction (Fig. 11.22c). Next,
the vias are filled with polysilicon (Fig. 11.22d) that is etched back to clear the
oxide via mask and the vias (Fig. 11.22e). The oxide is repatterned to form boron
doped junctions on the front and back surfaces of the wafer. After the oxide mask is
etched, a mask pattern is used to form isolated ohmic contacts by implanting phos-
phorus (Fig. 11.22f). The fabrication process is completed by liftoff patterning of
Au contacts on the doped junctions (Fig. 11.22g).
In this process, they were able to achieve a 0.05 pF parasitic capacitance with a
reverse-biased (10 V) pn-junction. This compares to 0.28 pF for a metal-insulator-
semiconductor (MIS) isolation system. The series resistance was 900 and the
leakage current was measured to be 7 nA.
Fig. 11.22 Through wafer interconnect fabrication process using isolated polysilicon vias
11 Wafer Bonding 861
A second through via process used a high-density low pressure (HDLP)
SF6/C4F8plasma to create via holes through a p-type, 4 in., 525 μm thick, 10
cm, double-side polished silicon wafer. The via holes were square with dimensions
of 30 μm/side, which resulted in an aspect ratio of 17.5:1. A 1 μm thick thermal
oxide was grown at 1100◦C for an isolation layer. A 1.5 μm thick low pressure
chemical vapor deposited (LPCVD) polysilicon was deposited as an adhesion layer
for a subsequent copper layer that had poor adhesion to the thermal oxide. Next a
250 nm CVD copper layer was deposited as a seed layer for the 6 μm thick electro-
plated copper. The through wafer interconnect resistance was further reduced by the
6μm thick electroplated copper with a sheet resistance of 2.8 m/cm. This process
resulted in vias with ultralow resistance of 50 m/via.
Following the thick Cu deposition, a 7 μm thick photoresist (Shipley PEPR 2400)
was electroplated for the subsequent patterning of the Cu and polysilicon. The Cu
and polysilicon were wet etched and dry etched in SF6plasma, respectively. Finally
the electroplated photoresist was removed to expose the isolated vias.
The process used to develop through wafer interconnects for MEMS applications
is based on etching high-aspect-ratio holes through the silicon wafer, depositing an
insulation layer, and depositing a conductive layer. The insulation layer will provide
electrical isolation of the conductive vias from the silicon wafer.
It was demonstrated in a process with 50, 75, 100, and 200 μm diameter vias
through a 525 μm thick 4 in. p-type, <100> silicon wafer. The vias were pat-
terned with a thick photoresist (AZ 4620 at 20 μm thick, and AZ 400 K developer)
(Fig. 11.23) and etched with a deep inductively coupled plasma etcher (Fig. 11.23b).
Then PECVD silicon dioxide was selected for the isolation layer (Fig. 11.23c). It
was deposited by sputtering because of the improved step coverage. The silicon
Fig. 11.23 Through wafer via process
862 S.J. Cunningham and M. Kupnik
dioxide was deposited to approximately 7000 Å, which is difficult to measure on
the sidewalls because of the surface roughness.
The conductive layer was demonstrated by two approaches. In the first approach,
a thin aluminum was sputtered from both sides of the wafer to achieve 1 μmon
the surface and approximately 2000 Å on the sidewall (Fig. 11.23d). In the sec-
ond approach, copper was electroplated as the conductor. This required 1500 Å
of titanium to be deposited first as an adhesion layer between the copper and the
silicon dioxide. The copper and titanium patterning was completed by etching in
H2O(80%) +H2SO4(10%) +H2O2(10%) and in H2O(90%) +HF(10%) to remove
the copper and titanium, respectively (Fig. 11.23e).
The primary goal of the next process (Fig. 11.24) was to improve the resistance
and parasitic capacitance of through wafer interconnects. The improvements are
in direct comparison to the dielectric isolated metal or polysilicon and to the pn-
junction, reverse-biased through wafer interconnects. The improvements will come
from air gap isolated interconnects.
The process begins in a typical fashion for etching deep high-aspect-ratio vias
through a silicon wafer. First, a 1.2 μm thermal oxide is grown and patterned to
be used as deep silicon etch mask (Fig. 11.24a). Also, the thermal oxide provides
isolation between the metallized via and the silicon substrate. In addition, a thick
Fig. 11.24 AirisolationTWIprocess
11 Wafer Bonding 863
photoresist (16 μm AZ9260) is deposited and patterned as the deep silicon etch
mask (Fig. 11.24b). Similar to other processes, the deep RIE is performed from the
topside and backside to define a high-aspect-ratio through wafer via (Fig. 11.24c,d).
The topside and backside etches were both targeted for 150 min to etch 250 μm
deep. Following the via etch, the thick photoresist is stripped.
The via interconnects are fabricated by doping the via silicon with boron during
a 6 h diffusion process that produces a 12–15 μm p++ region (Fig. 11.24e). The
next steps are associated with fabricating metal electrical contacts to the p++ inter-
connect (Fig. 11.24f). First, a Cr–Au seed layer is deposited for electroplating an
8–10 μm thick Ni contact layer. An alternate DRIE is performed to create isolation
between the p++-doped interconnect and the substrate (Fig. 11.24g). The isolation
is enhanced by an anisotropic wet silicon etch (EDP, TMAH, or KOH) to complete
the air gap isolation (Fig. 11.24h).
The University of Michigan design/process achieved a 27 series resistance
(this compared to calculated 4. series resistance that was attributed to necking of
the doped interconnect) and a 10 fF parasitic capacitance. The parasitic capacitance
is dominated by the Ni contact frames that couple to the silicon substrate through
the 1.2 μm thick oxide.
11.7 Characterization Techniques for Wafer Bonding
The characterization of the wafer bond is either destructive or nondestructive.
Nondestructive techniques include imaging techniques to examine the bond inter-
face or to evaluate voids in the bond interface that are distributed across the wafer.
Destructive techniques include cross-section analysis and bond strength evalua-
tion. The nondestructive techniques can be used as an in-process or end-of-line
evaluation. The destructive techniques are used at end-of-line. The assessment of
bond quality includes defect rate, bond strength, stresses [77], bond energies [78],
hermeticity (if used for packaging), materials, and harsh environments [79].
The nondestructive imaging techniques include optical microscopy, infrared
microscopy, acoustic microscopy [80], white light interferometry, secondary ion
mass spectroscopy (SIMS), transmission electron spectroscopy (TEM), multiple
internal reflection spectroscopy [81], and X-ray topography. Optical microscopy
will require one of the wafers to be optically transparent so that defects, voids
[82,83], and contaminations can be identified through one wafer to the interface.
Optical microscopy is an efficient and inexpensive means of inspection. The infrared
imaging mounts the bonded wafers (transparent to IR such as silicon) above an IR
source and in the path of an IR-sensitive camera. Interfacial bond defects will show
up as changes in contrast in the IR image and appear to have a “Newton’s rings”
pattern. The resolution of this technique is limited to about 1
/4of the wavelength of
the IR source. For the typical source this resolution is several mm. This technique
will not identify voids that are identified by other techniques. IR imaging resolution
is further limited by high doping levels, IR absorbing films, and by rough surfaces.
864 S.J. Cunningham and M. Kupnik
The advantage of IR imaging is its speed, simplicity, and low cost to implement and
perform. The increased resolution is obtained at the expense of cost and speed.
Ultrasound or acoustic microscopy uses the propagation properties of a sound
wave in the bonded materials. The measurements are made in water or other liquids
and are relatively expensive to make. The propagation and scattering of the acoustic
wave depends on the elastic properties of the materials, which distinguishes the
bonded wafers and any voids that are present. The measurement resolution of the
acoustic microscopy depends on the measurement frequency but it is in the range of
10 μm.
X-ray topography is an expensive and time-consuming method when compared
to other techniques that are used to image cross-sections to examine distortion or
defects in lattice planes. It is applied to single crystalline materials and has a typical
resolution of 2–20 μm.
Two destructive techniques include interface etching [84] and cross-sectional
analysis. With interface etching, one wafer is sacrificed by etching until the interface
or selective etch stop is reached. Once the interface is reached, voids and defects can
be visually inspected. This is a common approach with SOI wafers. Cross-sectional
analysis is usually performed in conjunction with a scanning electron microscope
(SEM) or transmission electron microscope (TEM) to image the bond interface. For
access to the bond interface the wafers are cleaved to expose the bonded interface by
using a focused ion beam (FIB). The image of the bonded interface can be further
enhanced by a defect etch to enhance the void.
Bond strength characterization is measured by a number of techniques that
include the pressure burst test, tensile test, shear test, bending test, and the razor
blade test (knife edge test). The tensile and shear tests are performed on prepared
samples of a specific area. The tensile test uses mounts to the two wafer surfaces to
load the sample perpendicular to the bond interface. The maximum load at failure or
the maximum stress, which is the maximum load divided by the sample area, is used
as the failure criterion. The shear test is similarly constructed but the load is applied
to the two wafers so that it acts parallel to the bond interface. The shear failure is
characterized by the maximum shear load or by the maximum shear stress, which is
the maximum shear force divided by the bond area tested.
The tensile/shear test has certain challenges relative to implementation and char-
acterization. The first challenge is the isolation of loading conditions. Without due
care and even with due care, it is possible to have torsion and bending loads that
are superimposed on the tensile (shear) load. The superposition of these and other
loading stated causes the sample to fail differently and at a lower load compared
to the simple tensile load. The second challenge is stress intensifiers that increase
the stress locally during the tensile test. It is the local maximum stress rather than
the area averaged stress that leads to failure and propagation of an interface crack. A
third challenge is the characteristics of the failure that include the propagation of the
failure. If the crack propagates into one of the wafers or travels some distance along
the bond interface then turns into one of the wafers, it is not directly measuring the
strength of the bond.
11 Wafer Bonding 865
The knife edge test uses a blade of specified thickness that is inserted directly
into the bond interface where a crack has been initiated. As the blade is inserted the
length of the opening between the two wafers (crack length) is measured using an
imaging technique to estimate the surface energy from the blade thickness, crack
length, and elastic modulus of the wafers. The surface energy scales as the fourth
power of the crack length; that is, uncertainties in crack length are magnified four-
fold. The crack length has been observed to be time- and humidity-dependent so
conditions must be carefully monitored. One challenge of the knife edge test is
using it to characterize a strong bond where it is difficult to insert the knife edge
without a crack propagating into one of the wafers (chipping).
The four-point bending test is performed on a sample that has a precrack started
in one of the wafers. The precrack can be started by etching or sawing. When the
sample is loading under four-point bending conditions, the precrack is expected to
propagate into the weak interface of the bond. The load versus displacement is used
to calculate the elastic energy and the surface energy of the bond.
Quantitative approaches have been developed through shear and tensile testing of
bonded dies (Nese and Hanneborg [85], Obermeier [86], DeReus and Lindahl [87],
Kubair and Spearing [88], and Tatic-Lucic et al. [89]) or burst pressure testing of
bonded cavities (Stratton et al. [90]). Niklaus et al. [9] reviewed these techniques for
the evaluation of adhesive bonds. These tests usually result in the load or pressure at
failure, which is not broadly applicable as a failure criterion because it depends on
the specimen size, geometry, and type of loading. Although the loading conditions
are simple, the stress state at the interface corner where fracture initiates, is quite
complex. This complexity of the interfacial loading has been argued by Madou [91]
to be a negative attribute of the tests because they fail to “yield information about
the detailed nature of the bond.” Another approach, the blasé test, is used to deter-
mine the interface surface energy. It was argued by Madou [91] to be advantageous
because it creates a well-defined interfacial loading.
In the blade test (Maszara et al. [92]), a thin blade is inserted into the interface
between two bonded wafers to propagate a crack. The blade test was approximated
by replacing the blade with patterned lines of varying pitch as demonstrated by
Tatic-Lucic et al. [89]. The elastic energy in the system is varied and correlated with
the surface energy required to produce a bond within the spaced lines. Based on the
extracted bond surface energy, the differences between different process variations
have been compared.
Elastic interface fracture mechanics applied to the fracture of silicon–glass
anodic bonds was attempted by Hurd et al. [93], and Go and Cho [94]. The appli-
cation of interface fracture mechanics is based on a crack propagating along the
interface. One challenge of interface fracture mechanics is the resulting crack does
not propagate along the interface, but turns away from the interface into the glass.
Another anodic bond fracture specimen was demonstrated by inserting a thin metal
blade between the silicon and glass prior to bonding [94]. In each case, an attempt
was made to apply interface fracture mechanics, but this was problematic and not
valid because often the crack does not propagate along the interface. Chen et al.
866 S.J. Cunningham and M. Kupnik
[95] have examined the effect of morphology on bond strength for copper wafer
bonding.
Another approach is to correlate fracture initiation at the silicon–glass interface
corner with a critical value of the stress intensity calculated from a linear elastic
stress analysis. In the spirit of the interface fracture mechanics this approach is
intended to be universal (independent of bond size) and can be used to design a
variety of different reliable bonds. It is guided by application to adhesively bonded
butt joints (Reedy and Guess [96–98]), homogeneous acrylic (Dunn et al. [99]), and
etched silicon microstructures (Suwito et al. [100]). This approach is valid for other
homogeneous or heterogeneous wafer bonded structures that are produced using any
of the processes described previously as proposed by Dunn et al. [101], Labossiere
and Dunn [102], and Labossierre et al. [103].
11.8 Existing Wafer Bonding Infrastructure
In his 1998 review, Schmidt [10] saw the primary driver for wafer-to-wafer bond-
ing to be the enablement of wafer-level packaging followed by the fabrication of
microstructures and the fabrication of heterogeneous starting wafer material. In the
meantime one might add the emerging need of 3-D IC integration, such as for high-
density memories. Schmidt [10] outlined several areas where continued progress
was needed in order to realize the full potential of wafer-to-wafer bonding. One of
these areas was to have a healthy infrastructure of equipment vendors and bonding
services that supply wafer bonding equipment solutions.
In the meantime, there is such a infrastructure available. For beginning R&D
purposes one can choose wafer bonding services to test the feasibility of a MEMS
fabrication process that requires wafer bonding. We provide a list for such services
in Section 11.8.1. Several tool vendors are available that provide state-of-the-
art wafer bonding tools. Most equipment offered provides an automatic/robotic
interface for handling wafers and automatic wafer-to-wafer alignment, the auto-
matic contacting of the wafers, and the recipe for a process in terms of pressure,
voltage, temperature, time (ramp up, hold, ramp down, anneal), and ambient envi-
ronment (vacuum, dry nitrogen or other inert gas). In Section 11.8.2 we provide an
overview of available wafer bonding tool vendors and discuss some aspects of their
systems.
11 Wafer Bonding 867
11.8.1 Wafer Bonding Services
Table 11.5 Wafer bonding service providers
Company information Principle services
Applied Microengineering, Ltd.
173 Curie Ave
Didcot Oxfordshire OX11 0QG
United Kingdom
www.aml.co.uk
Wafer Size: 50–200 mm
Processes: FB, AN, AB, DS, MM, TC
Materials: Silicon, CW, Glass
Dalsa Semiconductor
18 Airport Blvd.
Bromont, Quebec, Canada
J2L 1S7
www.dalsasemi.com
Wafer Size: 100–150 mm
Processes: FB, AB, DS, MM, TC
Materials: Silicon, Glass, CW, CMOS
Innovative Micro Technology
75 Robin Hill Road
Santa Barbara, CA 93117
www.imtmems.com
Wafer Size: up to 150 mm
Processes: FB, AN, AB, TC, Eutectic, Glass Frit
Materials: Silicon, Glass
TWV: Yes
Integrated Sensing Systems
(ISSYS)
391 Airport Industrial Drive
Ypsilanti, MI 48198
www.mems-issys.com
Wafer Size: 100–150 mm
Processes: FB, AN, DS, Glass Frit
Materials: Silicon, Glass
Silex Microsystems
Bruttovägen 1, SE-175 26
Järfälla, Sweden
www.silexmicrosystems.com
Wafer Size: 150 mm, 200 mm
Processes: FB, AN, AB, DS, TC
Materials: Silicon, Glass
TWV: Yes
Ziptronix Inc.
800 Perimeter Park Dr., Ste B
Morrisville, NC 27560
www.ziptronix.com
Wafer Size: to 300 mm
Processes: FB,
Materials: Silicon, CW
11.8.2 Bonding Tool Vendors
In addition to existing wafer bonding services (Table 11.5), there is a healthy
infrastructure of wafer bonding vendors available from which to choose. We have
identified four companies that sell state-of-the-art bonding tools. Thus, there is
a multifaceted product portfolio available. Depending on the needs for academia
or industry, one can choose from manually operated tabletop systems up to fully
automated systems that perform cleaning, surface activation, wafer alignment, and
bonding including postbonding inspection (IR), in a closed environment inside the
bonding tool itself. Almost every tool supports all bonding methods that we have
868 S.J. Cunningham and M. Kupnik
discussed in the previous sections for various substrate sizes, but there are different
aspects in specialties of each of these tools. To give a first overview, we briefly
introduce these companies (in alphabetical order) with some examples and aspects
of their tools. Each company provided photos for the shown figures, company
descriptions, and tool specifications for that purpose.
11.8.2.1 Applied Microengineering Ltd (AML), UK
The company AML offers wafer bonding machines (Fig. 11.25a) capable of in situ
alignment under vacuum and elevated temperature, surface activation, and bonding.
The target markets are the MEMS, IC, and III-V industries. The tools offer high
throughput, because pumpdown, heating, and alignment are performed in parallel,
speeding up the bonding time per wafer.
The supported wafer sizes range from 2 to 8 in. The alignment tolerance is spec-
ified to be 1 μm and the unique XYZ-Theta alignment mechanism (Fig. 11.25b,d)
allows a large distance between the bonding surfaces before the bond (surface
activation and outgasing) without contacting the surfaces with flags or spacers.
Top lid of bonding
chamber
(a)
(b)
(d)
Optics for
alignment
During In-Situ
Radical Activation
XYZ-Theta
manipulation for in
chamber alignment
Large gap between top
and bottom chuck possible
(c)
Fig. 11.25 (a) AML’s versatile wafer bonding platform (2–8 in.), which features alignment,
activation, bonding, in situ UV curing, all in the same chamber without any handling steps
between. (b) Bonding chamber from inside. (c) Tool during in situ radical activation for room
temperature bonding; (d) Alignment optics (cameras) (Photos and drawings courtesy of Applied
Microengineering Ltd. (AML), UK)
11 Wafer Bonding 869
Upgrades for in situ radical surface activation, featuring room temperature direct
bonding, are available (Fig. 11.25c), as well as the capability of in situ high-accuracy
alignment with UV cure using UV LED array inside the chamber. Another upgrade
is available for polymer embossing, imprinting, NIL, and other pattern transfer
techniques. The machines have the flexibility for R&D and the throughput and
automation for volume production as well. All wafer bonding types are supported.
Stacks of up to 8 mm can be bonded.
11.8.2.2 EV Group (EVG), Austria
The company EVG offers several types of wafer bonding tools for the MEMS,
3-D–IC integration, and advanced packaging, as well as the compound semiconduc-
tor industries. The systems accommodate the demanding applications by bonding
under high vacuum, precisely controlled fine vacuum, temperature or high-pressure
conditions. EVG’s tools support a wide variety of bonding processes such as anodic,
thermocompression, glass frit, eutectic, diffusion, fusion, solder, adhesive, and UV
bonds. Based on a modular bond chamber design, the systems can be configured for
R&D, pilot line, or high-volume production.
A maximum level of automation and process integration is achieved by EVG’s
GEMINI R
platform (Fig. 11.26). The automated production wafer bonding systems
Bond module
EVG s production
wafer bonding
Fig. 11.26 The GEMINI R
is EVG’s production wafer bonding platform with up to four bond
chambers for high throughput. The system is also available with more than four bond chambers
and it supports wafer sizes up to 300 mm. The wafers first go through wafer surface preparation
modules (plasma and cleaning), then to the SmartView R
face-to-face-bond alignment module
before the wafers are loaded into the bond chamber (bond module) (Photos courtesy of EV Group
(EVG), Austria)
870 S.J. Cunningham and M. Kupnik
for high-volume applications support wafer-to-wafer alignment and wafer bonding
processes with up to four bond chambers in parallel for high throughput. EVG’s
patented SmartView R
face-to-face-bond aligner and various preprocess modules
for wafer sizes up to 300 mm are available. Furthermore, for postbonding inspection
compatible metrology equipment, such as IR inspection, is offered as well. EVG
introduced and focuses on the concept of separation between wafer alignment and
bonding.
11.8.2.3 Mitsubishi Heavy Industries Ltd. (MHI), Japan
The target market of Mitsubishi’s latest 200 mm bonding tool (Fig. 11.27a)is
the integration of CMOS and MEMS wafers. The tool allows performing direct
bonding at room temperature for various material combinations, as illustrated by
the examples shown in Fig. 11.27b–i.
+ +
++
+
Dangling bonds
Activation Activated Surface After Bonding
Ion Beam Oxide
(f) (g) (h) (i)
(d) (e)
(b) (c)
(a)
(j)
Fig. 11.27 (a) Mitsubishi’s MWB-08A fully automated room temperature bonding machine for
8 in. wafer. Examples: (b)Si–Si;(c) Quartz–quartz; (d) GaAs–GaAs; (e) MEMS device; (f)Au–
Au; (g) LiNbO3–Si; (h) vacuum leak test sample; and (i) Al TSV bonding. (j) Operation principle
of room temperature bonding with ion beam under high vacuum conditions (Photos courtesy of
Mitsubishi Heavy Industries Ltd. (MHI), Japan)
11 Wafer Bonding 871
The achieved bonding strengths are comparable to those of the base material
with the advantage that no heat treatment is required. The technology is based on a
sophisticated surface activation step under high vacuum conditions. The disclosed
main steps (Fig. 11.27j) are as follows. Oxide and other absorbed substances are
removed from the wafer surface under high vacuum conditions by means of ion
irradiation. This creates a highly reactive surface (dangling bonds), which then can
be bonded at room temperature to another wafer.
For research and development, a semiautomatic model is available as well. The
fully automated room temperature bonding machine for 8 in. wafers (Fig. 11.27a)
features an alignment tolerance of 2 μm and a powerful bonding unit that features
up to 100 kN force for metal–metal bonding. The degree of vacuum is 1 e–5 Pa.
11.8.2.4 SUSS MicroTec AG, Germany
SUSS MicroTec provides wafer bonding solutions for the R&D and low- and high-
volume production needs of customers in the MEMS, semicompound/LED and
Cool plate
module
Plasma
module
Align module Bond module
Inspection module
SUSS MicroTec s
CBC200 wafer
bonding cluster
system for the
MEMS market
Cleaning module
Fig. 11.28 SUSS MicroTec’s CBC200 wafer bonding cluster system for MEMS market with
process modules available. Listed are the modules the wafers run through from surface cleaning
and conditioning, through aligning and bonding, finishing with cooling and postbond metrology
(Photos courtesy of SUSS MicroTec AG, Germany)
872 S.J. Cunningham and M. Kupnik
3-D industries. The CBC200, featuring interchangeable modules to accommodate
evolving process and production requirements, is SUSS MicroTec’s 200 mm fully
automated production wafer bonder platform for customers in the MEMS and 3-
D industries (Fig. 11.28). SUSS MicroTec’s bond modules have a closed bond
chamber design for a contamination-free bonding environment. Wafers are loaded
through a slot door and then the chamber is sealed throughout the bond process. The
chamber is purged with nitrogen to keep moisture and particles out, reducing cycle
time and cost. A gas overpressure up to 3 bars can be used to dampen the motion of
accelerometers or other sensitive MEMS devices. The tool can be configured with a
bond chamber that is ideal for glass frit, anodic, and direct bonding, or with a bond
chamber that is ideal for providing high forces necessary for thermo-compression,
eutectic, metal–metal bonding, and so on.
Further features of the bond module are: a pressure column technology (patent
pending) that evenly distributes the force across the bond interface to ensure force
uniformity, and multizone vacuum isolated heaters (patent pending) for temperature
uniformity.
In addition to its wafer bonding capabilities, the CBC200 has highly advanced
bond aligner modules, which utilize face-to-face ISA, TSA (topside), or BSA
(backside) alignment methods for flexible and precise alignment capability.
11.9 Summary and Outlook
In the last decades, wafer bonding has served as one of the dominant tools in the field
of microfabrication. Not only can it be seen as an enabling technology for the field
of MEMS, it also pushes 3-D–IC integration technology and the compound semi-
conductor industry forward, and, thus, will be an integral part of the semiconductor
industry in the future.
Wafer bonding is best known for advanced wafer-level packaging applications
for various fields, such as sensors. It is accepted that often the packaging cost on a
chip level is the highest cost of the product.
Wafer bonding is often the only approach to fabricate specific MEMS devices,
mainly because bridging large gaps with sacrificial release methods is often imprac-
tical if not impossible. A good example is the fabrication of micromachined pressure
sensors or capacitive micromachined ultrasonic transducers for lower frequencies
needed for airborne applications, just to name two examples.
It is essential that the MEMS product engineer is fluent in all aspects of wafer
bonding. Only then can the best fabrication process for a certain problem statement
be found and the best equipment chosen for a certain fabrication task. The infras-
tructure and knowledge are available in the form of commercially available bonding
equipment, wafer bonding service, and the literature.
Wafer bonding is still being heavily researched to improve the technology. One
good example is the recent progress in providing commercial wafer bonding tools
that allow reliable direct wafer bonding without any heat treatment. The value
11 Wafer Bonding 873
in such technology lies in the fact that heat treatment can cause problems when
different materials are direct bonded due to different thermal expansion coefficients
or thermal budget limits such as found in IC circuitry. Such tools will extend the
range of possible material combinations, and, thus, open the door to new applica-
tions. It will be only a matter of time that all wafer bonding tool vendors provide
such additional features in their product palette.
Acknowledgments We thank Prof. Roger Howe, Prof. Pierre Khuri-Yakub, and Dr. Eric
Perozziello, Stanford University, for many fruitful discussions and their support. We also thank
Dr. Robert Rhoades, Entrepix Inc., Dr. Aaron Partridge, SiTime Corporation, and Dr. Steve Vargo,
ST Systems USA Inc., for valuable feedback on CMP, direct hand bonding, and HF vapor etching,
respectively.
In addition, the authors acknowledge the employees from the bonding tool vendors that pro-
vided technical specifications, feedback, and/or provided photo material for Section 11.8.2. These
are Rob Santilli, from Applied Microengineering Ltd; Paul Maciel, from Optical Associates Inc.;
Kensuke Ide, from Mitsubishi Heavy Industries Ltd.; Garret Oakes and Renae Bellah, from
EV Group Inc.; and Kristin Connors, Jim Hermanowski, and Sabine Radeboldt, from SUSS
MicroTec AG.
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