V. Bharath Sreenivasulu

Indian Institute of Technology Patna | IIT Patna

In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire field-effect-transistor (FET) for significantly enhanced performance at sub-5 nm nodes. The symmetric and asymmetric spacer lengths are optimized and compared towar...

In this article, FinFET, vertically stacked gate-all-around (GAA) nanowire (NW), and nanosheet (NS) FETs performance are estimated with equal effective channel widths ( ${W}_{eff}$ ) at the 5-nm technology node (N5). The comparison reveals that NS FET exhibits the highest ON current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ), the lowest OFF curr...

In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In JL mode, the ON current ( $I_{\mathrm {ON}}$ ) rises with an increase in temperature compared to the downfall trend in INV mode. In addition, compared to JL mode, the INV mo...

The DC and RF assessment of critical barrier-AlGaN/GaN nano channel tri-gate fin-shaped High Electron Mobility Transistor (FinHEMT) is investigated for Enhancement-mode (E-mode) operation. We propose and analyze critical barrier layer (CBL) and critical-strained barrier layer (CSBL) FinHEMT for a fixed fin-shaped channel width (W fin = 160 nm) and...

In this study, for the very first time developing of n- and p-type 3-D single-channel (SC) FinFET and Multi-Bridge-Channel (MBC) gate-all-around (GAA) FETs are benchmarked on both the device and circuit levels and compared to the IRDS for sub-5-nm technology nodes. The performance of FinFET, nanowire (NW) and nanosheet (NS) FETs are compared at the...

In this article, the comparison of nanosheet (NS) FET, CombFET, and TreeFETs at advanced technology nodes is performed. Initially, the DC metrics like I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/19...

Tree-shaped Nanosheet FETS (NSFET) is the most dependable way to scale down the gate lengths deep. This paper investigates the 12nm gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) n-type Tree-shaped NSFET with the gate having a stack of high- k dielectric (HfO <sub xmlns:mml="...

This work investigates the effect of single and dual- k spacer materials consisting of different dielectric constants ( k ) in optimized nano-channel gate-stack nanosheet (NS-FET) employing hafnium oxide and silicon dioxide as gate insulator to improve its sub-threshold performance. The effect of the external low-k spacer modification in the dual...

Moore's law claims that recent technological developments have already resulted in a significant rise in the number of transistors on a chip. By switching from a conventional MOSFET built with a single control gate to one with numerous control gates, the device's manageability has been significantly improved. Apart from this dielectric spacer plays...

This manuscript demonstrates the performance comparison of vertically stacked nanosheet field-effect transistor (FET) with various high-k materials in gate stack (GS) configuration. As the high-k dielectric materials are inevitable to continual scaling, high-k dielectric materials such as Si3N4, Al2O3 and HfO2 are incorporated in the GS, and the pe...

In this paper, for the first time, the performance of 3-D Nanosheet FETs (NSFETs) is reported in the inversion (INV), accumulation (ACC), and junctionless (JL) modes at elevated temperatures. The performance comparison is demonstrated at both device and circuit levels. It is observed that, as the temperature increases from 250C to 2000C, a decremen...

Moore's law states that the technical innovations are being absorbed already. The device's controllability has dramatically improved since moving from a straightforward metal oxide semiconductor field effect transistor (FET) constructed with a single control gate to one with many control gates. Here, the device-level simulation of vertically stacke...

In this paper, multi-channel nanowire (NW) performance is significantly improved by symmetric and asymmetric spacer length optimization. Device performance metrics including ON current (ION), OFF current (IOFF), and switching ratio (ION/IOFF) are improved by careful optimization of spacer length. It is observed that the NW FET exhibits the best per...

For the first time, a nanosheet field effect transistor (NS FET) performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly-doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET wi...

The impact of scaling on the gate all around the nanosheet field effect transistor (NSFET) was studied in detail at sub-5-nm nodes for digital and analog/RF applications. When LG is scaled from 20 to 5 nm, ION is improved by 2.1×, IOFF increases by three orders of magnitude, SS increases by 27%, DIBL is increased by 4×, and a Vth roll off of 41 mV...

Direct current, analog/radio frequency device, and circuit applications of nanosheet (NS) field effect transistors were investigated. To enhance power performance, co-optimization geometry parameters like NS width (NSW) and NS thickness (NSH) are varied for high-performance and low-power applications. A rise of 1.47x in ION and a rise of 5.8x in IO...

Nonlinearity operation and early gain suppression limit the high‐frequency operation of GaN‐HEMTs. Nonlinear transconductance and resistance drop‐off at relatively large VGS are the major sources for the nonlinear operation of the high electron mobility transistors (HEMTs). In this article, we present the In0.1Ga0.9N channel‐based HEMTs for stable...

Nanosheets are the revolutionary change to overcome the limitations of FinFET. In this paper, the temperature dependence of 10 nm junctionless (JL) nanosheet FET performance on DC and analog/RF characteristics are investigated for the first time using extended source/drain and with high-k gate stack. The detailed DC performance analysis like transf...

This certificate is awarded to for serving as a reviewer for Thank you for reviewing 2 manuscripts in 2021 2 March 2022 Date Prof. Haiwen Liu Editor V. BHARATH SREENIVASULU International Journal of RF and Microwave Computer-Aided Engineering

An approximate carry select adder (CSLA) with reverse carry propagation (RCSLA) is showed in this work. This RCSLA was designed with reverse carry propagate full adder (RCPFA). In RCPFA structure, the carry signal propagates in the reverse direction that is from MSB part to LSB part, then the carry input has greater importance compared to the outpu...

Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless SOI FinFET by different spacer engineering techniques with hafnium based (HfxTi1-xO2) high-k dielectric in the gate stack. The device process parameters like dielectric spacer im...

The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (A...

Fault-tolerant systems are needed for reliable operation in the presence of faults. The concurrent error repairable adder can itself repair the faults which are present in the circuit. In this paper, two new concurrent error repairable carry select adders (CSLAs) are proposed. The proposed concurrent error repairable CSLA I detects and repairs the...

Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. Si NS MOSFETs provide high current drivability due to wider effective channel (Weff) and maintain better short channel performance. Here, the perfo...

Silicon (Si) ultrathin junctionless (JL) n-FinFET with LG = 3 nm and 1 nm are explored for the first time by invoking HfxTi1-xO2 based high-k gate dielectric. The 3D device performance analysis is carried using self-consistent Poisson and Schrödinger equations based on a non-equilibrium Green’s function (NEGF) approach. The result analysis ensures...

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC metrics like SS, DIBL, ION/IOFF ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barr...

In this paper we have performed scaling performance of asymmetric junctionless (JL) SOI nanowire FET at 10 nm gate length ( L G ). To study the device electrical performance various DC metrics like SS, DIBL, I ON / I OFF ratio are performed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = 64 mV/dec, drain indu...

We demonstrate junctionless (JL) n-channel SOI nanowire FET with asymmetric spacer at nano regime. The impact of various spacer dielectrics on device performance is presented and various electrical characteristics are analyzed. The gate length ( L G ) scaling impact of the asymmetric spacer with various spacers on I ON , I OFF , and I ON / I OFF is...

Multi‐fin devices are the most reliable option for terahertz (THz) frequency applications at nano‐regime. In this work impact of spacer engineering on multi‐fin SOI FET performance is evaluated by invoking single low‐k (Air), high‐k (Si3N4, HfO2), and hybrid dual‐k (Air + Si3N4) spacer in the underlap section at nano‐regime. The simulation study re...

In this paper, for the first time, we have investigated the DC and analog/RF performance metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using HfxTi1-xO2 high-k material in gate stack to improve subthreshold characteristics. The 3-D device performance of single-k, dual-k, and hybrid spacer is compared without spacer dielectric, a...

Nano-sheets are the revolutionary change to overcome the limitations of FinFET. In this paper, the temperature dependence of 10 nm junctionless (JL) nano-sheet FET performance on DC, analog and RF characteristics are investigated for the first time using extended source/drain and with high- k gate stack. The detailed DC performance analysis like tr...

In this paper, we have studied the impact of various dielectric single-k (S-k) and dual-k (D-k) spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric oxide based (HfxTi1−xO2) gate stack to enhance the sub-threshold performance of the device. Performance impact of outer low-k spacer variation on D-k spacer by fixing...

Redundant Based Multiplier Over Galois Field(GF(2 m)) have gained huge popularity in elliptic curve cryptography (ECC) mainly because of their negligible hardware cost for squaring and modular reduction. In this paper, we have proposed a novel recursive decomposition algorithm for RB multiplication to obtain high-throughput digit-serial implementat...