Trudo Clarysse

imec · Materials and Component Analysis

Focused ion beams (FIBs) are widely applied during manufacturing and for failure analysis, as a preparation tool for cross sectional scanning electron microscopy or for the extraction of lamellae for (scanning) transmission electron microscopy investigation of nanoelectronic devices. The impact of the ion beam milling on surface contamination is in...

Uniaxial stressors have received much interest over the last few years as a method to enhance carrier mobility and, hence, drive current with minimal modification to the structure of the transistor. However, the shift in device design to complex structures with multiple crystallographic orientations like advanced bulk-FinFETs has significantly comp...

In this paper, we illustrate how high-resolution 2-D carrier profiles from scanning spreading resistance microscopy (SSRM) can be used to predict and understand device performance of dynamic random access memory peripheral transistors with high-k metal gate and ultrashallow junctions. In an earlier study on high-speed complementary metal–oxide–semi...

Electrical nanoprobing inside scanning electron microscopy (SEM) systems has become a routinely used characterization technique for electrically measuring prototypes of the most advanced nanoelectronics device structures. Tungsten wire needles with a sharpness of about 50-100 nm are commonly used as probe tips in these measurements. They suffer unf...

A method and system for optically determining a substantially fully activated doping profile are disclosed. The substantially fully activated doping profile is characterized by a set of physical parameters. In one aspect, the method includes obtaining a sample comprising a fully activated doping profile and a reference, and obtaining photomodulated...

The accurate determination of the sheet resistance and carrier depth profile, i.e. active dopant profile, of shallow junction isolated structures involving new high mobility materials, such as germanium, is a crucial topic for future CMOS development. In this work, we discuss the capabilities of new concepts based on micro machined, closely spaced...

Interest in Sn-based semiconductors largely increased during the last decade. If doubts remained in the early 2000's on the hypothetical use of (Si)GeSn epitaxial layers in advanced technologies (mainly due to the low Sn solubility in Si and Ge and the associated reduced thermal stability of those alloys), recent publications from various groups pr...

This study presents a broad investigation on Al implantation in crystalline Ge. We show that up to 600 °C, Al does not diffuse and a remarkable electrical activation of ˜1× 1020 cm-3 is obtained. For higher annealing temperatures (from 700 to 800 °C), Al shows a significant diffusion towards the bulk and an unexpected uphill diffusion next to the s...

Therma-Probe® (TP) is widely used in the semiconductor industry for the Statistical Process Control (SPC) monitoring of the various ion implantation steps included in the Complementary Metal Oxide Semiconductor process. This fully optical, hence non-destructive and fast, pump-probe technique measures the probe laser reflectance (DC reflectance) as...

We developed a procedure and software allowing us to predict and understand device performance by incorporating 2D-carrier profiles from high resolution scanning spreading resistance microscopy into a device simulator. We demonstrate the incorporation of the quantified SSRM 2D-profiles into a device simulator using data collected on p-MOSFETs. Base...

Strained Ge pMOSFET GeSn materials Source/drain engineering GeSn thermal budget a b s t r a c t In this paper, we propose the fabrication of whole strained Ge complementary metal–oxide-semiconduc-tor (CMOS) with Ge 1Àx Sn x materials as stressors to outperform the state-of-the-art uniaxial compressive strained Si CMOS. Ge 1Àx Sn x materials have la...

Pyramidal tips made from boron doped diamond have become the ultimate choice for electrically measuring semiconductor device structures in electrical atomic force microscopy (AFM). An advanced measurement setup with diamond probing units directly integrated inside a scanning electron microscopy (SEM) system is highly wanted as this allows for accur...

Published results on Ge junctions are benchmarked systematically using RS–XJ plots. The electrical activation level required to meet the ITRS targets is calculated. Additionally, new results are presented on shallow furnace-annealed B junctions and shallow laser-annealed As junctions. Co-implanting B junctions with F is shown to degrade junction pr...

In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate...

This paper reports the two-dimensional epitaxial growth of thin intrinsic Ge and in-situ doped n-Ge on GaAs substrates by atmospheric pressure chemical vapor deposition. High quality Ge growth on GaAs is activated almost instantly by an optimized pregrowth procedure. Ga autodoping is found to occur within the first Ge monolayers close to the inte...

This work presents the properties and applications of high vacuum scanning spreading resistance microscopy (HV-SSRM) for two-dimensional carrier profiling. Characteristics of this concept in terms of spatial resolution and dopant gradient resolution as well as in terms of concentration sensitivity and quantification procedures are briefly presented...

The accurate characterization of free carrier profiles in ultra‐shallow junctions, such as the source and drain extension regions, is one of the major challenges of metrology in modern silicon Complementary Metal‐Oxide‐Semiconductor technology. Currently, only destructive and time‐consuming techniques, such as Scanning Spreading Resistance Microsc...

Millisecond laser annealing is used to fabricate ultra shallow arsenic junctions in preamorphized and crystalline germanium, with peak temperatures up to 900 degrees C. At this temperature, As indiffusion is observed while yielding an electrically active concentration up to 5.0 x 10(19) cm(-3) for a junction depth of 31 nm. Ge preamorphization and...

The electrical characterization of the source and drain extension regions of complementary metal oxide semiconductor (CMOS) transistors is highlighted in the international technology roadmap for semiconductors (ITRS) as a major challenge for future technology nodes. In practice, there is a clear need for techniques which are simultaneously accurate...

In this study, we report on the device impact related to B pocket diffusion/deactivation using an atomistic kinetic Monte Carlo (KMC) diffusion modeling. An atomistic distribution of B-clusters in nFET channel region is shown. Spike-RTA scaling down to 1000°C for shallow extension formation induces about 10% of B pocket deactivation. KMC reveals th...

Within this paper, the authors propose a refined high vacuum scanning spreading resistance microscopy (HV-SSRM) electromechanical nanocontact model based on experimental results as well as molecular dynamics (MD) simulation results. The formation under the tip of a nanometer-sized pocket of β-tin, a metastable metalliclike phase of silicon (also na...

The authors demonstrated that the combination of VPD and LA enables the fabrication of high quality, defect-free USJs with abrupt dopant profile. The results for PMOS with B-VPD are very promising for the 32 nm and the 22 nm technology nodes. In the case of NMOS, As-VPD and LA enable the fabrication of an USJ but the electrical deactivation of a la...

In this paper, we propose the fabrication of strained Ge complementary metal-oxide-semiconductor (CMOS) with Ge1-xSnx materials as embedded stressors to outperform the state-of-the-art strained Si CMOS. Ge1-xSnx materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Compatibility of Ge1-xSnx (with...

The ITRS Roadmap highlights the electrical characterization of the source and drain extension regions as a key challenge for future complimentary-metal-oxide-semiconductor technology. Presently, an accurate determination of the depth of ultrashallow junctions can routinely only be performed by time-consuming and destructive techniques such as secon...

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 30...

Submelt laser annealing is a promising technique to achieve the required sheet resistance and junction depth specifications for the 32 nm technology node and beyond. In order to obtain a production worthy process, it is important to minimize possible nonuniformities caused by the annealing process both at macroscopic and microscopic levels. In this...

Electrical characterization of ultra-shallow junctions, relying on advanced implant and anneal processes, has received much attention in the past few years since conventional characterization methods fail. With continued scaling of semiconductor devices, the problems associated with conventional techniques will become even more evident. In several...

Earlier work [T. Clarysse , Mater. Sci. Eng., B 114-115, 166 (2004); T. Clarysse , Mater. Res. Soc. Symp. Proc. 912, 197 (2006)] has shown that only few contemporary tools are able to measure reliably (within the international technology roadmap for semiconductors specifications) sheet resistances on ultrashallow (sub-50-nm) chemical-vapor-deposite...

Shallow n+ layers in Ge are formed by phosphorus implantation and subsequent millisecond flash lamp annealing. Present investigations are focused on the dependence of P redistribution, diffusion and electrical activation on heat input into the sample and flash duration. In contrast to conventional annealing procedures an activation up to 6.5×1019 c...

The introduction of millisecond annealing in advanced CMOS process flows turns out to generate considerable temperature variations which can enhance the device dispersion. In the present work we report on the use of inline Therma-Probe (TP) and Micro Four-Point Probe (M4PP) metrology to assess these temperature variations on shallow trench isolatio...

In the present work we report on Therma-Probe (TP) measurements to quantify the residual lattice damage after sub-melt laser annealing for different Ge pre-amorphization implant (PAI) conditions. The calibration of the TP signal, the influence of different laser parameters and the relation to junction leakage is discussed.

In routine scanning probe microscopy (SPM) measurements either the tip is hidden underneath the cantilever and thus the position of the tip is only known with a very low accuracy (>5 μm) or a high aspect-ratio tip is used which is visible but is very fragile. Furthermore, for electrical applications, visible tips are simply coated with a thin layer...

Atomistic modeling and optimized TCAD simulation strategy for Laser-only annealing device are shown. Multiple laser annealing scans are modeled by using atomistic KMC. KMC clarified that dopant diffusion is changed as a function of laser scan number. SSRM with 1 nm special resolution is used for the 2-dimensional carrier distribution measurement an...

We investigated the as-implanted profiles, electrical activation, diffusion, and recrystallization of gallium implanted in germanium samples through the combination of secondary-ion mass spectrometry, transmission electron microscopy, and sheet resistance measurement. Because of their high activation level (4.4× 1020 cm-3) without preamorphization,...

The performance of electronic devices relies crucially on the precise tailoring of their carrier distributions. The earlier widely used conventional spreading resistance probe (SRP) suffers from many limitations for profiling sub-50 run silicon based profiles and is also poorly suited for the new high mobility materials being considered today. In t...

The ITRS roadmap stresses the electrical characterization of the active doping profiles for sub-32 nm structures as a key challenge for future CMOS technology. Earlier work has shown the promising capabilities of non-destructive photomodulated optical reflectance (PMOR) techniques, based on the localized detection of variations in the reflectivity...

In order to fabricate carrier profiles with a junction depth (∼15nm) and sheet resistance value suited for sub-32nm Si-CMOS technology, the usage of sub-melt laser anneal is a promising route to explore. As laser annealed junctions seem to outperform standard anneal approaches, a detailed assessment of the basics of laser induced activation seem ap...

Sub-melt laser annealing is a promising technique to achieve the required sheet resistance and junction depth specifications for the 32 nm technology node and beyond. In order to obtain a production worthy process with minimal sheet resistance variation at a macroscopic and microscopic level, careful process optimization is required. While macrosco...

The formation of ultra-shallow n⁺ layers by P or As implantation and subsequent rapid thermal annealing (RTA) or flash-lamp annealing (FLA) is investigated. The focus is on diffusion and activation of dopants. RTA leads to considerable broadening of the shallow as-implanted profiles by concentration-dependent diffusion. In contrast, FLA...

Accurate characterization of ultra shallow junctions (USJ) is important in order to understand the principles of junction formation and to develop the appropriate implant and annealing technologies. We investigate the capabilities of a new micro-scale Hall effect measurement method where Hall effect is measured with collinear micro four-point probe...

The impact of the Ge pre-amorphization conditions on shallow B profiles, resulting from a 1keV implantation in n-type Ge and a 500°C 1min rapid thermal anneal, is investigated. In general, an increase of the sheet resistance with lower Ge energy is observed. There is some evidence for tail diffusion, enhancing slightly the junction depth and reduci...

As CMOS is approaching the 22nm node, the importance of high-mobility materials such as Ge and GaAs is rapidly increasing. For the timely development of these new technologies accurate dopant and carrier-profiling solutions for source-drain extensions with these materials are required. Identical n-type-doped (Si, Se) layers on same and opposite typ...

In order to reach the ITRS goals for future complementary metal-oxide semiconductor technologies, there is a growing need for the accurate extraction of ultrashallow electrically active dopant (carrier) profiles. In this work, it will be illustrated that this need can be met by the micro four-point probe (M4PP) tool. M4PP sheet resistance measureme...

A key challenge in the engineering of Ge MOSFETs is to develop a proper Ge surface passivation technique prior to high-κ dielectric deposition to obtain low interface state density and high carrier mobility. A review on some possible treatments to passivate the Ge surface is discussed. Another important aspect is the activation of p- and n-type dop...

Maintaining or improving device performance while scaling semiconductor devices, necessitates the development of extremely shallow (< 20 nm) source/drain extensions with a very high dopant concentration and electrical activation level. Whereas solutions based on RTA with cocktail implants have been proposed in previous generations, sub-45 nm techno...

Photomodulated optical reflectance is a well established technique for surface and near surface characterizations. In this work, the nonlinear behavior of the differential reflectance as a function of the pump irradiance (104–106 W/cm2) is studied on uniformly and nonuniformly (p-n/p+-p junctions) doped silicon structures, with a particular emphasi...

Earlier work has clearly shown that only a very few tools are able to measure reliably sheet resistances on advanced complementary metal-oxide semiconductor (CMOS) structures. One of these promising techniques is the junction photovoltage based technique, which uses a modulated light emitting diode to generate, in a millimeter size area of a single...

As indicated by the ITRS roadmap, obtaining accurate information on the electrically active dopant profile for sub-30-nm structures is a key issue. Presently, however, there is no conventional, probe-based (destructive) technique available satisfying the ITRS targeted depth (3%) and carrier level (5%-10%) reproducibility and accuracy. In this work,...

Sheet resistance and leakage current density of spike rapid thermal processed, millisecond flash annealed, and chemical vapor deposition (CVD) grown ultrashallow junctions (USJs) are compared with the contactless junction photovoltage technique for measurement of sheet resistance and leakage current (R_sL) and four-point probe (4PP) techn...

A non-contact method for measurement of sheet resistance and leakage current (RsL) for ultra-shallow junction (USJ) characterization is described based on analysis of frequency-dependent junction photovoltages from p-n junctions . Theoretical, device-simulated and measured photovoltages, sheet resistance as well as RsL and reverse-biased diode curr...

Sheet resistance and leakage current of spike rapid thermal processed (RTP), millisecond flash (fRTP) annealed and chemical vapor deposition (CVD) grown ultra‐shallow junctions (USJ) are compared with a non‐contact junction photovoltage, RsL, technique. Theoretical reverse‐biased diode and non‐contact leakage currents are compared. A significant l...

The constant downscaling of CMOS technology is accompanied by a constant downscaling of transistor junctions. In a few years, electrical junctions will reach a depth of ∼20 nm and the electrical characteristics of these junction conditions the working of a transistor. However, this downscaling has not been followed by a parallel downscaling of the...

We have investigated flash-lamp annealing (FLA) of germanium wafers doped with phosphorous and boron introduced in the crystal by ion implantation. Annealing was performed by using pre-heating at 400–450 °C in a conventional rapid thermal processing (RTP) unit and a fast (3–20 ms) FLA annealing at 800 °C or 900 °C. Diffusion of P is suppressed duri...

Carrier illumination (CI) is a photoelectrothermal modulated optical reflectance (PMOR) technique for the one dimensional active doping profile characterization of ultrashallow junctions. The specificity of CI as a PMOR technique is to exploit the probe differential reflectance nonlinearity as a function of the pump laser irradiance (104–106 W/cm2)...

Without Abstract

Understanding dopant diffusion and activation mechanisms is a key issue for future sub-45-nm CMOS technologies. This understanding requires the availability of accurate chemical and electrically active dopant profiles. In this work we will focus on the accurate and reliable characterization of carrier depth profiles for ultra-shallow (USJ) structur...

The Volterra integral equation of the second kind is approximated by rational predictor-corrector formulas, derived through osculatory rational interpolation. A fourth order method is treated explicitly. Convergence and A-stability are considered. For some nonlinear and singular equations, numerical results are included, and compared with results f...

The in-situ fabrication of rectangular concentration-depth profiles of phosphorus in germanium, with electrically active concentrations approaching 1020 cm-3 is reported. The growth method is atmospheric chemical vapor deposition using germane and phosphine with N2 as carrier gas. Best results have been achieved using a relatively low growth temper...

This paper provides an overview of the current state-of-the-art in the formation of shallow junctions in germanium by ion implantation, covering the issues of dopant activation, diffusion and defect removal. As will be shown, for the case of p+ implantations, the application of rapid thermal annealing (RTA) to B implants yields good sheet resistanc...

Carrier illumination is an optical, fast, and nondestructive technique for an ultrashallow complementary metal oxide semiconductor structure characterization based on the measurement of differential probe laser reflectivity changes, which originate from refractive index variations induced by excess carriers generated by a second modulated pump lase...

As indicated by the International Technology Roadmap for Semiconductors (ITRS) (http://public.itrs.net/), obtaining accurate information on the electrically active dopant profile for sub-30 nm structures is a key issue. Presently, however, there is no conventional destructive (probe based) technique available satisfying the ITRS targeted depth (3%)...

Time evolution of the chemical profile, electrical activity, and regrowth of P implanted in Ge at a concentration above the maximum equilibrium solubility is investigated at 500 °C rapid thermal annealing temperature. During the first anneal, a second, epitaxial regrowth of a part of the amorphous layer leads to P trapping in substitutional sites a...

We have studied implant-induced damage, defect annealing, and recrystallization of B, Ga, P, As, and Sb introduced in Ge by ion implantation at high doses, such that dopant chemical concentrations are above the corresponding solubility in Ge, with energies that target about 100-nm junction depths. It is shown that the amount of damage induced in th...

The carrier illumination (CI) method is an optical nondestructive technique primarily used today for the in-line monitoring of ultrashallow doping profiles in advanced complementary metal oxide semiconductor devices. A CI measurement is basically a differential probe laser reflectivity measurement providing (indirect) information on the underlying...

The accurate and reliable characterization of the sheet resistance of ultra-shallow (USJ) profiles is a key issue in the development of future CMOS technologies. Typically, conventional means, such as in-line four point probe measurements, have a limited accuracy due to the substrate contribution resulting from too much probe penetration, especiall...

We have studied doping profiles, activation levels, and defect annealing of P introduced in Ge by ion implantation at different doses and energy, and annealed under various conditions by rapid thermal annealing. Common to all implant energies, ion-implanted P in Ge exhibits a “box profile” at high implant doses, when a sufficiently high thermal bud...

In order to reach the ITRS goals for future complementary metal-oxide semiconductor technologies there is a growing interest in using germanium as an alternative substrate material in view of its higher mobility. Different species and thermal budgets are presently being investigated in order to determine the most likely candidates for the required...

Passivation of the channel in the gate stack is the most important problem for introducing another material than silicon into the channel of CMOS devices. In order to compare the mobility values of different passivation techniques, we propose to use a parameter, which is a proportional to the drive current of the transistor. We call this parameter...

The formation of shallow junctions in germanium substrates, compatible with deep submicron CMOS processing is discussed with respect to dopant diffusion and activation and damage removal. Examples will be discussed for B and Ga and for P and As, as typical p- and n-type dopants, respectively. While 1 to 60 s Rapid Thermal Annealing at temperatures...

We have investigated diffusion and activation of boron implanted with 6 keV energy to a maximum concentration of 8.0×1020 atoms/cm3 in crystalline germanium (c-germanium) and preamorphized germanium, employing rapid thermal annealing in the range of 400–600 °C. As-implanted boron profiles in preamorphized germanium are shallower than the ones in c-...

N- and p-type junctions were formed in Ge crystal by introducing several dopant species by ion implantation at different energies and doses. The behavior of P, As and Sb as donor species and of B and Ga as acceptor species was investigated in terms of diffusion and activation levels. The implanted junctions were annealed by rapid thermal processing...

Since its original conception in the 1960s, the spreading resistance probe (SRP) has evolved into a reliable and quantitative tool for sub-micrometer, electrically active dopant, depth profiling in silicon. Its application limit has in recent years even been pushed down to ultra-shallow (sub-50nm) structures. In this review, a systematic discussion...

Understanding dopant diffusion and activation mechanisms is a key issue for future sub-45 nm CMOS technologies. This understanding requires the availability of accurate chemical and electrically active dopant profiles. In this work we will focus on the accurate characterization of the electrical active portion of ultra-shallow junction (USJ) profil...

Electromigration in copper damascene interconnects is usually associated with interfacial diffusion at the copper/ dielectric barrier interface. In this study, we demonstrate how impurity and microstructural properties of the bulk copper can influence failures at the copper/dielectric barrier interface. Impurity concentrations in the bulk copper we...

The size effect observed for copper in reduced dimensions is studied by several different routes in order to further understand the relative influence of various scattering mechanisms and determine where to focus our efforts in order to reduce line resistance.

The inverse relationship between film thickness and electrical resistivity of metallic films is usually studied by depositing a series of films with different thickness and measuring their sheet resistance with a four-point probe. However, the structure and uniformity of polycrystalline thin films typically depend on thickness, rendering it difficu...

The Carrier Illumination™ (CI) method is an optical technique for nondestructive in-line monitoring of postanneal junction depth, preanneal preamorphization implant depth, and dose. This work intends to extend the use of the CI measurements from a relatively process specific quantitative measurement towards a more universal quantitative analysis of...

The spreading resistance probe (SRP) tool is widely used for obtaining the electrically active dopant profile in silicon. In this work, the capabilities of SRP for thin metal film (Cu/Al/TaN) characterization are investigated. It is well known that quite large correction factors (∼500) are involved in sub-100 nm silicon SRP profiling to extract the...

Solid phase epitaxial regrowth (SPER) is a promising method for junction formation of sub-65 nm complementary metal–oxide–semiconductor technology nodes. This is mainly due to a high dopant activation level, easy control over electrical junction depth, excellent abruptness, and limited boron diffusion. In the present research we investigate in deta...

This article discusses the results obtained from an extensive comparison set up between nine different European laboratories using different two-dimensional (2D) dopant profiling techniques (SCM, SSRM, KPFM, SEM, and electron holography). This study was done within the framework of a European project (HERCULAS), which is focused on the improvement...

In this paper, we present the overall progress in scanning spreading resistance microscopy (SSRM) capabilities, achieved over the last year, with respect to all aspects of the technique. Progress in spatial resolution (less than 3 nm) has been achieved by optimized sample preparation and the development of better hard conductive diamond tips. Limit...

The Carrier Illumination™ (CI) method is an optical technique for non‐destructive in‐line monitoring of post‐anneal junction depth, pre‐anneal pre‐amorphisation implant (PAI) depth, and dose. This work describes the sensitivity of the CI‐signal to the as‐implant dose and demonstrates that a universal response function can be derived for doses below...

As emphasized in the ITRS roadmap, two-dimensional (2D) carrier profiling is one of the key elements in support of technology development. For CMOS silicon devices, scanning spreading resistance microscopy (SSRM) has demonstrated an attractive spatial resolution and concentration sensitivity. The automated construction of calibration curves allows...

It is well known that the electrical junction depth position measured along a beveled surface, as is routinely done in the spreading resistance probe (SRP) technique, is shallower than the corresponding metallurgical junction as seen by secondary ion mass spectrometry. The amount of on bevel junction shift (i.e., the difference in electrical on bev...

Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) are both valuable tools for analyzing the two-dimensional carrier distribution in semiconductor devices. Both tools rely on the application of a bias between tip and sample to probe the relevant property (capacitance or resistance). With respect to SCM, experi...

As emphasized in the International Technology Roadmap for Semiconductors (ITRS), two-dimensional (2D) carrier profiling is one of the key elements in support of technology development. Sub-10 nm resolution, high dynamic range (1016-1020 at/cm3) and good quantification accuracy (10%) are the most important targets to be achieved. In this work we foc...

The resistivity of thin copper films is characterized by both spreading resistance probe (SRP) and conventional four-point-probe (FPP) as a function of thickness and temperature. A strong increase in resistivity is observed by SRP and FPP measurements with decreasing the thickness. SRP also enables us to study the resistivity of ultra-thin films wi...

Carrier Illumination™ (CI) is an optical technique for non-destructive in-line monitoring of post-anneal junction depth and pre-anneal PAI depth and dose with wafer mapping capabilities. This work intends to extend the use of the CI-measurements from a range-specific quantitative measurement towards a more universal quantitative analysis of junctio...

The relationship between damage formation/annealing and As profile redistribution has been studied using low energy As implants into Si at 2.5 keV at doses between 3 × 10¹³ cm^-2 and 2 × 10¹⁵ cm^-2 at room temperature. Samples were annealed at temperatures between 600 and 1050°C. High depth resolution mediu...

The spreading resistance probe (SRP) is a widely used measurement tool for electrical characterization of Si structures. From the measured spreading resistance depth profile, the underlying electrically active dopant profile can be extracted through the application of a series of specific software corrections. In this letter, it is shown that for s...

In this work we have done a systematic study with scanning capacitance microscopy (SCM) on cross-sectional and beveled structures. A study was made on the practical problem of contrast reversal as well as on the effect of carrier spilling related to bevel angle, steepness and substrate concentration of the doping profile. A comparison has been made...

Limitations and their solutions related to the use of spreading resistance probe (SRP) for future sub-100 nm technologies using sub-35 nm junctions was discussed. Large sampling volume induced by large contact and probe spacing necessitated correction factors as large as 1-2000. Chemical beveling, interferometry and the use of conductive atomic for...

As emphasized in the International Technological Roadmap for Semiconductors (ITRS), two-dimensional carrier profiling is one of the key elements in support of technology development. Scanning spreading resistance microscopy (SSRM) has been demonstrated to have attractive concentration sensitivity, an easy quantification, and is applicable to comple...

The spreading resistance probe (SRP) and four point probe (FPP) use, respectively, two or four metal probes with loads in the range of 5–100 g to obtain indispensable information on the electrical characteristics (sheet resistance, junction depth, activation degree, profile shape) of impurity depth profiles in silicon. Recently, however, it has bee...