A Survey on Performance Analysis of Different Architectures of AES Algorithm on FPGA

Abstract

Encryption is the primary way for ensuring communication security. The symmetric key method, often known as Advanced Encryption Standard (AES), is a well-known technique in the field of security. AES can be implemented in either software or hardware. In the current study, Field Programmable Gate Arrays (FPGAs) are utilized to implement AES. Number of studies have been done on experiments of AES using FPGAs. Till date, no study has been done on the architectures that are being utilized to implement AES on FPGA. This paper provides an in-depth examination of several hardware implementation of AES on FPGA in terms of through put and performance. This survey article enables the engineers to choose the best architecture of FPGAs to implement AES algorithm in terms of design as per the requirement. The surveyed architectures are sequential, pipelined, iterative, and parallel. Parallel architectures with pipelining between rounds have shown an excellent throughput. Certain improved S-box and key expansion approaches have also been employed by the researchers to reduce the hardware areas.

Full text

A Survey on Performance Analysis
of Different Architectures of AES
Algorithm on FPGA
Taniya Hasija, Amanpreet Kaur, K. R. Ramkumar, Shagun Sharma,
Sudesh Mittal, and Bhupendra Singh
Abstract Encryption is the primary way for ensuring communication security. The
symmetric key method, often known as Advanced Encryption Standard (AES), is
a well-known technique in the field of security. AES can be implemented in either
software or hardware. In the current study, Field Programmable Gate Arrays (FPGAs)
are utilized to implement AES. Number of studies have been done on experiments of
AES using FPGAs. Till date, no study has been done on the architectures that are being
utilized to implement AES on FPGA. This paper provides an in-depth examination
of several hardware implementation of AES on FPGA in terms of through put and
performance. This survey article enables the engineers to choose the best architecture
of FPGAs to implement AES algorithm in terms of design as per the requirement.
The surveyed architectures are sequential, pipelined, iterative, and parallel. Parallel
architectures with pipelining between rounds have shown an excellent throughput.
Certain improved S-box and key expansion approaches have also been employed by
the researchers to reduce the hardware areas.
Keywords AES algorithm ·AES architectures ·Pipeline architecture ·Parallel
architecture
T. Ha si ja (B)·A. Kaur ·K. R. Ramkumar ·S. Sharma ·S. Mittal
Chitkara University Institute of Engineering and Technology, Chitkara University, Rajpura,
Punjab, India
e-mail: taniya@chitkara.edu.in
A. Kaur
e-mail: amanpreet.kaur@chitkara.edu.in
K. R. Ramkumar
e-mail: k.ramkumar@chitkara.edu.in
S. Sharma
e-mail: shagun.sharma@chitkara.edu.in
S. Mittal
e-mail: sudesh.mittal@chitkara.edu.in
B. Singh
Centre for Artificial Intelligence & Robotics, DRDO, Bangalore, India
e-mail: bhupendra@cair.drdo.in
© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023
R. Agrawal et al. (eds.), Modern Electronics Devices and Communication Systems,
Lecture Notes in Electrical Engineering 948,
https://doi.org/10.1007/978-981-19-6383-4_4
39

40 T. Hasija et al.
1 Introduction
Internet messaging and data transfer are the most preferred modes of communication
in today’s society. Security is the primary concern of every business or government
organization. If a company provides data security to its clients, it will be regarded
trustworthy; otherwise, the organization will be considered unreliable. Cryptography
is a type of cybersecurity that encrypts and decrypts data in order to ensure its
secrecy, integrity, and validity [1]. Encryption is the act of converting data into cipher
text (incomprehensible text), and decryption is the process of converting that cipher
text back to intelligible language [2]. Cryptography employs two different types of
security algorithms: symmetric key cryptography and asymmetric key cryptography.
The only distinction between the two is how the key is utilized. In symmetric key
cryptography, the same key is used for encryption and description, but in asymmetric
key cryptography, two separate keys are used for encryption and description [3]. Some
symmetric algorithms are DES, 3DES, AES, and Blowfish [4,5]. Asymmetric key
cryptography, on the other hand, includes Diffie Hallman, RSA, ECC, and digital
signatures [5].
The National Institute of Standards and Technology (NIST) released a new algo-
rithm to replace the data encryption standards (DES) algorithm, and the name given
to the new algorithm is AES. Algorithm implementation can be divided into two
categories: software implementation and hardware implementation. The drawback
of DES is that it is only implemented on hardware, whereas AES is implemented in
both software and hardware. In the year 2000, Rijmen and Daemen developed the
Rijndael algorithm, which was later adopted as the AES method by NIST [6]. AES
offers a number of benefits over DES, including fast throughput, ease of upgrading,
software hardware implementation, portability, and flexibility [7]. The AES algo-
rithm became the most popular cryptographic algorithm in 2006, and it attracted the
attention of the entire globe. The size of the key is one of the reasons for switching
from DES to AES. The key size of DES is 56 bits, which is breakable by today’s
hacking techniques. To address the risk of key attacks, AES uses a 128-bit key, a
192-bit key, or a 256-bit key, depending on the number of rounds [3,8].
Due to the non-readability of hardware functionality and the fact that it cannot be
manipulated by an intruder, hardware implementations of algorithms are considered
more secure than software. Because standard hardware equipment lacks flexibility,
the AES code is implemented on advanced hardware devices known as FPGA [9].
FPGAs are dynamic circuits with functionalities that are not fixed and may be modi-
fied over time or in response to a need [10]. In FPGAs, SRAM-controlled transistors
are utilized, and a large number of logic cells are integrated into the wire network [10].
Iterative, loop unrolling, pipelining, sub-pipelining, and parallel architectures have
been implemented on FPGAs. Some researchers have compared the hardware imple-
mentation of DES and AES algorithms [11–13]. Number of architectures are imple-
mented on AES using FPGAs, but no study has been conducted on the throughput
analyzes for AES. In this work, we will conduct a thorough analysis of the perfor-
mance of various architectures implemented on FPGAs. The designs are compared

A Survey on Performance Analysis of Different Architectures of AES … 41
on the basis of throughput, hardware area, cost, and complexity. The literature study
of AES algorithm implementations is depicted in Sect. 2. Section 3goes through
the theoretical background of the AES algorithm. In Sect. 4, the various architec-
tures used in AES are discussed. The comparison table and performance analysis of
implemented AES designs are included in Sect. 5. The conclusion and references
are included in the next section.
2 Literature
The well-known AES algorithm first came into light in 2001 after the acceptance
of Rijndael algorithm. Deaman and Rijman [14] introduced a new algorithm for the
cryptography techniques. In their proposed algorithm, they represented mathemat-
ical preliminaries and then the round specifications and functionalities and also the
key scheduling. Later, NIST accepted Rijndael algorithm as standard and named
it as AES. Elbirt et al. [9] presented their work in IEEE transactions, in which the
AES algorithm was finalized. They built RC6, Rijndael, snake, and Twofish algorithm
designs on FPGA in their work, and they tested these algorithms in four modes: speed
optimized non-feedback mode, area optimized non-feedback mode, speed optimized
feedback mode, and area optimized feedback mode. The result is that the Rijndael
algorithm performs well in hardware implementation and is the titled as AES algo-
rithm. Wollinger and Paar [15] have published an article about the security of FPGAs.
They examined the various types of attacks in their article and presented a research on
how FPGAs are effective at coping with them. Zhang and Wang [16] worked on the
AES algorithm and used FPGA to construct the AES outer-rounder pipelined design.
They utilized block RAM to store the S-box values in their research. The provided
system has a throughput of 34.7 Gbps at 271 MHz. Yoo et al. [17] developed a vertex
II pro FPGA version of the AES algorithm in 2005. They used a parallel architecture
for the AES algorithm, which resulted in a system throughput of 29.77 Gbps. Fan and
Hwang [8] presented a study on completely sequential and pipelined design for the
AES algorithm on FPGAs in 2007. To achieve high throughput, a content addressed
memory-based approach is utilized. They employed a high-speed mix column block
and a low-cost add round key architecture in their suggested work. For architectural
designs, Xilinx ISETM 7 and XSTTM IDEs are utilized. The sequential design has
a throughput of 0.876 Gbps, whereas the pipelined architecture has a throughput of
32 Gbps. For the recursive algorithm architecture on FPGA, Sklyarov [18] represents
code for the recursive algorithm. He suggested a hierarchical recursive finite state
machine paradigm. For implementation, the Xillin Spartan-II series is employed.
Swankoski et al. [19] proposed two FPGA architectures for the AES algorithm.
The first is a completely parallel loop unrolled design, while the second is a 32-bit
datapath round-based architecture. The performance of the unrolled architecture is
superior in terms of speed to area since there is no controller overhead, but it uses 1 2
million gate devices and has a throughput of 25 Gbps. For the first architecture, Xillin
Spartan-III is utilized. The AES algorithm is investigated by Deshpande and Bhosle

42 T. Hasija et al.
[20] for parallel, pipelined, and sequential systems. For the implementation of these
three designs, they employed 11 keys. In terms of throughput and area, a finite state
machine is suggested and proven to be efficient. Kumar et al. [3] developed AES on
the vivado ISE design suit in 2020, and the results were shown in Artix 7 FPGAs.
During implementation, 3987 slice tables, 4115 lookup tables, 269 I/O, and 1 global
buffer are used.
There have been a lot of papers published on AES implementation on FPGA,
with various architectures being utilized for AES implementation. In this survey, we
evaluated and analyzed the performance of different architectures so that one may
have a good understanding of the performance of each architecture and select the
best architecture for his work domain.
3 AES Algorithm
AES algorithm encrypts 128-bit plain text into cipher and cipher text into plain text
using identical key [11]. The length of the key is of 128-bits for 10 rounds, 192-bits
for 12 rounds, and 256-bits for 14 rounds. 128-bit plain text which is input to the AES
algorithm is firstly converted into data block of 4 ×4 matrix having 16 elements, and
each element is of one byte [21]. The algorithm is subdivided into three parts [22].
The key is XORed to the input matrix in the first stage, while the second stage includes
nine cipher rounds, each with four functions: subBytes(), shiftRows(), mixColumn(),
and addRoundKey() and in third stage which is also called the 10th round implements
three functions which are subBytes(), shiftRows(), and addRoundKeys() [23]. The
structure of AES algorithms is shown in Fig. 1. The same structure as in encryption
is utilized for decryption, but the inverse of all functions is employed, as illustrated
in Fig. 1.
The following are the four functions that we are using during the span of 10
rounds:
3.1 subBytes Transformation
Using the substitution box [24], each byte of the input matrix is replaced with a new
byte in the subByte function. The substitution box is created using multiplicative
inverse over GF(28), as well as a multiplicative inverse affine transformation. The
inverse subByte function is used in the decryption step to obtain the original value
[21].

A Survey on Performance Analysis of Different Architectures of AES … 43
Fig. 1 Basic structure of AES algorithm
3.2 shiftRow Transformation
Four rows of the matrix are moved to the left in this transformation. The first row
remains intact, but the second is moved by one cycle, the third by two, and the fourth
by three. The identical method is used in the inverse shifting row, but the shifting is
done to the right side.
3.3 mixColumn Transformation
Each column is treated as a polynomial in this transformation, and it is multiplied
by a fixed polynomial before being moduled with x^4 +1[
17]. Inverse mixColumn
follows the inverse of the multiplication to get plain text.

44 T. Hasija et al.
3.4 addRoundKey Transformation
The key is created in the key scheduling block, where a 128-bit key is permuted
using shifting row or column operations before being used to the encryption rounds.
The mixColumn output is then XORed with this key, and a new XORed output is
delivered to the following round [14].
4 Different Architectures for AES
The fundamental objective of any hardware architecture is to achieve high throughput
while using the least amount of space possible. A variety of hardware architec-
tures have been designed that meet these objectives. From which some popular
architectures are explained below:
4.1 Iterative Architecture
Iterative architecture is the most efficient technique since it requires the least amount
of hardware. The architecture of iterative AES is shown in Fig. 2. This design has a
low register to register latency, but encryption requires a significant number of clock
cycles. The only expense associated with this approach is the hardware needed for
round key and S-box multiplexing [25]. The cost of operating in RAM mode can
be lowered by employing a 4-bit lookup table within the configurable logic blocks.
Lookup tables are used to store round keys; one lookup table may hold up to 16 round
keys, eliminating the need for registers, which are expensive in terms of hardware
[9].
Fig. 2 Iterative architecture

A Survey on Performance Analysis of Different Architectures of AES … 45
Fig. 3 Sequential architecture [8]
4.2 Sequential or Loop Unrolling Architecture
Multiple rounds are unrolled, up to the total number of rounds required for the cipher
text. All loops are unrolled in this design, and the entire algorithm is implemented as
a single combinatorial logic block. This design has a significant hardware demand.
There are two new registers, as well as input and output interfaces. To encrypt 128-bit
plain text, 11 clock cycles are needed [25]. The architecture of sequential architecture
is depicted in Fig. 3.
4.3 Pipelined Architecture
Because a large number of blocks are processed at the same time, the pipeline layout
allows for high throughput. When round 2 is run for the cipher text production, 1st
one will not be on ideal state, the next plain text is supplied as input to the round 1st,
while 2nd is processing the previous input. This may be accomplished by inserting
a register between the intermediate rounds. The critical route latency is reduced by
adding registers [16]. The pipeline architectures are further subdivided into different
categories. In outer round only pipelined architecture, pipelining is applied only in
first round and in last round. While in external pipeline architecture, all 10 rounds are
pipelined, and throughput is high. In sub-pipelining, the subByte step of all rounds
is also subdivided into four steps, and all steps are pipelined, so that delay can be
overcome. In sub-pipelined, the hardware area is quite high, but the throughput is
also very good. Figure 4depicts the pipelined design.
4.4 Parallel Architecture
For achieving maximum utilization of FPGAs logic cells, gates, and I/O resources,
parallel architecture is implemented, which in return has high throughput and

46 T. Hasija et al.
Fig. 4 Pipelined architecture [16]
maximum utilization of resources. The parallel designing provides more degree of
flexibility.
Two or more than two pipeline architectures are implemented in parallel, utiliza-
tion of resources is done efficiently, and performance is also increased [7]. Parallel
architecture allows multiple parallel encryptions of plain text. Independent key
scheduling is used in parallel architectures as if shared key is used by two parallel
blocks, these blocks are not at the same point in the encryption [17]. The parallel
processing of AES is depicted in Fig. 5. Multi-core systems are used for the imple-
mentation of parallel architecture where two or more cores are in a single processor. In
simple words, core is a processing or execution unit. In multi-core systems, each core
has its own execution pipeline and also has resources to run the block independently
[26].
Fig. 5 Parallel architecture

A Survey on Performance Analysis of Different Architectures of AES … 47
5 Performance Analysis of AES Architectures
Because of its widespread use, the AES algorithm is utilized in nearly every aspect of
security. A number of AES architectures have been implemented to achieve reduced
costs and higher output by knowing the device or algorithm’s demand for throughput.
In literature section, a number of researcher have contributed significantly to the field
of AES and have built hardware designs of algorithms by describing the throughput
of the architecture in terms of time complexity and hardware area complexity. There
has been no comprehensive research of the various hardware design algorithms for
AES till date. We compared implemented designs and performed a performance
study based on the throughput of their implementation in this part. A performance
analysis table for the AES algorithm on FPGAs utilizing various designs is shown in
Table 1. The comparison is made up of seven criteria that describe implementation
specifics. The defined characteristics are the author’s implemented architecture, the
device used to implement that architecture, the mode used (mode is a method of
determining whether output encrypted data is given to the next input plain text or
not), the slices used, the frequency and then the number of cycles used to run a block,
and the main parameter throughput of the implemented system.
AES FPGAs have been used by reference no. 9 to construct three designs, as
indicated in the Table 1.Thework[9] has been approved by NIST as a standard. AES
throughput has been improved in the sources [8,13,19,25,27] by using a pipelined
design that includes inner pipelining, outer pipelining as well as deep pipeline, sub-
pipeline, and hybrid pipelining architectures, compared to source [9]. Sequential
architecture’s throughput rate is not very great [8]. The iterative framework has
been developed by authors [24] and [32] and has a throughput of 14.383 Gbps
on the average. The authors [7,14,16,20,26] worked on parallel architectures,
implementing parallelism via loop unrolling, pipelining, and lookup tables. With
minimal time complexity and large throughputs, parallel architecture provides its
own set of advantages.
6 Conclusion
This article offers a detailed analysis of the AES algorithm and the architectures
being used to implement it. Different architectures are developed to meet the needs of
various requirements. Some architectures are focused on low hardware, while others
are focused on high throughput, while yet others are focused on maximizing resource
utilization. In this study, we conducted a survey of existing work that compares
the performance of several designs for the AES algorithm on FPGAs. It has been
concluded that iterative design is well suited in terms of lowest hardware area, but
that parallel architecture with pipelining between rounds leads to efficient resource
utilization and high throughput. A completely unrolled three-stage inner and outer
double pipelined design and parallel lookup table architecture provide the greatest
throughput of 60.29 Gbps in the surveyed articles.

48 T. Hasija et al.
Tabl e 1 Different architectures implemented on AES and different perimeters used during implementations
S. No. Author Architecture Device used Mode Slices Frequency Cycles (MHz) Throughput
1Elbirt et al. [9]Loop unrolling
with two rounds
having speed
optimized
feedback mode
and
non-feedback
mode
VHLD code on FPGA,
Xilinx Virtex
XCV1000BG560-4
ECB
(Electronic
codebook
mode)/cipher
text feedback
mode (CFB)
5302 14.1 MHz 6 per block 300 Mbps
2Elbirt et al. [9]Pipeline
architecture
with two stages
having speed
optimized
non-feedback
mode
Xilinx Virtex
XCV1000BG560-4
ECB 10,533 20 MHz 2.2 per block 1165 Mbps
(continued)

A Survey on Performance Analysis of Different Architectures of AES … 49
Tabl e 1 (continued)
S. No. Author Architecture Device used Mode Slices Frequency Cycles (MHz) Throughput
3Elbirt et al. [9]Sub-pipeline
architecture, a
partially
pipelined
architecture
with five stages
and one
Sub-pipeline
stage per
pipeline stage
having speed
optimized
non-feedback
mode
Xilinx Virtex
XCV1000BG560-4
ECB 10,992 31.8 MHz 2.1 per block 1937.9 Mbps
4Chodowiec
et al. [27]
Pipeline
architecture
Vir tex
XCV-1000BG560-6
ECB 12,600 100–130 MHz 22 complete
one cipher
text
generation
12.2 Gbps
5Swankoski
et al. [7]
Parallel
architecture
with 10 blocks
Vertex-II pro FPGAs
(XC2VP50)
ECB 20,249 150.61 MHz Not
mentioned
19.28 Gbps
6Yoo et a l . [17]Parallel
pipelined
architecture
Virtex-II Pro FPGA (
chip contains same 10
units, each unit perform
one round of algorithm)
ECB 6541 222.2 MHz 7.96 ns for
one complete
128-bit cipher
text
generation
29.77 Gbps
(continued)

50 T. Hasija et al.
Tabl e 1 (continued)
S. No. Author Architecture Device used Mode Slices Frequency Cycles (MHz) Throughput
7Good and
Benaissa et al.
[16]
Fully parallel
loop unrolled
architecture
Xilinx Spartan-III
(XC3S2000)
ECB 25,107 196.1 MHz 70 cycles for
all rounds, to
pass AES
cipher
25 Gbps
8Fan and
Hwang [8]
Sequential
architecture
Xilinx ISE™ 7
(XC2V3000)
Not
mentioned
7617 75.3 MHz 11 clock
cycles
required for
encrypting
128-bit
0.876 Gbps
9Fan and
Hwang [8]
Fully pipelined
architecture
XST™
(XC4VLX200)
Not
mentioned
86,806 250 MHz 1for
complete
cipher of the
128-bit text
32 Gbps
10 Wang et al.
[22]
Multi-core
architecture
Vertex-II
XC2V6000
ECB/ CBC (
cipher block
chaining)
27,561 102 MHz 3 for one
cipher output
1.29 to 3.7
Gbps
11 Zhang and
Wan g [16]
Outer round
only pipelined
architecture
Virtex-II Pro FPGA
XC2VP70
ECB 2389 CLB with
200 Block RAMs
271.15 MHz 11 clock
cycles
required for
encrypting
128-bit
34.7 Gbps
12 Borker et al.
[24]
Iterative
architecture
Xilinx’s Vertex XCV600
BG 560–6
CFB 1853 slices, 512
flip flops, 3645
lookup tables
140.39 MHz 51 for 128-bit
data
encryption
352 Mbps
(continued)

A Survey on Performance Analysis of Different Architectures of AES … 51
Tabl e 1 (continued)
S. No. Author Architecture Device used Mode Slices Frequency Cycles (MHz) Throughput
13 Rahimunnisa
et al. [28]
Parallel
operation in the
folded
architecture
Virtex-6 XC6VLX75T Not
mentioned
2056 registers,
3788 LUTs, 48
block RAMs
505 MHz 1.978 ns 37.1 Gbps
14 Deshpande
and Bhosle
[20]
Parallel as
encryption and
decryption is
done parallel,
pipelined as all
rounds are
accepting input
and giving
output to next
round
Implemented in Zynq
(xc7z020-2clg484)
device and tested on
Zedboard
Not
mentioned
Slice registers-
2008
Lookup tables
(LUT)- 1364
239.648 MHz 1for
complete
cipherof16
byte data
5.75 Gbps
15 Yada v et a l .
[29]
Outer pipeline
architecture and
inner line
pipelining on
different stages
Xilinx 9.2
on Spartan and Virtex
series (xc4vlx20)
ECB 2273 slices and
LUTs
388.667 MHz 11 Clock
cycles
49.49 Gbps
16 Zhang et al.
[30]
Fully unrolled
three-stage
inner and
outer double
pipelined
architecture and
parallel lookup
tables
Vertex-6
(XC6VLX240T)
Not
mentioned
2252 slices, 244
block RAMs
470.99 MHz 31 clock
cycles for on
cipher output
60.29 Gbps
(continued)

52 T. Hasija et al.
Tabl e 1 (continued)
S. No. Author Architecture Device used Mode Slices Frequency Cycles (MHz) Throughput
17 Zodpe and
Sapkal [21]
New hybrid
non-pipelined
(PN sequence
generator is
used for S-box
values)
Spartan6
XC6SLX150-3FGG900
FPGA
Not
mentioned
5566 237.45 MHz 10 clock cycle
to generate
output
30.39 Gbps
(security is
enhanced)
18 Chen et al.
[31]
Deep pipeline
architecture and
full expansion
technology
Implemented with
Vivado HLS (v2016.4)
built on Xilinx
xc7k325tffg676-2 l chip
ECB Block RAM- 288,
flip flop- 13,647,
lookup
tables-1,26,040
Not mentioned 62 clock
cycles for
cipher of
given plain
text
31.30 Gbps
19 Murugan et al.
[32]
Iterative
architecture
with
sub-pipelined
S-box
technique
Spartan-3, virtex-4 Cipher
feedback
mode
Slices-1132, flip
flops- 680, 4
in–out UTs-2156
112.37 MHz for
vertex-4.
67.75 MHz for
Spartan-3
Not
mentioned
14,383 Mbps
for vertex-4,
8672 Mbps
for Spartan-4

A Survey on Performance Analysis of Different Architectures of AES … 53
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