Snaider Carrillo

Ulster University · Intelligent Systems Research Centre

The mammalian brain has become one of the most interesting and active research topics, not only for neuroscientists, but also for computer scientists and engineers. However, whilst neuroscientists are interested in biophysical models (Trappenberg, 2009), computer scientists and engineers are more interested in the brain’s powerful signal-processing...

Technology scaling over the years has enabled the integration of multiple processing cores on a single chip with Network-on-chip (NoC) becoming an interconnect standard for facilitating large scale connectivity between cores. However, these NoC components, like any other circuit components, are also becoming more susceptible to faults with further...

Spiking neural networks (SNNs) attempt to emulate information processing in the mammalian brain based on massively parallel arrays of neurons that communicate via spike events. SNNs offer the possibility to implement embedded neuromorphic circuits, with high parallelism and low power consumption compared to the traditional von Neumann computer para...

Biologically-inspired packet switched network on chip (NoC) based hardware spiking neural network (SNN) architectures have been proposed as an embedded computing platform for classification, estimation and control applications. Storage of large synaptic connectivity (SNN topology) information in SNNs require large distributed on-chip memory, which...

Recent focus has been placed on exploring the possibility to switch from parallel to serial data links between NoC routers in order to improve signal integrity in the communication channel. However, moving streams of data between the parallel path of the internal router and external serial-channel links between them consumes additional power. One c...

The complexity of inter-neuron connectivity is prohibiting scalable hardware implementations of spiking neural networks (SNNs). Traditional neuron interconnect using a shared bus topology is not scalable due to non-linear growth of neuron connections with the neural network size. This paper presents a novel hierarchical NoC (H-NoC) architecture for...

The brain is highly efficient in how it processes information and tolerates faults. Arguably, the basic processing units are neurons and synapses that are interconnected in a complex pattern. Computer scientists and engineers aim to harness this efficiency and build artificial neural systems that can emulate the key information processing principle...

EMBRACE has been proposed as a scalable, reconfigurable, mixed signal, embedded hardware Spiking Neural Network (SNN) device. EMBRACE, which is yet to be realised, targets the issues of area, power and scalability through the use of a low area, low power analogue neuron/synapse cell, and a digital packet-based Network on Chip (NoC) communication ar...

This paper presents an adaptive Network-on-Chip (NoC) router, which forms part of an embedded mixed signal Spiking Neural Network (SNN) architecture called EMBRACE (Emulating Biologically-inspiRed ArChitectures in hardware). The novel adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoidi...

This paper presents the design and implementation of an arithmetic processing unit based on the logarithmic number system. The proposed implementation is supported in a new set of linear equations, which allows calculating the approximation of the logarithm and antilogarithm binary functions and leads to a maximum relative error of 1×10<sup>-3</sup...

Network on Chip (NoC) based Spiking Neural Network (SNN) hardware architectures have been proposed as embedded computing systems for data/pattern classification and control applications. As the NoC communication infrastructure is fully reconfigurable, scaling of these systems requires large amounts of distributed on-chip memory for storage of the S...

This paper presents EMBRACE-SysC, a simulation-based design exploration framework for the EMBRACE mixed signal Network on Chip (NoC)-based hardware Spiking Neural Network (SNN) architecture. EMBRACE-SysC incorporates Genetic Algorithm-based training of SNN applications. Results illustrate the application of EMBRACE-SysC for performance analysis of...

Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However the use of the NoC as an interconnection fabric for large scale SNN (i.e. beyond a million neurons) demands a good trade-off b...

In this paper, we propose two novel techniques to transform control statements so they can be executed efficiently on the NVIDIA G80 architecture. Our techniques called loop splitting and branch splitting smartly increase code redundancy, which might be deemed as "de-optimization" for CPU; but for a GPU framework these techniques improve the occupa...

Control statements in a GPU program such as loops and branches pose serious challenges for the efficient usage of GPU resources because those control statements will lead to the serialization of threads and consequently ruin the occupancy of GPU, that is, the number of threads running concurrently. Unlike traditional vector processing units that ar...

The use of HDLs (Hardware description languages) allows the design of a considerable variety of embedded systems. As a good example of this we present the flow used in the design and construction of an application specific non-pipelined microprocessor, that will serve as core of a PLC (programmable logic controller) compatible with the programming...

This paper shows the procedure followed by the Robotics and Intelligent Systems Group of the Universidad del Norte (Colombia), for the design and construction of a Programmable Logic Controller (PLC), compatible with the IL (Instructions List) programming language, according to the norm IEC 61131-3 and able to be programmed locally through the RS-2...