Design of Balanced Ternary Encoder and Decoder

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Design of Balanced Ternary Encoder and Decoder
Aadarsh G. Goenka
Department of CSE
Jadavpur University
Kolkata, India
aggtur11@gmail.com
Shyamali Mitra
Department of IEE
Jadavpur University
Kolkata, India
shyamali.mitraa@jadavpuruniversity.in
Nibaran Das
Department of CSE
Jadavpur University
Kolkata, India
nibaran@ieee.org
Abstract
The origin of Ternary computing which is based on
a3-valued logic, can be traced back to the 18th century.
Despite having its enormous potential to deal with a huge
range of numbers with low consumption of power, Ternary
logic system has received little attention with the advent
and unprecedented progress of binary computers. In this
paper, we propose an architecture and design of Balanced
Ternary Encoder and Decoder circuit. The existing En-
coder and Decoder circuits uses Unbalanced Ternary to
create desired functions and are limited to only two logic
levels, whereas the proposed Encoder and Decoder circuits
harnessing the property of Balanced Ternary, exploit all
the possible logic levels and can be used in both Balanced
Ternary and Binary Coded Balanced Ternary applications.
The complexity of the circuits is calculated to show the
potential of proposed designs.
I. INTRODUCTION
With the increasing demand for high logic density [1], as
device dimensions in binary logic have continued to shrink,
certain problems are evident. Complex binary circuits face a
number of inherent difficulties, the majority of which revolve
on increasing the logic density, interconnection complexity,
and, subsequently, leakage currents. As a result, there is a
constant endeavour to replace the conventional Binary Logic
System. When building high-performance, energy-efficient
VLSI circuits, ternary logic arises as an alternative to standard
binary logic due to its reduced number of interconnects and
hence chip area. Three digits are used in Balanced Ternary
system; −1,0,and +1. The ternary number system enables us
to construct three outputs/choices when compared to binary.
As for example, comparator circuits consist of three outcomes
greater than (>), smaller than (<) and equal to (=) and here
we have the leverage to define three logic levels for three
different outcomes. There are also real life examples that
make use of three logical outcomes, e.g., a patient suspected
with cancer after being examined by a doctor can throw
three decisions, such as; benign, malignant and inflamma-
tory conditions. Implementing these kinds of problems using
ternary logic can help to reduce the complexity of the circuit.
The commonly used devices to create ternary logic blocks
include Carbon Nanotube Field-Effect Transistor (CNTFET)
[2], Field–Programmable Gate Array (FPGA) [3], CNTFET
and Magnetic Tunnel Junction (MTJ) [4], Memristors and
MOSFETs [5], [6], Single Electron Transistor (SET) [7], [8],
Binary Coded Ternary (BCT) [9], Recharged CMOS Semi-
Floating Gate (RSFG) devices [10], CMOS implementation of
ternary arithmetic logic gates [11]. In Ternary [12], there are
certain logic circuits that exist in literature such as, addition
and multiplication. When it comes to processing functions
involving large numbers, ternary computing offers immense
promise.
In digital electronics, binary Encoder and Decoder are rec-
ognized as tools for converting data between different formats
and are extensively used in communication systems such as
telephone and networking. Prasad et al. [13] has proposed a
circuit to create the functionality of the Unbalanced Ternary
Encoder and Decoder circuits using CNTFETs, but there exist
no Encoder and Decoder circuits in balanced ternary logic that
can handle a larger number of signals with equivalent number
of digits. The major limitation of the logic in [13], [14] is
that the inputs of the proposed Encoder do not use the third
variable i.e., the logic symbol 1, which could have reduced the
number of the input lines used. The logic used by the Encoder
circuit encodes given inputs in binary corresponding to two
only logic levels i.e., 0and 2using Unbalanced Ternary. Same
reasoning applies to the Decoder circuit. Also, Unbalanced
Ternary number uses the digits 0,1and 2instead of −1,0and
1, used in Balanced Ternary, thus unable to represent negative
numbers without using 3’s complement notation. Balanced
Ternary, on the other hand, can deal with negative numbers
easily because of the presence of −1digit in it. So, we
propose the design and architecture of the balanced Ternary
Encoder and Decoder circuit in this paper with an estimation
of their hardware complexities and time complexities. The
circuits can be constructed using binary equivalent designs,
making them versatile. Furthermore, it can handle more data
while maintaining the comparable time complexity as binary
implementation.
A Decoder, like an Encoder, is a combinational circuit, but
its operation is exactly the opposite. It outputs the original
signal from a coded input signal and converts nlines of
input to 2nlines of output. Because an AND gate provides
a high output only when all inputs are high, it can be utilised
as the basic decoding element. Decoders are employed in a
variety of applications, including decoded driving signals for
seven-segment displays and memory address decoding. The
contribution in the present work can be highlighted as follows:
1) The design of three ternary Input Decoder circuits are
proposed in Section 2. The Decoder circuits are designed
to aid the complex circuits in achieving flexibility to
accept the different types of input formats.

2) The design of three ternary Output Decoder circuits are
proposed and introduced in Section 3. These Decoder
circuits are designed to aid the complex circuits in
achieving flexibility to generate different types of output
formats.
3) The design of a 14:3 Balanced Ternary Encoder circuit
is proposed and described in Section 4.
4) The design of a 3:14 Balanced Ternary Decoder circuit
is proposed and introduced in Section 5.
II. IN PU T DEC OD ER
The Input Decoder takes each input from the user I0to
Id as Iand generates a 3-trit number Ii of each input to be
utilised in further units. The 3-trit number contains I−trit, I0
trit and I+trit. We have presented three circuits for generating
outputs from the input Decoder circuits in three different cases
such as; balanced ternary numbers, to employ binary gates in
other units and for binary-coded balanced ternary numbers
(BCBT) respectively.
A. Input Decoder circuit for Balanced Ternary (BT)
The Input Decoder for balanced ternary numbers is shown
in Fig. 1. It produces I−trit as 1, when the input given to the
circuit is -1, else if the inputs are 0and 1the I−trit is −1.
The I0trit is 1 when input given is 0, else for inputs −1and
1, the output is −1. Similarly, I+trit is 1 only when input is 1,
otherwise the output is −1.I−trit is generated by passing the
input Ithrough an NNOT gate. I+trit is generated by passing
the input through a PNOT gate cascaded with a NOT gate. I0
trit of Iiis generated by passing the inputs I−and I+trit
through OR gate cascaded with a NOT gate. The truth table
for input Decoder circuit for generating the balanced ternary
numbers I[I−I+I0]exploiting the logic expressions in Eq. 1
is given in Table I.
I−=N N OT (I)
I+=P N OT (I)
I0=I−+I+
(1)
II−I0I+Ii
-1 1 -1 -1 1-1-1
0 -1 1 -1 -11-1
1 -1 -1 1 -1-11
TABLE I: Truth table for the input Decoder circuit using
Balanced Ternary
Fig. 1: Input Decoder Circuit using Balanced Ternary
B. Input Decoder circuit to use Binary Gates in other Units
The arrangement of the proposed Decoder unit is shown in
Fig. 2. Here, the I−trit is 1when the input is −1, but for
inputs 0and 1the output is 0.I0trit is observed as 1, when
the given input is 0, else it is 0. Similarly, I+trit is 1 when
the input given is 1else it is 0. I−trit is generated by passing
the input Ithrough NNOT gate cascaded by two RTD gates,
followed by a NOT gate. Similarly, I+trit of Iiis generated
by passing Ithrough PNOT gate cascaded with an RTD gate.
I0trit of Iiis generated by passing the values of I−and I+
trit through an OR gate. The output of OR gate via an RTD
gate followed by a NOT gate generates the required output.
The logic expression of proposed input Decoder, in this case,
is shown in Eq. 2. The corresponding truth table of the circuit
is shown in Table II.
I−=RT D(RT D(N N OT (I)))
I+=RT D(P N OT (I))
I0=RT D(I−+I+)
(2)
II−I0I+Ii
-1 1 0 0 100
0 0 1 0 010
1 0 0 1 001
TABLE II: Truth table for the input Decoder circuit using
Binary Gates
Fig. 2: Input Decoder Circuit using Binary Gates in output
generating units
C. Input Decoder for Binary Coded Balanced Ternary (BCBT)
As the name suggests, the BCBT encoding scheme [9]
permits binary computers to manipulate ternary data. As long
as we have binary peripherals to process ternary data, these
encoding schemes are required. Here balanced ternary values
are represented as pairs of binary numbers. This Input Decoder
for BCBT takes each input from the user I0to Id as Iin 2 bit
format, where −1is entered as 11 (decimal 3), 0 is entered
as 00 (decimal 0), and 1 is entered as 01 (decimal 1), and
generates the 3bit number Ii. The I−bit is 1 when input
given is 11 else it is 0, I0bit is 1 when input given is 00 else
it is 0 and I+bit is 1 when input given is 01 else it is 0. The
circuit of the Input Decoder is shown in Fig. 3. I−bit of Ii
is generated by passing the two bits of Ithrough AND gate.
I+bit of Iiis generated by passing the two bits of Ithrough
XOR gate. I0bit of Iiis generated by passing the two bits of
Ithrough NOR gate. The logic expression is given Eq. 3 and
the corresponding truth table is given in Table III.

I−=I1⊕I0
I+=I1I0
I0=I1+I0
(3)
II−I0I+Ii
11 1 0 0 100
00 0 1 0 010
01 0 0 1 001
TABLE III: Truth table for the input Decoder circuit using
Binary Coded Balanced Ternary (BCBT)
Fig. 3: Input Decoder Circuit using Binary Coded Balanced
Ternary (BCBT)
III. OUT PU T DEC OD ER
The Output Decoder takes the output of the circuit units
in the form of O0and O1as inputs and generates the final
output as O. Thus, O00and O01together form the output trit
O0,O30and O31create the output trit O3and O90and O91
create the output trit O9. Three output Decoder circuits are
proposed to deal with three different number formats.
A. Output Decoder circuit for Balanced Ternary
Circuit of the proposed Output Decoder for a balanced
ternary number is shown in Fig. 4b. The output Ois obtained
by passing first O0trits through an RTD gate followed by an
inverter. O1trit is passed directly to the input of an OR gate
to generate the final result. The logic expression for the output
Decoder is given Eq. 4 and the corresponding truth table is
depicted in Table 4a. The output Decoder circuit in balanced
ternary format is shown in Fig. 4b. Thus,
O01=RT D(O0)
O11=O1
O=O01+O11=RT D(O0) + O1
(4)
O0O1O
-1 -1 -1
1 -1 0
-1 1 1
(a) Truth Table (b) Circuit
Fig. 4: Output Decoder for Balanced Ternary
B. Output Decoder circuit using Binary Gates in other Units
To generate the output trit Oin this scheme, first the O0
trit is passed through an RTD gate to generate O01and the
O1trit through a PNOT gate cascaded with an inverter to
generate O11. The two trits thus obtained are passed through
an OR gate to generate O. The logic expression guiding the
outputs of the Decoder unit can be given using Eq. 5. The
proposed Output Decoder circuit to use binary gates in other
units is given in Fig. 5b and the corresponding truth table is
shown in Table 5a.
O01=RT D(O0)
O11=P N OT (O1)
O=O01+O11=RT D(O0) + P N OT (O1)
(5)
O0O1O
0 0 -1
1 0 0
0 1 1
(a) Truth Table (b) Circuit
Fig. 5: Output Decoder Using Binary Gates in output gener-
ating units
C. Output Decoder circuit for Binary Coded Balanced
Ternary
To generate the output trit Ocorresponding to a Binary
Coded Balanced Ternary number, the O0trit is passed through
an NOT gate to create O01bit. The O1and O0bits are passed
through XNOR gate which is equivalent to an XOR gate with
one of its inputs inverted to create O11bit. The two bits
obtained are used to generate the final output O. The logic
expressions guiding the outputs of the Decoder unit can be
given using Eq. 6. Circuit of the Output Decoder for BCBT
is given in Fig. 6b and the corresponding truth table is given
in Table 6a.
O01=O0
O11=O0O1
O= [O11O01]
(6)
O0O1O
0 0 11
1 0 00
0 1 01
(a) Truth Table (b) Circuit
Fig. 6: Output Decoder for Binary Coded Balanced Ternary
IV. TER NA RY ENCODER
Encoders are multi-input combinational logic circuits that
consider all input lines concurrently and then turn them into

an equivalent single encoded output. In a binary Encoder
there are noutput lines corresponding to 2ninput lines.
Encoders compress several ternary inputs into smaller number
of outputs. The block diagram of the Encoder circuit is shown
in Fig. 7.
TABLE IV: 14:3 Trit Encoder Truth Table
Id Ic Ib Ia I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 O9 O3 O0
00000000000000 -1-1-1
0000000000000-1 0 0 0
00000000000001 0 0 0
000000000000-10 0 0 -1
00000000000010 0 0 1
00000000000-100 0 -1 1
00000000000100 0 1 -1
0000000000-1000 0 -1 0
00000000001000 0 1 0
0 0 0 0 0 0 0 0 0 -1 0 0 0 0 0 -1 -1
00000000010000 0 1 1
00000000-100000 -1 1 1
00000000100000 1 -1-1
0000000-1000000 -1 1 0
00000001000000 1 -1 0
0 0 0 0 0 0 -1 0 0 0 0 0 0 0 -1 1 -1
00000010000000 1 -1 1
00000-100000000 -1 0 1
00000100000000 1 0 -1
0000-1000000000 -1 0 0
00001000000000 1 0 0
000-10000000000 -1 0 -1
00010000000000 1 0 1
00-100000000000 -1-1 1
00100000000000 1 1 -1
0 -1 0 0 0 0 0 0 0 0 0 0 0 0 -1 -1 0
01000000000000 1 1 0
-10000000000000 -1-1 -1
10000000000000 1 1 1
m+1:n+1
encoder
I0
I1
Im
O0
O1
On
I2
Fig. 7: Block diagram of the Encoder Circuit
In ternary, each trit of number can store three distinct values,
−1,0and 1, so a 3-trit ternary number can represent decimal
numbers ranging from −13 to +13, or −1−1−1to 111.
Thus, an Encoder can have 14 distinct inputs ranging from
0 to 13 or 0 to ’d’ in hexadecimal and can represent them
using 3 ternary digits. Each of the 14 input lines has an option
of having an input of either ’-1’ or ’1’, which signify the
negative and positive value of the number to be encoded by
the Encoder. Fig. 7 shows the block diagram of an Encoder
circuit, consisting of m+ 1 input lines and n+ 1 output lines.
The number of output lines that is sufficient to the encode a
given range of input signals using an Encoder circuit can be
expressed using the following relation,
m= Σn
x=03x(7)
where, xranges from 0to n. Thus, for 3output lines, n
ranges from 0to 2and m= 30+ 31+ 32= 13, which can
encode m+ 1 = 14 input lines (1is added to mbecause of
the I0input line).
A. 14:3 Trit Encoder
In the present work we propose the design and architecture
of a 14 : 3 Encoder circuit. 14 : 3 Ternary Encoder circuit with
three output lines O0, O3, O9capable to encode the inputs
from I0to Id. In Table IV, the truth table of the proposed
circuit is given. The logic ’1’ is taken as positive input of the
number and logic ’-1’ is taken as negative input of the number.
Logic ’0’ means the input is not given by the user
B. Logic Expressions for Output Generating Units
The logic expressions for the output generating units O0, O3
and O9are found by finding their minterms corresponding to
logic 0and logic 1.
1) Equations for O0: The logic expressions for O0can
be given by finding minterms for O00and O01separately as
shown in Eq. 8. The circuit implementing the logic for O00
and O01are shown in Fig. 8 and Fig. 9 respectively.
O00=I00+I30+I60+I90+Ic0
O01=I1++I2−+I4++I5−+I7+
+I8−+Ia++Ib−+I d+
(8)
2) Equations for O3: The logic expressions for O3can be
expressed by finding minterms for O30and O31separately as
shown in Eq. 9. The circuit implementing the logic for O30
and O31are shown in Fig. 10 and Fig. 11 respectively.

O30=I00+I10+I80+I90+Ia0.
O31=I2++I3++I4++I5−+I6−
+I7−+Ib++Ic++I d+.
(9)
3) Equations for O9: The logic expressions for O9can be
expressed by finding minterms for O90and O91respectively
as shown in Eq. 10. The circuit implementing the logic for
O90and O91are shown in Fig. 12 and Fig. 13 respectively.
O90=I00+I10+I20+I30+I40
O91=I5++I6++I7++I8++I9+
+Ia++Ib++I c++Id+
(10)
C. Circuit Design of different Output Generating Units
Using the logic expressions from Eq. 8-10 developed in
Section IV-B, the output generating circuits are developed and
are shown from Fig. 8-13.
Fig. 8: The circuit for generating O00
Fig. 9: The circuit for generating O01
Fig. 10: The circuit for generating O30
Fig. 11: The circuit for generating O31
Fig. 12: The circuit for generating O90
Fig. 13: The circuit for generating for O91
Using the proposed input and output Decoder circuits, a
14 : 3 Encoder circuit can be introduced in ternary computing
as shown in Fig. 14.
Fig. 14: The proposed 14:3 Encoder Circuit
V. TH E PRO PO SE D TER NARY DECODER CIRCUIT
Decoders are multi-input combinational logic circuits that
consider a single encoded input and then give an output
corresponding to a unique combination of the input. In a binary
Decoder there are 3m+1 output lines corresponding to ninput
lines. In Ternary, each trit of number can store three distinct
values, -1, 0 and 1, so, a 3-trit ternary number can represent
decimal numbers ranging from −13 to 13, or −1−1−1to
111. Thus, a Decoder can have 14 distinct outputs ranging
from 0 to 13 or 0 to ’d’ in hexadecimal, given out by using
3 ternary inputs. Each of the 14 output lines has an option
of having an output of either ’-1’ or ’1’, which signify the
negative and positive value of the number to be decoded.
Fig. 15 shows the block diagram of an (n+ 1) : (m+ 1)
Decoder circuit, consisting of ’0’ to ’n’ input lines and ’0’ to
’m’ output lines. The number of output lines that is sufficient

to the decode a given range of input signals using a Decoder
circuit can be expressed using the following relation,
m= Σ3x(11)
where, x ranges from 0 to n. Thus, for 3 input lines, m=
30+ 31+ 32= 13. Thus it is able to produce m+ 1 = 14
output lines (1is added to mbecause of O0line). The block
diagram of the Decoder circuit is shown in Fig. 15. The truth
table of the 3 : 14 Decoder circuit is shown in Table V. The
Decoder generates the output from O0to Od corresponding
to three input lines A0, A3, A9.
n+1:m+1
decoder
A0
A1
An
O0
O1
O2
Om
Fig. 15: Block diagram of Decoder Circuit
TABLE V: Truth Table of the 3:14 Decoder
A9 A3 A0 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 Oa Ob Oc Od
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 -1 0 -1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 -1 1 0 0 -1 0 0 0 0 0 0 0 0 0 0 0
0 1 -1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 -1 0 0 0 0 -1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0 -1 -1 0 0 0 0 -1 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0
-1 1 1 0 0 0 0 0 -1 0 0 0 0 0 0 0 0
1 -1 -1 0 0 0 0 0 1 0 0 0 0 0 0 0 0
-1 1 0 0 0 0 0 0 0 -1 0 0 0 0 0 0 0
1 -1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
-1 1 -1 0 0 0 0 0 0 0 -1 0 0 0 0 0 0
1 -1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0
-1 0 1 0 0 0 0 0 0 0 0 -1 0 0 0 0 0
1 0 -1 0 0 0 0 0 0 0 0 1 0 0 0 0 0
-1 0 0 0 0 0 0 0 0 0 0 0 -1 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
-1 0 -1 0 0 0 0 0 0 0 0 0 0 -1 0 0 0
1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0
-1 -1 1 0 0 0 0 0 0 0 0 0 0 0 -1 0 0
1 1 -1 0 0 0 0 0 0 0 0 0 0 0 1 0 0
-1 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 -1 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
-1 -1 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 -1
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
A. 3:14 Decoder
The architecture of the proposed 3 : 14 Decoder circuit
is presented in this section. 3 : 14 Ternary Decoder circuit
with fourteen output lines O0to Od is capable to decode
three inputs A9, A3and A0. In Table V, the truth table of the
proposed circuit is shown. The logic ’1’ is taken as positive
output of the number and logic ’-1’ is taken as negative output
of the number. Thus, when all the three input trits are 0, the
output trit O0is only high to signify its weighted-ternary
equivalence to 0. When A9A3A0 = 00 −1,O1 = −1,
signifying that its weighted equivalence in ternary is −1. When
A9A3A0 = 001, the output O1=1with all other outputs
logic ’low’, to signify that the weighted equivalence of the 3
trit number is 1. With this logic as convention the truth table
for the Decoder circuit is constructed.
B. Implementation of Decoder Units
The logic expressions for the outputs of the 3 : 14 Decoder
circuit, i.e., O0to Od can be given by finding minterms
separately for O00to Od0and O01to Od1. These minterms
from O00to Od0are generated using Decoder0and the
minterms from O01to Od1are generated using Decoder1
circuit. The equations for the minterms from Decoder1and
Decoder1are generated and are shown in Table VI. The
circuit design for the Decoder 0(D0) is given in Fig. 16 that
employ Inverter-OR-AND gate combination to implement 14
different functions except the NOT-OR combination for the
O00output. The circuit design for the Decoder1(D1) is given
in Fig. 17 and generates 14 different functions corresponding
to O01to Od1using AND gates. We have minimized the
logic expressions wherever possible to reduce the circuitry.
As for example, the output lines from Decoder0, i.e., O30
and O90are obtained from the reduced form of the logic
expressions shown in Table VI. Thus, in these cases, it is
possible to replace 3-input gates with 2-input gates in level
2 of the design.
From each of the inputs A9,A3and A0there are three lines
ejecting out that correspond to the three logic levels that a trit
can possess. A particular logic input with its logic level is
selected based on the logic expressions of the Decoder units.
Exploiting the proposed Decoder units the 3 : 14 Decoder
circuit shown in Fig. 18 is developed.

TABLE VI: Logic expressions for the outputs of D0and D1.
Equations for Decoder 0 Equations for Decoder 1
Output O00=(A90+A30+A00)Output O01=(A90A30A00)
Output O10=(A90+A30+A0−)(A90+A30+A0+)Output O11=(A90A30A0+)
Output O20=(A90+A3−+A0+)(A90+A3++A0−)Output O21=(A90A3+A0−)
Output O30=(A90+A3−+A00)(A90+A3++A00)Output O31=(A90A3+A00)
Output O40=(A90+A3−+A0−)(A90+A3++A0+)Output O41=(A90A3+A0+)
Output O50=(A9−+A3++A0+)(A9++A3−+A0−)Output O51=(A9+A3−A0−)
Output O60=(A9−+A3++A00)(A9++A3−+A00)Output O61=(A9+A3−A00)
Output O70=(A9−+A3++A0−)(A9++A3−+A0+)Output O71=(A9+A3−A0+)
Output O80=(A9−+A30+A0+)(A9++A30+A0−)Output O81=(A9+A30A0−)
Output O90=(A9−+A30+A00)(A9++A30+A00)Output O91=(A9+A30A00)
Output Oa0=(A9−+A30+A0−)(A9++A30+A0+)Output Oa1=(A9+A30A0+)
Output Ob0=(A9−+A3−+A0+)(A9++A3++A0−)Output Ob1=(A9+A3+A0−)
Output Oc0=(A9−+A3−+A00)(A9++A3++A00)Output Oc1=(A9+A3+A00)
Output Od0=(A9−+A3−+A0−)(A9++A3++A0+)Output Od1=(A9+A3+A0+)
Fig. 16: The proposed D0Circuit
Fig. 17: The proposed D1Circuit
Fig. 18: The proposed 3:14 Decoder Circuit

VI. COMPLEXITY OV ERVIEW
The time complexity of the 14:3Ternary Encoder circuit
(without Input and Output Decoders) is calculated as O(4).
The time complexity is the same when the Encoder is im-
plemented in binary and BCT. The time complexity of the
3 : 14 Ternary Decoder circuit (excluding Input and Output
Decoders) is also O(4). When alternative number formats are
used, the time complexity of binary Encoders and Decoders
remains the same. Also the latency in these cases are found to
be the same, which is equal to 4. The comparison of the time
complexity of the proposed circuits, when compared to the
binary is jotted down in Table VIII. The depth complexity of
the Encoder and Decoder circuit is observed to be O(3). The
hardware complexity of the proposed circuits are compared to
binary and BCT equivalents utilising the number of gates (gate
count) necessary to construct Encoder and Decoder circuits as
shown in Table VII.
It is observed that the proposed circuits (both Encoder
and Decoder) have a gate count of 36 (both for Ternary
and BCT), which is less than the gate count of the 32 : 5
binary Encoder circuit, i.e., 75, without the input Decoder and
Decoder circuits. The value of the same involving input and
output Decoders counts up to 101 for Ternary Encoder and
84 for BCT Encoder. The gate counts of the Ternary circuit is
observed by converting all three input logic gates to two input
logic gates. Otherwise the circuit could have been realized
with a lower number of gate counts. Similarly, for designing
3 : 14 Ternary Decoder circuit, the gate count without input
and output Decoders is 98 which is smaller than the gate count
in binary i.e., 133 and is equivalent to BCT i.e., 98. Also,
utilizing Input and Output Decoders in the design the gate
count increases to 152 in Ternary Decoder and 135 in BCT
Decoder. It is also seen that the Transistors required to make
the entire circuit in Ternary is less than making the circuit in
BCT or Binary.
TABLE VII: Comparison of the gate counts for Encoder and Decoder circuits using different formats
Circuit Different
formats AND OR NOT Gate
count
Input
Decoder
Output
Decoder
Total
#
Total
Transistors
Encoders
32:5 Binary 0 75 0 75 0 0 75 450
14:3 Ternary 0 36 0 36 56 9 101 414
14:3 BCT 0 36 0 36 42 6 84 492
Decoders
5:32 Binary 128 0 5 133 0 0 133 778
3:14 Ternary 41 48 9 98 12 42 152 726
3:14 BCT 41 48 9 98 9 28 135 718
TABLE VIII: Comparison of the time complexity to implement Encoder and Decoder circuits using different number formats
Circuit Number
format
Time complexity Latency
without
i/p and o/p
Decoder
with
i/p and o/p
Decoder
without
i/p and o/p
Decoder
with
i/p and o/p
Decoder
Encoder
32:5 Binary O(4) - 4 -
14:3 Ternary O(4) O(11) 4 11
14:3 BCT O(4) O(7) 4 7
Decoder
5:32 Binary O(4) - 4 -
3:14 Ternary O(4) O(11) 4 11
3:14 BCT O(4) O(7) 4 7
VII. DISCUSSION
The operation that is carried out using Balanced Ternary
logic in in the Output Generating Units and the Input and
Output Decoder units of the Ternary Encoder circuit uses
Ternary logic gates. The Input and Output Decoders as well
as the output generating units for the Binary Coded Balanced
Ternary, on the other hand, can be implemented using simple
binary logic gates without the dire need of Ternary logic
gates. Also, using the Input and Output Decoders for Balanced
Ternary operation in Decoder circuits, such as Decoder 0
and Decoder 1 Units use Ternary logic gates to carry out
the operation. On the other hand, using the Binary Coded
Balanced Ternary format for Input and Output Decoders, i.e.,
the Decoder 0 and Decoder 1 units use binary logic gates to
carry out the operation. Changing between Binary and Ternary
gates will have no effect on the circuit provided for these units,
and the gate location and the nature will remain the same as
before (Ternary AND gate will be replaced by Binary AND
gate, Ternary OR gate will be replaced by Binary OR gate and
so on). This attribute can be leveraged to reduce the amount
of hardware necessary, as well as to make the circuit more
flexible, allowing it to be used in both Ternary and binary
operations.
The Encoder and Decoder circuits in literature [13] uses
unbalanced Ternary format and uses CNTFETs to create the
desired functions with only two logic levels, i.e., the logic
level is ’true’, if the input is 2 and ’false’ when inputs are
0,1. This method increases the number of input and output
lines for both the Encoder and Decoder circuits. Thus, the
number of input lines for Encoder circuit is 3n, where nis
the number of output lines generated by the Encoder.
Whereas the proposed Encoder and Decoder circuits exploit

all the possible logic levels in Balanced Ternary, i.e., using
−1state to indicate a negative number and +1 to indicate a
positive number. 0is regarded as the false state of the input and
output. This reduces the number of input lines of the Encoder
to (3n+ 1)/2, as each input or output line can now denote
both the positive and negative magnitude of a number, thereby
reducing the complexity of the circuit. This design is also
flexible as it can be used in both Balanced Ternary as well as
BCBT applications without changing the overall design of the
circuit and the performance of the same.
VIII. CONCLUSION
This article has introduced balanced Ternary Encoder and
Decoder as essential circuit designs. The circuits can be im-
plemented in a variety of ways, making them highly versatile.
For Binary Coded Balanced Ternary, where 0is encoded as
00,1as 01, and −1as 11 in binary, the functionality of the
proposed circuit can be implemented by inserting specified
input and output Decoder units. A comparison table is also
given that compares three different circuits in terms of the
gate counts. It is observed that gate counts (without input
and output Decoder)in the proposed Encoder and the Decoder
circuits remain the same. While binary circuits have a lower
computational complexity, the Ternary circuits can process
larger data, i.e., log2(3)=1.58 bits of data/trit. It requires a
higher amount of gates compared to the binary counterparts
to implement a function in Ternary logic because the minterms
for the output logic ’high’, and the minterms for the output
logic ’low’, have to be dealt with separately. Since, Ternary
can compute larger data compared to binary, the overall
effect is balanced. In the future, we can build higher order
Encoders and Decoders, along with different types of encoding
techniques that can be able to build and implement the required
logic on balanced Ternary numbers by reducing errors and
hardware requirements in comparison to binary. Additionally,
Ternary logic can be used to create some logic blocks, as well
as certain combinational and sequential blocks efficiently, that
can be compatible with both the integer and floating point
arithmetic.
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