A CMOS quadrature VCO with subharmonic and injection-locked techniques

Abstract

A 1-V quadrature voltage-controlled oscillator (QVCO) using subharmonic and injection-locked techniques (SHIL-QVCO) is presented. Instead of using the traditional transformer-coupling LC tank with a large area to implement the quadrature output, we use a frequency-doubled differential pair with an injection-locked method. The proposed QVCO is implemented with a TSMC 0.18- μm 1P6M CMOS process having a 1.4 × 0.67 × mm² chip area. This QVCO has the advantages of low phase noise and low power consumption. Experimental results show that the QVCO has a phase noise of - 126 dBc/Hz at an offset frequency of 1 MHz and a power consumption of 4.9 mW to achieve a 186 figure of merit. Moreover, a tuning frequency between 2.17 and 2.52 GHz can be obtained with a tuning voltage range of 0-1 V for the IEEE 802.15.4.

Full text

IEEE TRA NSACTI ONS ON CIR CUI TS AND SYSTEM S—II: EX PRE SS BRIE FS, VOL. 57, NO. 11, NOVEMBER 2010 843
A CMOS Quadrature VCO With Subharmonic
and Injection-Locked Techniques
Shuenn-Yuh Lee, Member, IEEE, Liang-Hung Wang, Student Member, IEEE, and Yu-Heng Lin
Abstract—A 1-V quadrature voltage-controlled oscillator
(QVCO) using subharmonic and injection-locked techniques
(SHIL-QVCO) is presented. Instead of using the traditional
transformer-coupling LC tank with a large area to implement
the quadrature output, we use a frequency-doubled differential
pair with an injection-locked method. The proposed QVCO is
implemented with a TSMC 0.18-µm 1P6M CMOS process having
a1.4×0.67 mm2chip area. This QVCO has the advantages
of low phase noise and low power consumption. Experimental
results show that the QVCO has a phase noise of −126 dBc/Hz at
an offset frequency of 1 MHz and a power consumption of 4.9 mW
to achieve a 186 figure of merit. Moreover, a tuning frequency
between 2.17 and 2.52 GHz can be obtained with a tuning voltage
range of 0-1 V for the IEEE 802.15.4.
Index Terms—Frequency doubled, injection locked, oscilla-
tor, quadrature, radio-frequency complementary metal–oxide–
semiconductor (RF CMOS), subharmonic, voltage-controlled
oscillator (VCO).
I. INTRODUCTION
AVOLTAGE-controlled oscillator (VCO) is indispensable
in the operations of fully integrated receiver architectures,
including orthogonal superheterodyne, direct conversion, and
low intermediate frequency (IF) [1]. The receiver adopting
a direct-conversion architecture or a low-IF architecture (in
Fig. 1) has the benefits of flexibility, low cost, and high integra-
tion; however, quadrature outputs (0◦,90
◦, 180◦, and 270◦)are
required in the fully balanced mixer for I/Q modulation or de-
modulation. Obviously, developing a quadrature VCO (QVCO)
with low phase noise and minimum power consumption is
important in creating this low-IF receiver.
To obtain good phase noise, the quadrature signals can be
developed using a cross-coupled differential pair topology with
two symmetric LC-tank VCOs, as shown in Fig. 2 [2]. These
traditional QVCOs can be classified into several categories with
different coupling mechanisms. One popular method is based
on coupling transistors in either parallel or series with the res-
onator [2], [3]. The drawback of the method is the design trade-
off between the phase noise and the phase imbalance. Other
methods include adopting common-mode inductive coupling
with a transformer [4] or applying second harmonic injection to
Manuscript received June 24, 2010; accepted September 13, 2010. Date of
publication October 21, 2010; date of current version November 17, 2010.
This work was supported in part by the Chip Implementation Center, by the
Wireless Communication Laboratories (WC Lab.), and by the National Science
Council, Taiwan, under Grant NSC 99-2628-E-194-032, Grant NSC 99-2220-
E-194-001, and Grant NSC 99-2220-E-194-006. This paper was recommended
by Associate Editor A. Liscidini.
The authors are with the Department of Electrical Engineering, National
Chung Cheng University, Chiayi 621, Taiwan (e-mail: ieesyl@ccu.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2010.2082990
Fig. 1. Low-IF receiver architectures.
Fig. 2. Conventional cross-coupled QVCO.
the cross-coupled switching transistors [5], [6]. These methods
enforce an antiphase between the two differential VCOs. The
drawbacks of these methods include the large chip size in the
implementation, which is brought about by the transformer’s
requirement to couple the quadrature outputs, and the large
power consumption requirement due to the prevalence of more
current paths during the development of quadrature signals.
This brief employs the subharmonic and injection-locked
techniques in two cross-coupled LC-tank VCOs to generate the
quadrature outputs. The 1/f flicker noise, channel thermal noise,
and required bias current can be reduced with this coupling mech-
anism to achieve low phase noise and minimum power con-
sumption. The proposed QVCO with a 2.4-GHz operational
frequency was implemented in the TSMC 0.18-μmCMOSpro-
cess. The QVCO consumed 4.9 mW under a 1-V supply voltage.
This brief is organized as follows. Section II presents the
analysis of the proposed QVCO architecture and the analysis
of the quadrature topology with the subharmonic frequency-
doubled method, orthogonal injection-locked phenomenon, and
phase noise. Section III presents the experimental results and
the comparison with the other papers. Finally, the conclusion is
presented in Section IV.
II. PROPOSED QUADRATURE VCO ANALYSIS
Fig. 3 shows the schematic of the proposed subharmonic
and injection-locked QVCO (SHIL-QVCO). The QVCO can
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844 IEEE TR ANSACTIO NS ON CI RC UIT S AND SY STEMS —II: EXP RES S BRIEFS, VOL. 57, NO. 11, NOVEMBER 2010
Fig. 3. Proposed QVCO.
Fig. 4. Frequency-doubled structure.
be divided into three of the following parts:
1) Two cross-coupled pairs with the current-reuse tech-
nique: Compared with the conventional cross-coupling
QVCO with eight current paths (see Fig. 2), the
current-reuse QVCO topology with both n-channel
metal–oxide–semiconductor (NMOS) and p-channel
metal–oxide–semiconductor (PMOS) transistors [7] can
be operated with only half the amount of dc current
because only four current paths are used to save power
consumption. Moreover, the current-reuse circuit under
push–pull operation can possess positive and negative
enhanced gains to improve the circuit linearity [8].
2) LC-tank resonator: The resonator oscillates the desired
frequency at the quadrature output, which is controlled
by the tuning voltage Vtune of the varactor Cvar .
3) Frequency doubled and injection locked: The proposed
subharmonic injection-locked QVCO uses an NMOS
(PMOS) frequency-doubled differential pair, instead of
traditional transformer-feedback VCOs, to double the
resonant frequency. Moreover, the doubled frequency will
be injected into the cross-coupled pair to generate the
quadrature signals. Fig. 5 shows the basic concept. If
we assume that the sinusoidal output signals of Oscilla-
tor_I are cos(ωt+θ)and cos[ωt+(θ+π)], the output
signals of the frequency doubler are cos(2ωt+2θ)and
cos[2ωt+(2θ+2π)], respectively. If the signals are in-
jected into Oscillator_Q with a locking phase of φand
if signal mixing occurs according to (2θ+2π)−(φ+
π)=φ, the difference of π/2between θand φin the dif-
ferential output of mixer can be obtained. Therefore, the
subharmonic injection-locked technique can generate the
quadrature signals without transformers, thereby greatly
reducing the chip size.
A. Subharmonic Frequency Doubling
The principle of frequency doubling can be referred to as
subharmonic mixing or even-harmonic mixing [8]. The double-
frequency circuit is constructed with the parallel connection of
a transistor pair (MCN1 and MCN2),asshowninFig.4.The
fundamental frequency of I (or Q) is canceled at the virtual
ground node (VCOM). However, the even-harmonic frequency
is induced at the drain and at the source of the transistor
pair called subharmonic circuit [8]. Therefore, the subharmonic
circuit provides a doubled frequency and isolates the leakage of
the fundamental frequency of I (or Q).
To analyze the circuit behavior, the inherent square-law cur-
rent model is adopted for circuit-tendency analysis. Equation
(1) describes the square-law model with the channel-length
modulation, where βn=(1/2)μnCOX(W/L)is the transcon-
ductance parameter; vin and VOV are defined as the input signal
and the overdrive voltage, respectively, and λnis the channel-
length modulation coefficient. The equation is expressed as
I=βn(VOV +vin)2(1 + λnVDS ).(1)
Assuming a sinusoidal input signal with an amplitude aLO,
the equation for vin is defined as
vin =v+
I=−v−
I=vI
2=aLO
2cos (ωIt).(2)
According to (1) and (2), the drain current (I+
Iand I−
I)ofthe
transistors (MCN1 and MCN2) can be written as follows:
I±
I∼
=βnV2
OV,I +1
4v2
I±VOV,I ·vI(1 + λnΔV)(3)
where VOV,I is the overdrive voltage of transistors.
Thus, the total current at the virtual ground node (VCOM)is
equal to iCOM and is expressed by
iCOM =2βnV2
OV,I +a2
LO
8+βna2
LO
4cos(2ωIt)

×(1 + λnΔV)=IIDC +i2I.(4)
In (4), the fundamental frequency of the I phase (or Q phase)
signal is filtered, and the doubling-frequency signal is produced
at the node VCOM.
B. Orthogonal Injection Locked
Fig. 5 shows the equivalent signal block for the proposed
subharmonic injection-locked QVCO. The cross-coupled pair
of the oscillator is similar to a single balance mixer. The
injected current has been mixed with the output signal of the
LC resonator.
We assume that the unlocked differential output signal is
II=IQ=cos(ω0t).(5)
Based on (4), the required injected currents, dc (IDC), and
double-frequency signal (Iinj cos(2ω0t)) are derived as
Iinj,I =IDC +Iinj cos (2ω0t).(6)
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LEE et al.: CMOS QUADRATURE VCO WITH SUBHARMONIC AND INJECTION-LOCKED TECHNIQUES 845
Fig. 5. Equivalent circuit of the subharmonic injection-locked VCO.
Fig. 6. (a) Phase shift with injected current. (b) Frequency shift with injected
current.
Fig. 7. (a) Phase difference between the injection-locked current and the
oscillation current. (b) Phase shift in an injection-locked condition.
During the oscillation, a total phase shift of 360◦around the
feedback loop is retained. If current is injected into the LC
tank, the resonator must introduce a negative phase (−φ0)to
compensate for the phase shift (φ0)of the VCO. Additionally,
the oscillation frequency is immediately varied from ω0to ωinj,
as depicted in Fig. 6(a). According to the mixing principle, the
output current (Iout)of the mixer is denoted as
Iout =IDC cos(ωinjt)+Iinj cos(ωinj t)+Iinj cos(3ωinjt).(7)
The third-order term Iinj cos(3ωinjt)is filtered by the LC-
tank bandpass filter. Simultaneously, a new current phase vector
(IT), synthesized by the IDC and the Iinj, is produced to cancel
the phase shift initiated by the VCO. Under the oscillation,
the dc current (IDC)must be operated in phase with Vout
[Fig. 6(b)].
If the amplitude and frequency of Iinj are chosen properly,
the circuit oscillates at ωinj rather than at ω0, and injection
locking occurs [9]. Fig. 7(a) presents the phase vector IT
synthesized by IDC and Iinj under the condition ωinj =ω0.The
Fig. 8. Phase error versus the ratio of the injection-locked current and the
oscillation current.
tank also contributes phase; therefore, the angle φ0between IT
and IDC is employed to eliminate the tank phase shift.
With the ωinj departing from ω0, the angle between IDC and
ITis also increased to match the increasing phase shift. Conse-
quently, the IDC will rotate counterclockwise. The relationship
between the angle θand φ0can be derived by [9]
sin φ0=Iinj
IT
sin θ=Iinj sin θ
I2
DC +I2
inj +2IDC Iinj cos θ
.(8)
On the contrary, a decreasing Iinj under a constant φ0results
in the clockwise rotation of the IDC. According to the deriva-
tion in [9], this can be illustrated as
sin θ≈2Q
ω0
(ω0−ωinj)IDC
Iinj
(9)
where quality factor Q=RP/Lω. Under the design conditions
of Iinj IDC and ω0−ωinj =ω0·Iinj/(2Q·IDC ),asshown
in Fig. 7(b), the 90◦phase difference is obtained to implement
the quadrature signal. According to the simulation result in
Fig. 8, the ratio of 0.31 between injection-locked current and dc
current (Iinj/IDC =0.31) was chosen to achieve a minimum
phase error at the quadrature output.
C. Analysis of the Phase Noise in the QVCO
The equivalent noise model of a quadrature LC VCO cir-
cuit with the equivalent inductor and capacitor model and the
cross-coupled differential circuit is shown in Fig. 9 [7], [10].
This model was employed to calculate the phase noise of the
proposed QVCO. Generally, the noise sources of the oscillator
[11] consist of the parasitic resistance noise from the LC tank
(i2
RT=(v2
RT/R2
T)=(4kT/RT)), the channel thermal noise
(i2
d=2kTγ(Ibias /εsatl)),1/f noise in the transistor at low
frequencies (i2
f/Δf=Kg2
m/Coxwlf ), and the gate noise of
the transistor (i2
g=8kTδ(ω2
oC2
gsεsatl/5Ibias )). For the analy-
sis, we assume that gm=gmn =gmp and gm=gmn =gmp.
Using this assumption, the phase noise of the half QVCO circuit
can be approximated as (10), shown at the bottom of the next
page [7], [10]–[12], where P0≈V2
tank/RT,RTis the LC-
tank parasitic resistor, Kis the flicker noise coefficient, lis
the channel length, γis the channel thermal noise, εsat is the
velocity saturation field strength, δis the coefficient of the gate
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846 IEEE TR ANSACTIO NS ON CI RC UIT S AND SY STEMS —II: EXP RES S BRIEFS, VOL. 57, NO. 11, NOVEMBER 2010
Fig. 9. Equivalent noise model of the proposed subharmonic injection-locked
QVCO.
Fig. 10. Phase noise versus the biased current of the QVCO with an oscillation
frequency of 2.35 GHz.
Fig. 11. Microphotograph of the proposed SHIL-QVCO.
noise, and Ibias is the bias current provided by the inductor
chock.
A systematic design method is developed to achieve a better
figure of merit (FOM) as described in
FOM= 20 log10ω0
Δω−L{Δω}−10 log10 PD
1mW .(11)
Fig. 12. Oscillation frequency of simulation versus measurement results.
Fig. 13. Measured phase noise at the 1-MHz offset frequency from the carrier
frequency of 2.17 GHz.
Fig. 14. Measurement results of power imbalance versus phase error.
In (11), ω0is the oscillation frequency, Δωis the offset
frequency, L{Δω}is the phase noise at Δω, and PDis the
power dissipation of the measured QVCOs. Equation (10)
shows that the phase noise can be lowered by decreasing the
resonant frequency or by increasing the quality factor of the
LC tank. However, the two parameters are limited by receiver
specification and inductor fabrication. For the circuit design, the
phase noise of the QVCO is inversely proportional to the bias
current Ibias. Therefore, according to the simulation shown in
Fig. 10, a 2.4-mA bias current of the half QVCO is employed
to achieve a lower phase noise.
L{ωm}=v2
out,total
V2
tan k
=kT
RT+2Kg2
mp
Coxwlf +4kT γ Ibias
εsatl+24kT δ ω0C2
gsεsat l
5Ibias ·RT·ω0
Qωm2
P0
(10)
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LEE et al.: CMOS QUADRATURE VCO WITH SUBHARMONIC AND INJECTION-LOCKED TECHNIQUES 847
TAB L E I
SUMMARIZED PERFORMANCES OF THE PROPOSED QVCO AND ITS COMPARISON WITH PREVIOUSLY PROPOSED VCOs
III. EXPERIMENTAL RESULTS
The proposed QVCO was implemented in the TSMC
0.18-μm 1P6M CMOS technology to verify the subharmonic
and injection-locked techniques. Fig. 11 shows the micro-
graph of the fabricated QVCO with a chip area of 1.4×
0.67 mm2. Measurements of the proposed circuit were per-
formed on a standard FR4 PCB. Aluminum wire bonds were
employed to assemble all pads. The output spectrum and phase
noise were measured using the Agilent PSA-E4440A and the
SSA-E5025A, respectively.
The measured frequency can be tuned between 2.17 and
2.52 GHz under the supply voltage of 1.05 V and tuning voltage
range of 0–1 V. The measured result was compared with the
postlayout simulation, as shown in Fig. 12. Moreover, the phase
noise at the 1-MHz offset frequency from the 2.17-GHz carrier
frequency (Fig. 13) was −126 dBc/Hz. The experimental result
was 0.7 dBc/Hz more than the simulation result. The slight
variations of the supply voltage, the carrier frequency, and the
phase noise were caused by the PVT variation. Furthermore,
the measured power imbalance and phase error were less than
0.8 dB and 6◦, respectively (Fig. 14).
IV. CONCLUSION
In this brief, a subharmonic injection-locked QVCO with a
cross-coupled structure and a current reuse topology has been
proposed to achieve a better FOM. The cross-coupled pair with
current reuse topology has provided a double negative resistor
to cancel the parasitic resistor of the LC tank. Compared to
the conventional QVCO with a parallel-resonator structure, the
proposed structure has reduced the current path from eight
to four and has shown the ability to save the half current.
Moreover, instead of a traditional transformer-feedback VCO,
the frequency-doubled mechanism has been adopted to save
the large area, and the injection-locked method has been used
to synthesize the quadrature outputs and to reduce the phase
noise. The analysis and measured results are close to theoret-
ical predictions. The performance comparison with published
QVCO results has been summarized in Table I. Although the
backgate QVCO [16], without transformers, has lower power
and a better FOM than our work, the proposed QVCO still has
a better tuning range and a lower supply voltage. Tuning range
and supply voltage have not been included in the description of
FOM. According to the experimental results, the proposed sub-
harmonic injection-locked QVCO is suitable for low-voltage
and low-power applications under a competitive FOM.
ACKNOWLEDGMENT
The authors would like to thank the Chip Implementation
Center of Taiwan for the technical support it has provided.
REFERENCES
[1] J. Crols and M. S. J. Steyaert, “A single-chip 900 MHz CMOS receiver
front-end with a high performance low-IF topology,” IEEE J. Solid-State
Circuits, vol. 30, no. 12, pp. 1483–1492, Dec. 1995.
[2] A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, “A 900 MHz
CMOS LC-Oscillator with quadrature outputs,” in Proc. IEEE Int. Solid-
State Circuits Conf., Feb. 1996, pp. 392–393.
[3] P. Andreani and X. Wang, “On the phase-noise and phase-error perfor-
mances of multiphase LC CMOS VCOs,” IEEE J. Solid-State Circuits,
vol. 39, no. 11, pp. 1883–1893, Nov. 2004.
[4] S. L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, and V. Boccuzzi,
“A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic
coupling,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1148–1154,
Jul. 2003.
[5] P. Tortori, D. Guermandi, E. Franchi, and A. Gnudi, “Quadrature VCO
based on direct second harmonic locking,” in Proc. ISCAS, May 2004,
pp. 169–172.
[6] S. B. Shin, H. C. Choi, and S. G. Lee, “Source-injection parallel coupled
LC-QVCO,” Electron. Lett., vol. 39, no. 14, pp. 1059–1060, Jul. 2003.
[7] S. Y. Lee and C. Y. Chen, “Analysis and design of a wide-tuning-range
VCO with quadrature outputs,” IEEE Trans. Circuits Syst. II, Exp. Briefs,
vol. 55, no. 12, pp. 1209–1213, Dec. 2008.
[8] S. Y. Lee, M. F. Huang, and C. J. Kuo, “Analysis and implementation of
a CMOS even harmonic mixer with current reuse for heterodyne/direct
conversion receivers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52,
no. 9, pp. 1741–1751, Sep. 2005.
[9] B. Razavi, “A study of injection locking and pulling in oscillator,” IEEE
J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004.
[10] S. Y. Lee and J. Y. Hsieh, “Analysis and implementation of a 0.9-V
voltage-controlled oscillator with low phase noise and low power dissi-
pation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 7, pp. 624–
627, Jul. 2008.
[11] M. Hershenson, S. S. Mohan, S. P. Boyd, and T. H. Lee, “Optimization
of inductor circuits via geometric programming,” in Proc. Des. Autom.
Conf., New Orleans, LA, Jun. 1999, pp. 994–998.
[12] M. Hershenson, A. Hajimiri, S. S. Mohan, S. P. Boyd, and T. H. Lee,
“Design and optimization of LC oscillator,” in Proc. IEEE ACM Int. Conf.
Comput. Aided Des., Nov. 1999, pp. 65–69.
[13] G. Huang and B. S. Kim, “Low phase noise self-switched biasing CMOS
LC quadrature VCO,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 2,
pp. 344–351, Feb. 2009.
[14] I. R. Chamas and S. Raman, “Analysis and design of a CMOS phase-
tunable injection-coupled LC quadrature VCO (PTIC-QVCO),” IEEE J.
Solid-State Circuits, vol. 44, no. 3, pp. 784–796, Mar. 2009.
[15] S. L. Jang, S. H. Huang, C. C. Liu, and M. H. Juang, “CMOS Colpitts
quadrature VCO using the body injection-locked coupling technique,”
IEEE Microw. Wireless Compon. Lett., vol. 19, no. 4, pp. 230–232,
Apr. 2009.
[16] J. P. Hong, S. J. Yun, N. J. Oh, and S. G. Lee, “A 2.2-mW backgate cou-
pled LC quadrature VCO with current reused structure,” IEEE Microw.
Wireless Compon. Lett., vol. 17, no. 4, pp. 298–300, Apr. 2007.
[17] X. Li, S. Shekhar, and D. J. Allstot, “Gm-boosted common-gate LNA
and differential Colpitts VCO/QVCO in 0.18-µm CMOS,” IEEE J. Solid-
State Circuits, vol. 40, no. 12, pp. 2609–2619, Dec. 2005.
Authorized licensed use limited to: National Cheng Kung Univ.. Downloaded on April 01,2020 at 05:45:40 UTC from IEEE Xplore. Restrictions apply.