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Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology
... The systematic offset of OP1 plays a significant role in BGR performance with respect to temperature [19,20]. Equation (6) shows that VOS is amplified using a ratio of due to the closed-loop nature of the BGR, and this amplification factor is so large that it might impact the TC of the output voltage. ...
... The systematic offset of OP1 plays a significant role in BGR performance with respect to temperature [19,20]. Equation (6) shows that VOS is amplified using a ratio of R 2 R P due to the closed-loop nature of the BGR, and this amplification factor is so large that it might impact the TC of the output voltage. ...
Reference voltage/current generation is essential to the Analog circuit design. There have been several ways to generate quality reference voltage using bandgap reference (BGR) and there are mainly two types: current mode and voltage mode. The current-mode bandgap reference (CBGR) is widely accepted in industry due to having an output voltage which is below 1 V. However, its drawbacks include a lack of proportional to absolute temperature (PTAT) current availability, a large silicon area, multiple operating points, and a large temperature coefficient (TC). In this paper, various operating points are explained in detail with diagrams. Similar to the conventional voltage mode bandgap reference (VBGR) circuits, modifications of the existing circuits with only two operating points have also been proposed. Moreover, the proposed BGR occupies a much smaller area due to eliminating the complimentary to absolute temperature (CTAT) current-generating resistor. A new self-biased opamp was introduced to operate from a 1.05 V supply, reducing systematic offset and TC of the BGR. The proposed solution has been implemented in 28 nm CMOS TSMC technology, and extraction simulations were performed to prove the robustness of the proposed circuit. The targeted mean BGR output is 500 mV, and across the industrial temperature range (−40 to 125 °C), the simulated TC is approximately 10.5 ppm/°C. The integrated output noise within the observable frequency band is 19.6 µV (rms). A 200-point Monte Carlo simulation displays a histogram with a 2.6 mV accuracy of 1.2% (±3-sigma). The proposed BGR circuit consumes 32.8 µW of power from a 1.05 V supply in a fast process and hot (125 °C) corner. It occupies a silicon area of 81 × 42 µm (including capacitors). This design can aim for use in biomedical and sensor applications.
... Multipliers constitute a significant portion of computer arithmetic units, leading to considerable energy and time consumption. Haq, Shams Ul, Erfan Abbasian, et.al [9] developed appeal of portable electronics, embedded systems, and other smart devices steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. ...
Multipliers are basic building blocks in various integrated circuits like microprocessors, micro controllers, and ALUs. The existing multipliers suffer from high power consumption and inefficient use of hardware resources. They often rely on traditional adder structures that are not tailored for specific operations, leading to suboptimal performance. Additionally, their fixed architectures limit adaptability and scalability in different applications. So, the proposed approach offers enhanced computational efficiency and reduced power consumption compared to conventional multiplier designs. By integrating multiplexer-dependent adders into the systolic array, the proposed method optimizes resource utilization and delivers improved performance for various arithmetic operations. This integration allows for dynamic selection of adder types based on the specific multiplication operation, significantly reducing power consumption and latency. By adapting the hardware resources to computational needs, the method achieves higher efficiency and flexibility, making it suitable for a wide range of applications in digital signal processing and data processing systems.
... 3-D schematic of MOSFET-like CNTFET[17]. ...
In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to the best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.
... Ternary logic is a form of MVL comprising three logic levels: '0′ (ground), '1′ (V DD /2), and '2′ (V DD ) [62,63,64]. The principal goal of ternary logic designers is to generate the logic level '1′, achieved through voltage division using series-connected transistors or utilizing two power supplies [65,66,67]. ...
As silicon field-effect transistors encounter increasing scaling challenges, digital system designers are shifting their attention towards multi-valued logic (MVL), specifically ternary logic. The graphene nanoribbon field-effect transistor (GNRFET) emerges as a compelling alternative among post-MOSFET technologies for the implementation of ternary logic. This paper delves into the computational intricacies of ternary logic, underscores the outstanding features of GNRFET technology, and introduces a novel GNRFET-based 1-trit ternary multiplier (TMUL) requiring only 26 transistors. The performance of the design is assessed using the Synopsis HSPICE simulator with a 32-nm GNRFET model file operating at VDD = 0.9 V. The proposed TMUL surpasses existing designs due to its efficient paths with a minimal number of transistors for each output transition, a singular power supply voltage, and an extended voltage division scheme. In comparison to other contemporary TMUL designs, the proposed design exhibits a notable enhancement, showcasing a 21.42 % reduction in delay, a 33.11 % decrease in power-delay-product (PDP), and a 58.17 % decrease in energy-delay-product (EDP). Additionally, the design is subjected to thorough testing under diverse conditions including process, voltage, temperature (PVT) fluctuations, and load variations, validating its reliability and robustness.
Natural language processing (NLP) based on deep learning provides a positive performance for generative dialogue system, and the transformer model is a new boost in NLP after the advent of word vectors. In this paper, a Chinese generative dialogue system based on transformer is designed, which only uses a multi-layer transformer decoder to build the system and uses the design of an incomplete mask to realize one-way language generation. That is, questions can perceive context information in both directions, while reply sentences can only output one-way autoregressive. The above system improvements make the one-way generation of dialogue tasks more logical and reasonable, and the performance is better than the traditional dialogue system scheme. In consideration of the long-distance information weakness of absolute position coding, we put forward the improvement of relative position coding in theory, and verify it in subsequent experiments. In the transformer module, the calculation formula of self-attention is modified, and the relative position information is added to replace the absolute position coding of the position embedding layer. The performance of the modified model in BLEU, embedding average, grammatical and semantic coherence is ideal, to enhance long-distance attention.
A fastIMM-extended Viterbi (fastIMM-EV) algorithm-based maneuvering target tracking method is proposed for the real-time tracking of ground maneuvering targets by a ballistic acoustic array, which firstly adopts the extended Viterbi interactive multi-model (IMM-EV) algorithm to select the best model from a given model set to match the maneuvering target motion pattern; secondly, the α–β filter and α–β–γ filter are used to replace the 2D or 3D Kalman filter in the traditional IMM algorithm, respectively, to form the fastIMM-EV algorithm, which nearly improves the algorithm efficiency, and at the same time, for the switching problem of different fastIMM-EV modules, a target maneuver recognition parameter is defined as the switching factor of the fastIMM-EV module, so that fastIMM-EV to switch the module when the target maneuver occurs; finally, the MATLAB simulation test results verify the practicality and high efficiency of the algorithm in this paper compared with different IMM target tracking methods.
Target threat assessment is a critical aspect of information warfare and can offer valuable auxiliary support to combat command decision-making. Aiming to address the shortcomings of three decision-making methods in air combat target assessment, such as the inability to effectively handle uncertain situation information and quantitatively rank the decision-making targets according to their importance, a dynamic intuitionistic fuzzy decision model based on the improved GRA-TOPSIS method and three-way decisions is proposed. First, the target attribute weight is obtained by cosine intuitionistic fuzzy entropy algorithm; then, a novel intuitionistic fuzzy distance measure is introduced, and grey incidence analysis and TOPSIS are used to build the conditional probability for three-way decisions that fully utilize the existing information and reflect the consistency of dynamic change trend; finally, the comprehensive loss function matrix is constructed and the threat classification results are obtained using the decision rules. The example analysis shows that the proposed method can not only effectively handle complex battlefield situations and dynamic uncertain information, but it can also classify targets, improving the effectiveness and rationality of decision-making and providing a reference basis for scientific command decision-making.
Contemporary system-on-chip-based applications are battery-powered. To increase the operation time, they need various low-power/energy circuits. Carbon nanotube field-effect transistor (CNTFET) is a potential alternative to complementary metal-oxide-semiconductor for power/energy-efficient circuits implementation due to its high performance. Another way to reduce power/energy consumption in a circuit is to use multiple-valued logic, especially ternary logic, which has three logical states. This paper presents a novel 1-trit ternary multiplier circuit with 23 transistors based on only unary operators of the ternary logic system and the dual-supply voltages technique. The proposed design does not use the ternary decoder/encoder, logic gates, cascading transmission gates, and ternary multiplexer to reduce the transistors count, delay, power, and energy. The Stanford CNTFET model in the 32-nm technology node is used to simulate the proposed design. The delay, power, and delay-power-product (PDP) of the proposed design at 0.9V are 0.026ns, 0.139μW, and 3.614aJ, respectively. It offers improvements between 50% and 61.19% in delay and between 52.72% and 59.75% in PDP compared to previously published multiplier circuits, which are based on the dual-supply voltages and use 23 transistors. These improvements make the proposed design a good candidate for the design of the next generation of multiplier circuits in arithmetic blocks.
Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels.
Nonuniform brightness distribution of collimator reticle images leads to the recognition difficulty of reticle grids and coordinate scales on images and affects the digitalization of reticle coordinate system. The article proposes an image quality improvement algorithm that operates on L channel of LAB color space to perform brightness correction. It designs four typical image modules depending on representative brightness features. Corresponding brightness correction models for all typical image modules are constructed by designing the new correction functions based on nonlinear gamma transform. A concept of brightness similarity is defined for automatic matching between typical image modules and the image region to be processed. On this basis, the algorithm can automatically adjust brightness correction mode to ensure the brightness of each pixel tends to be uniform, which is reflected in a visible improvement in the color distortion of the image. The algorithm can effectively reduce the complexity of model processing and adaptively adjust brightness correction intensity according to the pixel brightness value. It enables more accurate corrections with good results.
Koopman operators are of infinite dimension and capture the characteristics of nonlinear dynamics in a lifted global linear manner. The finite data-driven approximation of Koopman operators results in a class of linear predictors, useful for formulating linear model predictive control (MPC) of nonlinear dynamical systems with reduced computational complexity. However, the robustness of the closed-loop Koopman MPC under modeling approximation errors and possible exogenous disturbances is still a crucial issue to be resolved. Aiming at the above problem, this paper presents a robust tube-based MPC solution with Koopman operators, i.e., r-KMPC, for nonlinear discrete-time dynamical systems with additive disturbances. The proposed controller is composed of a nominal MPC using a lifted Koopman model and an off-line nonlinear feedback policy. The proposed approach does not assume the convergence of the approximated Koopman operator, which allows using a Koopman model with a limited order for controller design. Fundamental properties, e.g., stabilizability, observability, of the Koopman model are derived under standard assumptions with which, the closed-loop robustness and nominal point-wise convergence are proven. Simulated examples are illustrated to verify the effectiveness of the proposed approach.
In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias minimised threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed a 0.9 mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64 ppm/⁰C. The proposed circuit consumed 5.04 µW of power from a 0.45 V power supply voltage. A prototype was implemented in 65 nm CMOS technology occupying a 2888 µm² silicon area, with the nominal value of the reference at 261 mV.
This paper presents a ternary half adder and a 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed using pass transistor logic and dynamic logic. Ternary logic uses less connections than binary logic, and less voltage changes are required for the same amount of data transmission. Carbon nanotube transistors have advantages over MOSFETs, such as the same mobility for electrons and holes, the ability to adjust the threshold voltage by changing the nanotube diameter, and less leakage power. The proposed half adder has lower power consumption, delay, and fewer transistors compared to recent ternary half adders that use similar design methods. The proposed 1-trit multiplier also has a lower delay than other designs. Moreover, these advantages are achieved over a wide supply voltage range, operating temperatures, and output loads. The design is also more robust to process variations than the nearest design in terms of PDP.
From the dawn of the computer age, man has mass produced binary components for computers, due to which ternary or higher radix computers are not yet commercially used. It has been proved that ternary logic can be more efficient than binary logic and there are many devices in development that operate on more than two internal states. Therefore an efficient method to produce multi-valued logic on the basis of binary input provided is needed. In this article, an effective, simple, flexible, and low power consumption implementation has been proposed that can convert any binary number to a number of chosen radix. The proposed design is implemented in 32 nm TSMC CMOS. The proposed design is then evaluated in power/delay space and its performances are compared with the latest state of art designs. The proposed circuit exhibits power saving up to 92% over previous models.
Full adder cell is an important module in arithmetic and processing systems whose performance has a great impact on performance of the whole system. By continuous scaling of the MOS transistors, some challenges and problems appear such as high leakage dissipation for which emerging technologies have been studied as a solution. Carbon nanotube field effect transistor (CNFET) is one of the most potential alternatives for the traditional MOSFET. The threshold voltage of a CNFET can be adjusted by tuning its CNT diameter. This property makes them to be appropriate for designing voltage mode multi-valued logic circuits. In this paper, a novel multiplexer-based ternary full adder cell using CNFET is presented. The proposed circuit is simulated and compared with the state-of-the-art designs using Synopsys HSPICE simulator. Simulations are done to investigate the effect of process (P), voltage (V) and temperature (T) variations on the circuit. The results show that the proposed design reduces the energy consumption by about 54% than the best reported design, while is robust against PVT variations.
A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness.
Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, Multi-Valued Logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this paper proposes new ternary circuits aiming to lower the power delay product (PDP) to save battery consumption. The proposed designs include new ternary gates [Standard Ternary Inverter (STI), Ternary NAND (TNAND) and combinational circuits Ternary Decoder (TDecoder), Ternary Half-Adder (THA), and Ternary Multiplier (TMUL)] using Carbon Nano-Tube Field Effect Transistors (CNFET). The paper employs the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate and applying the dual supply voltages (Vdd, and Vdd/2). The five proposed designs are compared to the latest fifteen ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies. One hundred eighty simulations are performed to prove the efficiency of the proposed designs. The results show the advantage of the proposed designs in reduction over 43% in terms of transistors’ count for the ternary decoder and over 88%, 99%, 98%, 86%, and 78% in energy consumption (PDP) for the STI, TNAND, TDecoder, THA, and TMUL respectively.
The performance of a Schottky barrier carbon nanotube field effect transistor (SB-CNTFET) has been analyzed by means of a compact model. We present a study of the physical and geometrical parameters and their effects on the static and dynamic performance of the SB-CNTFET. For the static regime, we determine the variations in the current–voltage characteristics for three values of the potential barrier and the influence of the barrier on the on-state current. Also, we report the effect of the oxide thickness on the static performance. The relationship between the current–voltage characteristics and the nanotube diameter for different values of drain–source voltage is investigated. For dynamic systems, we study the effect of the gate–source voltage, the chirality and the CNT diameter on the transition frequency. It has been observed that the performance of the SB-CNTFET can be significantly controlled by changing some physical and geometrical parameters of the device.
This study explores the suitability of dynamic logic style in ternary logic. It presents high-performance dynamic ternary half and full adders, which are essential components in computer arithmetic. The complete transformation from a static ternary design into its dynamic form is comprehensively investigated. The proposed dynamic strategy does not suffer from any race or charge sharing problems. These dynamic logic problems are dealt with in this study. In addition, the number of successive pass-transistors is reduced by a design technique which shortens the critical path of ternary circuits. The new adder cells are simulated by using Synopsys HSPICE and 32 nm carbon nanotube field-effect transistor technology. Simulation results demonstrate the superiority of dynamic ternary circuits. The proposed dynamic ternary half adder operates 21% faster, consumes 23% less power, and has even 14 fewer transistors than its static counterpart.
Due to their nanoscale scattering cross section, single-walled car-
bon nanotubes (SWCNTs) have never been reported for crystallite
size or similar characteristics. Here, we characterize the average
structure thermal domain size of SWCNTs. This characteristic size
reflects the average mean free path of low-momentum phonon
scattering. The characterization itself involves measuring the ther-
mal reffusivity of SWCNT bundles in the axial direction down to 77
K and determining the residual value at the 0 K limit. This residual
value reflects the sole structure-phonon scattering due to vanishing
Umklapp scattering. We obtain the average structure thermal
domain sizes of two SWCNT bundles, which are 46.0 and 61.9 nm.
Since there is no other characteristic size information available to
compare for SWCNTs, we compare the structure thermal domain
size of other micro-/nanoscale materials with their crystallite size
by X-ray diffraction to interpret our results.
In this paper, we study the architectures of space-air-ground integration network (SAGIN) proposed by domestic scientific research institutes, and put forward an collaborative federal learning architecture suitable for SAGIN to solve the problems of insecurity and low timeliness caused by traffic backhaul. An anomaly traffic detection method is proposed based on the requirements and characteristics of SAGIN. The problem that it is difficult to manually label and extract features in the traffic of SAGIN is solved through the improvement of deep learning algorithm. The challenge of lack of professionals labeling training set is solved by studying the method of semi supervision. The problem of artificial feature engineering is solved by studying the end-to-end anomaly traffic detection algorithm. Finally, we design a simulation environment for the anomaly traffic detection in SAGIN, and verify the feasibility and advanced nature of the proposed methods.
Passenger counting is crucial for many applications such as vehicle scheduling and traffic capacity assessment. However, most of the existing solutions are either high-cost, privacy invasive or not suitable for passengers the vehicle scenarios. In this work, we propose the
Pa
-
Count
, an effective real-time
Pa
ssenger
Count
ing system deployed inside the vehicle via using Wi-Fi
CSI
(Channel State Information). Specifically, in Pa-Count, we design a set of combined filters to eliminate environmental interference and enhance CSI quality. In so doing, we can identify the fluctuation of weak CSI caused by passengers' subtle movement, i.e., the fidgeting, and then obtain the distribution of fidgeting period and silent period. Following that, we describe the subtle movements of passengers via power law with exponential cutoff distribution and establish a counting model based on the queuing theory. A mathematical inference method with a priori probability is devised to calculate the number of real-time passengers through CSI. We evaluate the performance of the Pa-Count by conducting a set of experiments in real-world vehicle scenarios (including private car and subway). Experimental results show that Pa-Count can achieve robust performance with an average accuracy of over 92
$\%$
.
The log-sum function as a penalty has always been drawing widespread attention in the field of sparse problems. However, it brings a non-convex, non-smooth and non-Lipschitz optimization problem that is difficult to tackle. To overcome the problem, an iterative threshold algorithm for the sparse optimization problems with log-sum function is proposed in this paper. For brevity, the sparse optimization problems with log-sum function are named log-sum regularization. Firstly, by introducing an intermediate function to construct another new function, a property theorem about solution for log-sum regularization is established. Secondly, based on the above theorem, the optimal setting rules of the compromising parameters are elaborated, and an iterative log-sum threshold algorithm is proposed. Thirdly, under the situation that the compromising parameters of log-sum regularization are relatively small, it can be proven that the proposed algorithm converges to a local minimizer of log-sum regularization. Finally, a series of simulations are implemented to examine performance of the proposed algorithm, and the results exhibit that the proposed algorithm outperforms the state-of-the-art algorithms.
Internet-of-things-based embedded systems depend on batteries as an energy resource, and thus, require energy-efficient circuits for prolonged operation. To achieve energy-efficient designs, multiple-valued logic circuits and carbon nanotube field-effect transistors (CNTFETs) are used instead of binary logic circuits and complementary metal–oxide–semiconductor, respectively. This paper presents a novel high-performance and energy-efficient ternary multiplier (TMUL) circuit in CNTFET technology. The proposed TMUL is designed by modifying its truth table by including two ternary unary operator circuits, negative ternary inverter and positive ternary inverter, and finding relations between these operators and outputs to dump ternary decoders/encoders and basic logic gates. Moreover, two power supplies, VDD and VDD/2, are employed to eliminate the direct path from high to low voltage levels in each possible combination of inputs. Using ternary unary operator circuits and applying two power supply components reduce the number of transistors used, delay, and power/energy. The delay, power, and power-delay-product (PDP) of the proposed design at 0.9 V supply voltage are 0.048 ns, 0.172 µW, and 0.008 pJ, respectively. The proposed TMUL offers an improvement between 8.70 and 71% in transistors count, between 11.11 and 81.54% in delay, between 6.52 and 72.74% in power consumption, and between 27.27 and 94.07% in PDP compared to the latest TMUL circuits.
According to the nonlinear response characteristics of magnetron, this article proves that a 2.45 GHz band continuous-wave magnetron can perform as a modulator in communication system. The intermediate frequency (IF) signal coupled to the power supply of magnetron, as the ripple of anode voltage, can be modulated to a nearby band centered on the resonant frequency of magnetron. We deduced the output expression of free oscillating magnetron under the influence of anode voltage ripple. And electromagnetic simulation was accomplished to testify the validity of the theoretical derivation. Moreover, we designed the circuit to couple signal with frequencies of 2, 3, and
$4$
MHz to the anode voltage. The output spectrum of magnetron changed as the frequencies were tuned, to satisfy the frequency requirements for modulating. Finally, a simultaneous information and power transfer system based on a magnetron combined with the power supply coupling circuit was developed and tested. This system achieved the modulation, amplification, transmission, and demodulation of low-frequency signal which is equivalent to human voice. This research reveals that the proposed techniques have great potential for future simultaneous wireless information and power transfer (SWIPT) system because they provide higher power at lower cost.
Dynamic Searchable Symmetric Encryption (DSSE) is a practical cryptographic primitive that assists servers to provide search and update functionalities in the ciphertext domain. Recent work on DSSE schemes has focused on the direction of forward-privacy, requiring that newly added files cannot be linked to previously query results. However, due to the complexity of forward-privacy updates, existing schemes can only address an honest-but-curious server. It is difficult to verify updated results while preserving forward-privacy. In this paper, we explore how blockchain techniques can help us achieve a verifiable and forward-privacy DSSE scheme. Our scheme resorts to the emerging smart contract as a trusted platform to store digests for public result verification, and carefully crafts dynamic query protocols to enable encrypted search with forward-privacy. In our design, indexes are collocated with encrypted files and stored at storage-servers, which makes the blockchain light-weighted and search operations more efficient. Moreover, we propose a hybrid index design to support efficient files deletion. By using our blockchain-assisted primitive, the property collision between dynamic result verification and forward-privacy can be solved. We formally analyze the security strengths and provide the prototype implementation on Ethereum. Experiment results demonstrate the feasibility and usability of our blockchain-assisted DSSE scheme.
The rapid development of modern communication systems propels the demand of high performance and miniaturization of RF/microwave components. Power dividers and filters are indispensable circuit components in amplifiers and antenna feed-networks which occupy large footprint of circuit broads, particularly at low frequency. The purpose of this study is to initiate a new type of planar transmission line with unique dual signal-path characteristics and ultimately achieve circuit miniaturization. In this paper, a novel technique of consolidating microstrip lines (MLs) and coplanar waveguide (CPW) lines on a single dielectric substrate, designated as the composite microstrip/CPW line (CM/CPW line), is proposed. With reference to the average line length of ML and CPW, it warrants a physical length reduction of 48.3% and further achieves a reduction of 80.8% after zigzagging CM/CPW line. The proof-of-concept design example of a two-way Wilkinson power divider (WPD) has demonstrated the effectiveness of the miniaturization technique. The simulation, in combination with the experimental results, validates that a size reduction factor of 86.9% when compared to conventional one has been achieved while maintaining a fractional bandwidth of 57.7% for the WPD.
This paper focuses mainly on the effect of various channel parameters like chirality, diameter of CNT, high-k dielectric materials and oxide layer thickness of DG-CNTFET on the threshold voltage at different temperature range of 225K–400K using nanoHUB simulation tools. The minor reductions (less than 5%) in threshold voltage of DG-CNTFET with respect to variable temperature increasing from 225K to 400K are observed. The results show that the threshold voltage increases with the reduction in carbon nanotube diameter of DG-CNTFET which affects the thermal conductivity of device as the van der Waals interaction between carbon-carbon bonds gets affected in DG-CNTFET. It was also investigated that decrease in quantum capacitance of DG-CNTFET improves the propagation delay of device. Using higher k-dielectric materials in DG-CNTFET enables faster switching speeds and lowers the power dissipation. Finally, based on results a conclusion has been drawn that best performance was recorded at lower value of temperature for threshold voltage.
In this study, a finite-time consensus tracking problem is investigated for a group of autonomous underwater vehicles (AUVs) with heterogeneous uncertain dynamics. We firstly propose a two-layer distributed control strategy, which consists of an upper-layer distributed observer and a lower-layer controller, without using any global information. Based on Hölder’s inequality and the theory of finite-time stability, a distributed finite-time observer is developed for each follower to estimate the position information of a leader (i.e., an exosystem). Based on the sliding mode control method, a consensus tracking control scheme is designed for each AUV, by which all follower AUVs can track the leader in finite time. Secondly, when the parameters in the AUV dynamics are uncertain, a parameter-adaptive sliding mode control algorithm is introduced to improve the control performance. Finally, simulation results are presented to demonstrate the effectiveness of the proposed control algorithms.
Ternary logic uses fewer interconnects than binary logic, and smaller voltage swings are required for the same information transfer. Carbon Nanotube transistors (CNFETs) have many advantages over Metal Oxide Semiconductor transistors (MOSFETs), such as equal mobility of electrons and holes, the ability to adjust the threshold voltage by changing the nanotube's diameter, and lower leakage power. In this paper, a dynamic ternary full adder is presented using CNFETs. Subsequently, a 5-trit ripple carry adder is designed based on the proposed dynamic ternary full adder and buffer circuits. The proposed hybrid circuits are designed using clocked dynamic logic. Synopsys HSPICE simulator and Stanford's 32-nanometer CNFET model are used to simulate the circuits. The performance of the approach is evaluated under different supply voltages, loads, and temperatures. It is shown that the proposed full adder has lower power consumption, transistor count, PDP, and EDP compared with previously presented ternary adders. Furthermore, the proposed circuit is more robust to process variations.
This brief proposes a sub-1V, voltage mode CMOS bandgap reference circuit. Conventionally, sub-1V references are obtained by converting PTAT and CTAT voltages to currents and summing them in the current domain. Such techniques have multiple operating points and cannot natively support applications that require PTAT currents in addition to a bandgap voltage. This brief presents a voltage mode reference circuit, which adds a PTAT voltage with a scaled version of a CTAT voltage all within the sub-1V domain. Compared to current mode bandgaps, summing in voltage domain enables reduction of one CTAT current mirror stage and a significant reduction in PTAT current mirror ratio resulting in a reduced number of error sources. In addition, this circuit also natively supports applications that require PTAT current. A novel, high-accuracy self-biasing technique has been adopted to minimize the systematic offset induced temperature coefficient. A prototype designed in 45nm TSMC CMOS technology for a nominal voltage of 500mV demonstrates 24.4ppm/°C temperature coefficient from −40°C to 125°C, 0.15% line regulation, and draws
$7.2\mu \text{A}$
from a 1.05V supply.
A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m ² of silicon area.
Silicon based technology encounters scaling parameters that prohibit the advancement of transistor technology. Graphene nanoribbons (GNR) and carbon nanotubes (CNT) are often considered the predominating devices to replace silicon technology. Carbon nanotube field effect transistors (CNTFETs) are considered the most promising devices because of their most interesting properties such as high current carrying ability (∼ 1010 A/cm²), excellent carrier mobility, scalability, high reliability for elevated temperature operation, and negligible leakage current. In this paper, a comparative analysis of CNTFET and graphene nanoribbon field effect transistors (GNRFET) is presented. The results of simulations are presented, and comparisons of devices are done based on different parameters listed as ION/IOFF current ratio, trans-conductance, and inverse subthreshold slope using NanoTCAD ViDES. After simulation, it is shown that CNTFET offers better results for ION/IOFF on the order of 10⁶, subthreshold swing (SS) as 74.4 mV/dec, and transconductance as 7.6 μS. Further the effect of oxide thickness and dielectric constant has been studied for both FET devices. At the end, it is concluded that CNTFET offers better simulation result than that of GNRFET.
Often Bandgap Reference performance limits the SNR of the bio-medical transceiver, hence sensitivity. In this paper, conventional beta multiplier has been explored to design a new low voltage pure CMOS bandgap architecture, which avoids op-amps and resistors, hence very less mismatch and area. Line sensitivity has been improved by adding an extra gain stage in the circuit. The circuit implementation of the proposed technique was done in 65 nm TSMC CMOS technology to generate 460 mV output voltage. The minimum operating voltage of the circuit is 650 mV. Post-layout simulation results are as follows, 31 ppm/\(^{\circ }\)C temperature coefficient against temperature variation of −40\(^{\circ }\) to 125 \(^{\circ }\)C, 0.5% regulation against supply variation of 0.65−1 V and 0.42% PVT variation. Circuit draws 2.3 A current from 650 mV from power-supply. The proposed band gap reference occupies 0.00144 mm\(^{2}\) silicon area.
This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87dB, 250MHz unity gain bandwidth amplifier has been developed in 65nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126μA from a 1.2V supply and occupies the 2184μm2 area.
In existing CNFET-based design methodologies that are used to implement ternary logic circuits, ternary signals are first converted to binary signals, which are then passed through binary gates and an encoder to get the final ternary output. In a ternary circuit, encoder is used to convert intermediate binary signals to final ternary outputs. This paper presents improved encoder designs which are used in implementation of ternary logic circuits. A detailed analysis is carried out on encoders to understand the effect of using CNFETs with CNTs of different diameter on the overall propagation delay and power consumption of the encoder. Based on this analysis, algorithms, which choose appropriate encoders for different output stages of a ternary circuit while optimizing different design parameters like power consumption, propagation delay or power-delay product, are presented. These algorithms are used to map appropriate encoders for different outputs of a ternary adder resulting in adder designs which are optimized for delay, power or power-delay product. Simulation results indicate that the ternary adder designs, which use encoder mapping obtained from proposed algorithms, result in 54 $\times$ 82% reduction in power consumption, 0 $\times$ 75% in propagation delay and 54 $\times$ 94% in power-delay product when compared to different existing ripple carry-based ternary adders.
This paper presents the design and measurements of a 32-Gb/s differential-input differential-output transimpedance amplifier (TIA) employed in dual polarization integrated coherent receivers for 100-Gb Ethernet. A circuit technique is shown that uses a replica TIA to stabilize the operating point of the two shunt-feedback input stages as well as to cancel the dc part of the two complementary input currents and balances their offset. The TIA can be operated in two modes, an automatic gain control mode to retain a good total harmonic distortion (THD) over a wide dynamic range and a manual gain control mode. Electrical as well as optical-electrical characterization of the TIA are presented. It achieves a maximum differential transimpedance of 74 dBΩ, 33 GHz of 3-dB bandwidth, 12.2 pA/√Hz of average input-referred noise current density with the photodiode, 900 mV
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of maximum differential output swing, less than 1% of THD for 600 mV
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differential output swing, and 500 μA
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differential input current. The linearity of the TIA is furthermore demonstrated with PAM4 measurements at 25 Gbaud. The dual TIA chip is fabricated in a 0.13-μm SiGe:C BiCMOS technology, dissipates 436 mW of power and occupies 2 mm
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of area.
This brief presents a multiternary digit (trit) multiplier design in carbon-nanotube field-effect transistor (CNTFET) technology using unary operators of multivalued logic. The proposed structure is based on the classical Wallace multiplier and includes a novel ternary multiplexer design requiring only a small number of CNTFETs. Two ternary full-adder configurations are also proposed based on an examination of the multiplier structure. In addition, the design includes a new single-trit multiplier which requires 67% less CNTFETs compared to a recent design. HSPICE simulations reveal low power-delay product for the proposed designs for different choices of drive strength. Furthermore, the designs are comparable to prior works with respect to noise margin.
In this paper we present an exhaustive description of the basic types of
CNTFETs. In particular we review two models, already proposed by us, which
allow an easy implementation in circuit simulators, both in analog and in
digital applications.