New multilevel inverter topology with reduced number of switches using advanced modulation strategies

Abstract

This paper presents a new class of three phase seven level inverter based on a multilevel DC link (MLDCL) and a bridge inverter to reduce the number of switches. There are 3 types of multilevel inverters named as diode clamped multilevel inverter, flying capacitor multilevel inverter and cascaded multilevel inverter. Compared to diode clamped & flying capacitor type multilevel inverters cascaded H-bridge multilevel inverter requires least no. of components to achieve same no of voltage levels and optimized circuit layout is possible because each level have same structure and there is no extra clamping diodes or capacitors. However as the number of voltage levels m grows the number of active switches increases according to 2×(m-1) for the cascaded H-bridge multilevel inverters. Compared with the existing type of cascaded H-bridge multilevel inverter, the proposed MLDCL inverters can significantly reduce the switch count as well as the number of gate drivers as the number of voltage levels increases. For a given number of voltage levels, the required number of active switches is 2 (m-1) for the existing multilevel inverters, but it is m+3 for the MLDCL inverters. The output of proposed MLDCL is synthesized as the staircase wave, whose characteristics are nearer to a desired sinusoidal output. The proposed MLDCL inverter topologies can have enhanced performance by implementing the pulse width modulation (PWM) techniques. This paper also presents the most relevant control and modulation methods by a new reference/carrier based PWM scheme for MLDCL inverter and comparing the performance of the proposed scheme with that of the existing cascaded H-bridge multilevel inverter. Finally, the simulation results are included to verify the effectiveness of the both topologies in multilevel inverter configuration and validate the proposed theory. A hardware set up was developed for a singlephase 7-level D.C. Link inverter topology using constant pulses.

Full text

2013 International Conference on Power, Energy and Control (ICPEC)
978-1-4673-6030-2/13/$31.00 ©2013 IEEE
693
New Multilevel Inverter Topology with reduced number of
Switches using Advanced Modulation Strategies
S. Nagaraja Rao D.V. Ashok Kumar Ch. Sai Babu
Dept. of EEE, RGMCET, Nandyal, Dept.of EEE, SDIT, Nandyal, Dept. of EEE, JNTUK, Kakinada
nagarajraomtech@gmail.com principal.sdit@gmail.com chs_eee@yahoo.co.in
Abstract—This paper presents a new class of three phase seven
level inverter based on a multilevel DC link (MLDCL) and a
bridge inverter to reduce the number of switches. There are 3
types of multilevel inverters named as diode clamped multilevel
inverter, flying capacitor multilevel inverter and cascaded
multilevel inverter. Compared to diode clamped & flying
capacitor type multilevel inverters cascaded H-bridge multilevel
inverter requires least no. of components to achieve same no of
voltage levels and optimized circuit layout is possible because
each level have same structure and there is no extra clamping
diodes or capacitors. However as the number of voltage levels m
grows the number of active switches increases according to 2×(m-
1) for the cascaded H-bridge multilevel inverters. Compared with
the existing type of cascaded H-bridge multilevel inverter, the
proposed MLDCL inverters can significantly reduce the switch
count as well as the number of gate drivers as the number of
voltage levels increases. For a given number of voltage levels, the
required number of active switches is 2 (m-1) for the existing
multilevel inverters, but it is m+3 for the MLDCL inverters. The
output of proposed MLDCL is synthesized as the staircase wave,
whose characteristics are nearer to a desired sinusoidal output.
The proposed MLDCL inverter topologies can have enhanced
performance by implementing the pulse width modulation
(PWM) techniques. This paper also presents the most relevant
control and modulation methods by a new reference/carrier
based PWM scheme for MLDCL inverter and comparing the
performance of the proposed scheme with that of the existing
cascaded H-bridge multilevel inverter. Finally, the simulation
results are included to verify the effectiveness of the both
topologies in multilevel inverter configuration and validate the
proposed theory. A hardware set up was developed for a single-
phase 7-level D.C.Link inverter topology using constant pulses.
Keywords-Cascaded H - bridge, multilevel dc link inverter,
Pulse width modulation, Total Harmonic Distortion.
I. INTRODUCTION
The voltage source inverters produce an output voltage or
current with levels either 0 or ±Vdc. They are known as the
two-level inverter. To produce a quality output voltage or a
current wave form with less amount of ripple content, they
require high switching frequency. In high- power and high
voltage applications these two level inverters, however, have
some limitations in operating at high frequency mainly due to
switching losses and constraints of device ratings. These
limitations can be overcome using multilevel inverters.
There are 3 types of multilevel inverters named as diode
clamped multilevel inverter, flying capacitor multilevel
inverter and cascaded multilevel inverter. These three types of
multilevel inverters requires more no. of components such as
switches, clamping diodes and capacitors. As the number of
voltage levels m grows the number of active switches
increases according to 2×(m-1) for the cascaded H-bridge
multilevel inverters. Multilevel inversion is a power
conversion strategy in which the output voltage is obtained in
steps thus bringing the output closer to a sine wave and
reduces the total harmonic distortion (THD).
This paper presents a 3–Ф seven level cascaded H-bridge
multilevel inverter based on an MLDCL and a bridge inverter.
Compared with the existing cascaded multilevel inverters, the
proposed MLDCL inverter topologies can have enhanced
performance by implementing the pulse width modulation
(PWM) techniques. This paper also presents the most relevant
control and modulation methods by a new reference/carrier
based PWM scheme for MLDCL inverter and comparing the
performance of the proposed scheme with that of the existing
cascaded H-bridge multilevel inverter. The proposed MLDCL
inverter can significantly reduce the switch count as well as
the number of gate drivers as the number of voltage levels
increases. For a given number of voltage levels m, the
cascaded MLDCL inverter requires m+3 active switches,
roughly half the number of switches.
II. CASCADED H-BRIDGE INVERTER
The cascade H-bridge inverter is a cascade of H-bridges, or
H-bridges in a series configuration. A single H-bridge inverter
is shown in fig (1) and three phase cascaded H-bridge inverter
for seven-level inverter is shown in fig (2). Fig (1) and fig (2)
shows the basic power circuit of single H-bridge inverter and
the cascade of H-bridge inverter for seven-level inverter
respectively. An N level Cascaded H bridge inverter consists
of series connected (N-1)/2 number of cells in each phase.
Each cell consists of single phase H bridge inverter with
separate dc source. There are four active devices in each cell
and can produce three levels 0, Vdc/2 and –Vdc/2. Higher
voltage levels can be obtained by connecting these cell in
cascade and the phase voltage van is the sum of voltages of
individual cells, van = v1 + v2 + v3 + :::: + vN.

2013 International Conference on Power, Energy and Control (ICPEC)
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Fig.1 Configuration of single-phase H-bridge inverter
Table 1. Load voltage with corresponding conducting switches
Fig. 2 Configuration of three-phase Cascaded Seven Level H-Bridge Inverter
Fig. 3 output wave form of single phase 7 level cascaded inverter
Table .2 Switching sequence for 1–Ф 7 level cascaded inverter
III. MULTILEVEL DC LINK INVERTER TOPOLOGY
The proposed 3–Ф seven-level MLDCL inverter
involves various steps of operation. The configuration of the
proposed inverter is given in fig.4. Compared with the existing
multi level inverters, the new MLDCL inverters can
significantly reduce the switch count as well as the no. of gate
drivers as the no. of voltage levels increases. For a given no.
of voltage levels m, the new inverter requires m+3 active
switches, roughly half of the no. of switches, clamping diodes,
and voltage-splitting capacitors in the diode clamped
configuration or clamping capacitors in the flying capacitor
configuration. Simulation results are included to verify the
operating principle of the proposed MLDCL inverters.
Fig. 4 Configuration of three-phase Multilevel DC Link Inverter
Table .3 Switching sequence for single phase 7 level MLDCL inverter
Comparison of the Proposed MLDCL Inverters and the
Existing Counterparts:
Active Switches Output Voltage(Vab)
S1,S2 +Vdc
S3,S4 -Vdc
S1,S4 or S2,S3 0
Output
voltage
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
0Vdc 1 0 1 0 1 0 1 0 1 0 1 0
Vdc 1 0 0 1 0 0 1 1 0 0 1 1
2Vdc 1 0 0 1 0 0 1 1 1 0 0 1
3Vdc 1 0 0 1 1 0 0 1 1 0 0 1
-Vdc 0 1 1 0 1 1 0 0 1 1 0 0
-2Vdc 0 1 1 0 0 1 1 0 1 1 0 0
-3Vdc 0 1 1 0 0 1 1 0 0 1 1 0
Output
voltage
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
0Vdc 1 0 1 0 1 0 1 0 1 0
Vdc 1 0 0 1 0 0 1 1 0 0
2Vdc 1 0 0 1 0 0 1 1 1 0
3Vdc 1 0 0 1 1 0 0 1 1 0
-Vdc 0 1 1 0 1 1 0 0 1 1
-2Vdc 0 1 1 0 0 1 1 0 1 1
-3Vdc 0 1 1 0 0 1 1 0 0 1

2013 International Conference on Power, Energy and Control (ICPEC)
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Fig.5 Comparison of MLDCL and cascaded inverters
Fig. 5 shows the comparison of the proposed
MLDCL inverter and cascaded inverters based on required
number of switches and number of levels. From this
comparison it is clear that as the number of voltage levels, m,
grows, the number of active switches increases according to
m+3 for the MLDCL inverter, compared to 2(m-1) for the
cascaded H-bridge multilevel inverters.
IV.
M
ODULATION
STRATEGIES
A number of modulation strategies are used in multilevel
power conversion applications. They can generally be
classified into three categories:
• fundamental Frequency switching strategies
• Space Vector PWM strategies
• Carrier based PWM strategies
Of all the PWM methods for cascaded multilevel inverter,
carrier based PWM methods and space vector methods are
often used but when the number of output level is more than
five, the space vector method will be very complicated with
the increase of switching states. So the carrier based PWM
method is preferred under this condition in multilevel
inverters. This paper focuses on carrier based PWM
techniques which have been extended for use in multilevel
inverter topologies by using multiple carriers.
A. Carrier based PWM methods using Sub-harmonic
PWM Method
The sub-harmonic pulse-width modulation (SPWM)
is commonly used in industrial applications. The
frequency of reference signals f
r
determines the inverter
output frequency f
0
; and its peak amplitude A
r
controls
the modulation index M.
. Fig.6 demonstrates the sine-
triangle method for a three phase seven-level inverter. Therein,
the a-phase modulation signal is compared with six (n-1 in
general) triangle waveforms. For a seven level inverter it
requires 6 triangular carriers.
Fig.6 Sinusoidal reference with
triangular carriers for a 3-phase seven-
level PWM scheme
B. Carrier based PWM methods using Modified Spac
vector PWM
In the SPWM scheme for two-level inverters, each
reference phase voltage is compared with the triangular carrier
and the individual pole voltages are generated, independent of
each other [6]. To obtain the maximum possible peak
amplitude of the fundamental phase voltage, in linear
modulation, a common mode voltage, Voffset1, is added to the
reference phase voltages [9, 1], where the magnitude of
Voffset1 is given by
2
)( minmax
1
VV
Voffset
+−
= -- (1)
In (1), Vmax is the maximum magnitude of the three sampled
reference phase voltages, while Vmin is the minimum
magnitude of the three sampled reference phase voltages, in a
sampling interval. The addition of the common mode voltage,
Voffset1, results in the active inverter switching vectors being
centered in a sampling interval, making the SPWM technique
equivalent to the modified reference PWM technique [9].
Equation (1) is based on the fact that, in a sampling interval,
the reference phase which has lowest magnitude (termed the
min-phase) crosses the triangular carrier first, and causes the
first transition in the inverter switching state. While the
reference phase, which has the maximum magnitude (termed
the max-phase), crosses the carrier last and causes the last
switching transition in the inverter switching states in a two-
level modified reference PWM scheme [9, 2]. Thus the
switching periods of the active vectors can be determined from
the (max-phase and min-phase) sampled reference phase
voltage amplitudes in a two-level inverter scheme [3]. The
SPWM technique, for multilevel inverters, involves comparing
the reference phase voltage signals with a number of
symmetrical level-shifted carrier waves for PWM generation
[8]. It has been shown that for an n-level inverter, n-1 level-
shifted carrier waves are required for comparison with the
sinusoidal references [8]. Because of the level-shifted
multicarriers as shown in (Fig. 4), the first crossing (termed
the first-cross) of the reference phase voltage cannot always be
the min-phase. Similarly, the last crossing (termed the third-
cross) of the reference phase voltage cannot always be the
max-phase. Fig.6 demonstrates the sine-triangle method for a
three phase seven-level inverter.
Fig. 7 Modified reference voltages and triangular carriers for a 3-phase seven-
level PWM scheme

2013 International Conference on Power, Energy and Control (ICPEC)
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V. SIMULATION RESULTS
The Simulation was conducted to verify the operation of the
Cascaded H-Bridge MLI and proposed MLDCL inverter using
SPWM and Modified SVPWM Techniques.
A. Seven Level Cascaded H-bridge MLI for 1–Ф :
(i) Sub-harmonic PWM Method (SPWM):
Fig.8 line voltage of 1–Ф seven level Cascaded H-Bridge MLI using SPWM
Fig.9 FFT analysis of line voltage of 1–Ф seven level cascaded H-Bridge MLI
using SPWM
(ii) Modified Spac vector PWM(MSVPWM)
Fig.8 line voltage of 1–Ф seven level Cascaded H-Bridge MLI using Modified
SVPWM
Fig.10 FFT analysis of line voltage of 1–Ф seven level cascaded H-Bridge
MLI using Modified SVPWM
B. Proposed Seven Level MLDCLI for 1–Ф
(i) Sub-harmonic PWM Method:
Fig.11 line voltage of 1–Ф seven level MLDCL Inverter using SPWM
Fig.12 FFT analysis of line voltage of 1–Ф seven level MLDCL inverter using
SPWM
(ii) Modified Spac vector PWM
Fig.13 line voltage of 1–Ф seven level MLDCL Inverter using Modified
SVPWM
Fig.14 FFT analysis of line voltage of 1–Ф seven level MLDCL inverter using
Modified SVPWM
C. Seven Level Cascaded H-bridge MLI for 3–Ф :
(i) Sub-harmonic PWM Method:
Fig.15 line voltage of 3–Ф seven level Cascaded H-Bridge MLI using SPWM

2013 International Conference on Power, Energy and Control (ICPEC)
697
Fig.16 FFT analysis of line voltage of 3–Ф seven level MLDCL inverter using
SPWM
(ii) Modified Spac vector PWM
Fig.17 line voltage of 3–Ф seven level Cascaded H-Bridge MLI using
Modified SVPWM
Fig.18 FFT analysis of line voltage of 3–Ф seven level MLDCL inverter using
Modified SVPWM
D. Proposed Seven Level MLDCLI for 3–Ф
(i) Sub-harmonic PWM Method:
Fig.19 line voltage of 3–Ф seven level MLDCL Inverter using SPWM
Fig.20 FFT analysis of line voltage of 3–Ф seven level MLDCL inverter using
Modified SVPWM
(ii) Modified Spac vector PWM
Fig.21 line voltage of 3–Ф seven level MLDCL Inverter using SPWM
Fig.22 FFT analysis of line voltage of 3–Ф seven level MLDCL inverter using
Modified SVPWM
The simulation results of the seven level cascaded H-
bridge inverter and proposed MLDCL Inverter using SPWM
and Modified SVPWM for 1–Ф and 3–Ф and its corresponding
harmonic spectrums are shown in above figures. These
waveforms confirm the operation of 7-level cascaded H-bridge
and MLDCL inverters described in section II and III using
SPWM and modified SVPWM with resistive load.
E. COMPARISON OF RESULTS:
Input voltage = 300v
Switching frequency = 10 KHz
Modulation index = 0.866
Table. 4 comparison of THD for various PWM Methods for 1–Ф
PWM
Technique
Cascaded 7LI Multilevel DCL 7LI
Fundamental
output
voltage(volts)
THD
(%)
Fundamental
output
voltage(volts)
THD
(%)
Sub-
harmonic
PWM
253.4 23.13 268.4 22.01
Modified
space
vector
PWM
258.1 22.17 274.1 20.64

2013 International Conference on Power, Energy and Control (ICPEC)
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A summary of THD and fundamental output voltage for
various multilevel inverter topologies with their control
strategies are presented. i.e., 1–Ф 7-Level cascaded inverter
and 1–Ф 7-level MLDCL inverters were simulated using
SPWM and modified SVPWM with triangular carriers. And it
is concluded that 1–Ф 7-level MLDCL inverter using modified
SVPWM has given good fundamental output voltage (274.1
V) with less THD (20.64%).
Table. 5 comparison of THD for various PWM Methods for 3–Ф
A summary of THD and fundamental output voltage for
various multilevel inverter topologies with their control
strategies are presented. i.e., 3–Ф 7-Level cascaded inverter
and 3–Ф 7-level MLDCL inverters were simulated using
SPWM and modified SVPWM with triangular carriers. And it
is concluded that 3–Ф 7-level MLDCL inverter using modified
SVPWM has given good fundamental output voltage (274.2
V) with less THD (6.84%).
V. HARDWARE IMPLEMENTATION OF
PROPOSED MLDCL INVERTER CIRCUIT
Fig. 23 Block Diagram of Overall System
Fig. 24 Proposed 1–Ф 7-level DC Link inverter hardware diagram
Fig. 25 output line voltage of 1–Ф 7-level DC Link inverter
VI. CONCLUSION:
The presented seven level MLDCL inverters can eliminate
roughly half the number of switches, their gate drivers
compared with the existing cascaded MLI counterparts.
Despite a higher total VA rating of the switches, the cascaded
MLDCL inverters are cost less due to the savings from the
eliminated gate drivers and from fewer assembly steps because
of the substantially reduced number of components, which
also leads to a smaller size and volume.
The simulation results with harmonic spectrum are
presented for cascaded and proposed MLDCL inverters with
various PWM techniques and in this paper it is concluded that
3–Ф 7-level MLDCL inverter using modified SVPWM has
given good fundamental output voltage (274.2 V) with less
THD (6.84%) when compared with other techniques.
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Cascaded 7LI Multilevel DCL 7LI
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THD
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Fundamental
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THD
(%)
Sub-
harmonic
PWM
254.5 10.78 269.1 9.02
Modified
space
vector
PWM
262.1 8.79 274.2 6.84

2013 International Conference on Power, Energy and Control (ICPEC)
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S.Nagaraja Rao was born in kadapa, India.
He received the B.Tech (Electrical and
Electronics Engineering) degree from the
Jawaharlal Nehru Technological University,
Hyderabad in 2006; M.Tech (Power
Electronics) from the same university in
2008.He is currently an Asst.Professor of
the Dept. of Electrical and Electronic Engineering, R.G.M
College of Engineering and Technology, Nandyal. He has
published several National and International Journals and
Conferences. His area of interest power electronics and
Electric Drives.
E-mail: nagarajraomtech@gmail.com
Dr. D. V. Ashok Kumar, was born in
Nandyal, India in 1975. He received the B.E
(Electrical and Electronics Engineering)
degree from Gulbarga University and the
M.Tech (Electrical Power Systems) from
J.N.T.U.C.E, Anantapur and Ph.D in Solar
Energy from same University. Currently he
is working as Pricipal in Syamaldevi
Institute of Technology for women, Nandyal, He has
published/presented technical research papers in national and
international Journals/conferences. His field of interest
includes Electrical Machines, Power electronics, Power
systems and Solar Energy.
E-mail: Principal.sdit@gmail.com
Ch. Sai Babu received the B.E from
Andhra University (Electrical & Electronics
Engineering), M.Tech in Electrical
Machines and Industrial Drives from REC,
Warangal and Ph.D in Reliability Studies of
HVDC Converters from JNTU, Hyderabad.
Currently he is working as a Professor in
Dept. of EEE in JNTUK, Kakinada. He has published several
National and International Journals and Conferences. His area
of interest is Power Electronics and Drives, Power System
Reliability, HVDC Converter Reliability, Optimization of
Electrical Systems and Real Time Energy Management.
E-mail: chs_eee@yahoo.co.in