Investigation and Minimization of Underfill Delamination in Flip Chip Packages

Abstract

A generalized plane strain condition is assumed for an edge interfacial crack between die passivation and underfill on an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursions are treated as loading conditions. The design factors studied include underfill elastic modulus, underfill coefficient of thermal expansion (CTE), fillet height, and die overhang. Varying underfill modulus and CTE produces a different stress field at underfill/die passivation interface, different stress intensity factor (SIF), and phase angle (ψ) even under the same loading condition. The baseline case uses underfill with elastic modulus of 6 GPa, CTE of 36 ppm/°C and fillet height equal to half die thickness. Four more cases involving underfill material properties are investigated by varying elastic modulus between 3 and 9 GPa, and by varying CTE between 26 and 46 ppm/°C. The effect of fillet height is also studied by assuming no fillet and full fillet, i.e., fillet height equal to die thickness. Finally, two cases concerning the influence of die overhang, defined as the nominal distance between outermost solder joint and die edge, are investigated. Fracture parameters, including energy release rate (G) and phase angle (ψ), are evaluated as a function of dimensions. Underfill material properties (elastic modulus and CTE), fillet configuration, and die overhang can be optimized to reduce the risk of underfill delamination in flip chip or direct chip attach (DCA) applications.

Full text

86 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 1, MARCH 2004
Investigation and Minimization of Underfill
Delamination in Flip Chip Packages
Charlie Jun Zhai, Sidharth, Richard C. Blish II, and Raj N. Master
Abstract—A generalized plane strain condition is assumed for
an edge interfacial crack between die passivation and underfill on
an organic substrate flip chip package. C4 solder bumps are explic-
itly modeled. Temperature excursions are treated as loading con-
ditions. The design factors studied include underfill elastic mod-
ulus, underfill coefficient of thermal expansion (CTE), fillet height,
and die overhang. Varying underfill modulus and CTE produces
a different stress field at underfill/die passivation interface, dif-
ferent stress intensity factor (SIF), and phase angle even under
the same loading condition. The baseline case uses underfill with
elastic modulus of 6 GPa, CTE of 36 ppm/ C and fillet height equal
to half die thickness. Four more cases involving underfill material
properties are investigated by varying elastic modulus between 3
and 9 GPa, and by varying CTE between 26 and 46 ppm/ C. The
effect of fillet height is also studied by assuming no fillet and full
fillet, i.e., fillet height equal to die thickness. Finally, two cases con-
cerning the influence of die overhang, defined as the nominal dis-
tance between outermost solder joint and die edge, are investigated.
Fracture parameters, including energy release rate and phase
angle , are evaluated as a function of dimensions. Underfill ma-
terial properties (elastic modulus and CTE), fillet configuration,
and die overhang can be optimized to reduce the risk of underfill
delamination in flip chip or direct chip attach (DCA) applications.
I. INTRODUCTION
IT IS WELL known that underfill has significant impact on
flip chip package reliability. Organic substrate flip chip tech-
nology with underfill provides a cost effective solution to the
demands of electronic packaging industry for increased relia-
bility. Underfill protects solder bumps by considerably reducing
the stress. However, underfill itself is subject to shear or peeling
stress, so it may induce additional failure modes. For instance,
imperfect underfill with voids or microcracks produces cracks
or delamination under temperature cycling conditions. Delam-
ination, driven by coefficient of thermal expansion (CTE) mis-
match between organic substrate and silicon die, at bi-material
interfaces such as underfill and die passivation or underfill and
substrate solder mask, is one of the dominant failure modes,
particularly if underfill is imperfect. Delamination behaves as
a mixed mode interfacial fracture. Mode mixity is characterized
by phase angle , which is determined by the loading configu-
ration and thermal mismatch. Unlike fracture toughness for ho-
mogeneous materials, interfacial fracture toughness is depen-
dent on both interfacial adhesion property and phase angle.
Suo et al. [1] measured interfacial fracture toughness as
a function of phase angle for a specific Epoxy/Plexiglass
interface. Fig. 1, extracted from [1], shows that interfacial
Manuscript received July 18, 2003; revised October 28, 2003.
The authors are with Advanced Micro Devices, Inc., Sunnyvale, CA
94088-3453 USA (e-mail: charlie.zhai@amd.com).
Digital Object Identifier 10.1109/TDMR.2003.822339
Fig. 1. Interface toughness versus mode mixity [1].
fracture toughness increases monotonically with phase angle,
as the crack mode shifts to Mode II from Mode
I. Clearly, interfacial fracture toughness, , at pure opening
mode is much lower than at pure shear mode .
Although Fig. 1 is based on data for a specific interface, the
general trend observed is valid for other interfaces.
The three-dimensional (3-D) junction at die corner and under-
fill is a potential failure site due to the presence of split singu-
larity [1], [2]. Singularity strength depends on associated mate-
rial properties and geometry. A delamination initiated from the
die edge takes the form of an interfacial microcrack. In addition,
initial delamination may also be caused by formation of micro-
cracks or voids during dispensing process or surface contamina-
tion. As some initial underfill flaws are unavoidable, preventing
flaw propagation as an unstable crack is important.
The purpose of this paper is to study the effects of various
design variables including underfill material properties, fillet di-
mensions, and die overhang on underfill delamination fracture
parameters. Since a bi-material interfacial crack is fundamen-
tally a mixed mode, fracture parameters must include both en-
ergy release rate and phase angle.
II. INTERFACIAL FRACTURE MECHANICS
Unlike cracks in homogenous materials, bi-material interfa-
cial cracks exhibit a different behavior. In isotropic homogenous
materials, cracks tend to grow along the path where the frac-
ture mode is purely opening mode (i.e., Mode I). However, a
weak bi-material interface normally prompts the crack to prop-
agate along the interface. As a result, interfacial cracks exhibit
mode mixity with coupling between mode I (opening mode) and
mode II (shear mode). By introducing a characteristic length,
, a loading phase angle can be defined to characterize mode
mixity.
1530-4388/04$20.00 © 2004 IEEE

ZHAI et al.: INVESTIGATION AND MINIMIZATION OF UNDERFILL DELAMINATION IN FLIP CHIP PACKAGES 87
Ahead of crack tip,
(1)
(2)
where is the distance from crack tip in polar coordinates,
and are stress components normal and parallel to crack sur-
face, respectively, and and are stress intensity factors in
mode I and II, respectively. The oscillatory index, , is a func-
tion of the material properties:
where is the shear modulus and – for plane strain
or for plane stress. The subscripts 1 and 2
for , , and are associated with the two different materials
on either side of the interface.
Therefore
(3)
In this study, m is chosen as the characteristic length
because the focus is on the area near the crack tip. The choice of
is arbitrary. If the same characteristic length is used to study a
particular effect (e.g., fillet height variation), the difference be-
tween the results of calculated phase angles will be independent
of characteristic length [1].
Energy release rate can be written as
(4)
where
The failure criterion for delamination growth is
(5)
Interfacial toughness, , is a function of phase angle ,
as illustrated by the trend in Fig. 1 for a different material set.
III. ENRICHED FINITE ELEMENT AND FRAC3D
In order to improve flip chip package reliability, it is neces-
sary to conduct interfacial fracture mechanics analysis, in ad-
dition to conventional finite element analysis (FEA), to char-
acterize interfaces. Two numerical methods to compute frac-
ture parameters are: virtual crack growth method and crack tip
opening displacement (CTOD) method. While these methods
can use energy release rate results from commercial FEA soft-
ware, such as ANSYS or ABAQUS, adequately refined finite
element mesh and complicated extrapolation algorithms are re-
quired near the crack tip region to calculate the stress intensity
factor (SIF) and the phase angle [3]–[6]. In this paper, a dif-
ferent strategy is used to implement fracture analysis. ANSYS
is used to build the solid model for a flip chip package. Frac3D,
developed by Lehigh University, is employed to conduct frac-
ture mechanics analysis. FRAC3D incorporates enriched crack
tip elements that contain analytic asymptotic displacement field
(a)
(b)
Fig. 2. (a) Schematic illustration of a flip chip package. (b) FEA mesh of a
3-D flip chip model.
and stress field. FRAC3D is highly efficient for computing the
required fracture parameters for thermomechanical problems by
using relatively small number of finite elements [7], [8].
Enriched crack tip elements as formulated for 3-D problems,
contain a closed form asymptotic field for crack tip displace-
ments, in addition to the usual polynomial interpolation func-
tion. Detailed description of numerical implementation proce-
dure is shown in Appendix A and in [7] and [8]. Once SIF’s
, and are obtained, energy release rate and phase
angle are calculated by using (3) and (4). It is noteworthy that
and do not identify with loading modes, i.e., tension and
shear are not separable near an interface. For instance, a negative
value does not necessarily indicate a compressive stress state
around a crack tip. In fact, the normal and shear stress compo-
nents and oscillate near crack tip if the oscillatory index
is nontrivial.
IV. MODEL
Since temperature cycling is the cause of failures studied in
this paper, thermal excursion from 165 C to room temperature
25 C is used as the temperature loading. The assembly is as-
sumed to be in stress free state at 165 C, which is a typical
curing temperature of epoxy underfill.
Most material properties are assumed to be isotropic linear
elastic. Substrate material, BT (Bismaleimide Triazine), is as-
sumed to be linear, orthotropic, and elastic. Although high-Pb
or eutectic solder mechanical properties are rate- and temper-
ature-dependent, material nonlinearity is not the focus of this
work and will not be considered. Underfill material is assumed
to behave linear elastically.
As illustrated in Fig. 2(a), a pre-existing crack is inserted
along the interface between silicon die and underfill with one
crack tip pinned at the die corner. The crack replicates the sit-
uation where a microcrack is initiated from the die edge or an
existing flaw due to nonclean surface. Since delamination usu-
ally initiates from die edge and then propagates toward the die
center, we will focus on fracture behavior at the crack tip far

88 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 1, MARCH 2004
TABLE I
MATERIAL PROPERTIES FOR FLIP CHIP PACKAGE
from die edge. Fig. 2(a) explains the definitions of fillet height
and die overhang size .
Frac3D requires geometric finite element data as input.
ANSYS is a powerful modeling tool that provides great
flexibility of parametric modeling. In this study, a parametric
flip chip model with capability of automatic crack generation
was generated. Fig. 2(b) shows finite element mesh of a 3-D
strip model. A strip parallel to the length of the square die
is considered. The geometrical model includes silicon die
(10.2-mm wide, 0.8-mm thick), BT substrate (1.2-mm thick),
solder bumps (0.1-mm thick with 0.36-mm pitch) and underfill
(0.1-mm thick). Fillet shape is assumed to be right-angled
isosceles triangle, which implies that fillet width is equal to
fillet height. Material properties used are given in Table I.
The finite element mesh consists of two layers of 20-node
solid elements in the Z-direction [see Fig. 2(b)]. The mesh was
generated through an extension of a 2-D mesh in the Z-direc-
tion in two steps. The first step is to extend the 2-D mesh with
a length equal to half the solder joint diameter, followed by a
second step to extend elements to half the solder pitch. Both
layers of elements consist of silicon die, BT substrate and un-
derfill, but the first layer of elements also includes solder bumps.
The geometric model describes a representative slice of flip chip
module applying all existing symmetry conditions. Although a
complete 3-D model would provide more accurate stress/defor-
mation results, the 3-D slice model is adequate for a first-order
solution. Only half the strip of the package is modeled because
of symmetric geometry and loading conditions.
A fine mesh is used near crack tip regions. The finite
element mesh is exported to a Frac3D format file. Input files
to run Frac3D also include a definition of material properties,
boundary conditions, and temperature profile. A generalized
plane strain condition, which specifies a coupled degree of
freedom in the Z-direction, is applied to the model. While the
generalized plane strain condition requires the front surface to
deform by the same magnitude in the Z-direction, it does not
assume vanishing normal stress as for a plane stress condition
or vanishing normal strain as for a plane strain condition.
Hence, the generalized plane strain condition, to a large extent,
accommodates the actual deformation state without going
further into complicated full 3-D model. At the die corner, the
crack is modeled as an edge-through crack and not a full 3-D
crack. The design factors studied in this paper are:
1) underfill material properties (elastic modulus and CTE);
2) underfill fillet height;
3) die overhang (nominal distance from outermost solder
joint to die edge).
A full factorial design of experiment (DOE), which
consists of three levels of elastic modulus and three levels of
Fig. 3. Contour plot of after temperature drop (Deformation is
exaggerated 20 ).
CTE values for underfill material, is implemented through
modeling. The baseline case assumes an
GPa, ppm/ C for the underfill and
mm. A crack length of 0.1 mm is a conservative
estimate for initial defect size. The elastic modulus values used
are 3, 6, and 9 GPa. The CTE values used are 26, 36, and
46 ppm/ C. The full factorial DOE allows full characterization
of individual as well as coupled (interactive) effects of underfill
mechanical properties on fracture parameters.
Next, the influence of fillet size up the die edge upon under-
fill delamination is investigated by varying the baseline case,
which assumes a fillet height of half the Si chip thickness, to
comprehend two more configurations, namely, zero height and
full height. These three fillet configurations are intended to
mimic properly encapsulated, under encapsulated, and over en-
capsulated situations resulting from variable underfill dispense
conditions.
Finally, the overhang issue is investigated by varying over-
hang from its baseline value (0.3 mm) to 0.2 and 0.4 mm, re-
spectively.
V. R ESULTS
Fig. 3 shows contour plots for stress component obtained
after ANSYS post-processing. Near the crack tip the normal
stress is tensile, which implies an opening mode at crack
tip. The package is warped in a convex shape as temperature is
dropped to room temperature. Fig. 4 clearly demonstrates that an
originally closed crack surface tends to open at both crack tips.
However, conventional stress analysis (FEA) is unable to reveal
asymptotic stress field at crack tip without introducing singular
elements. Fracture analysis is conducted using Frac3D instead.
It is important to understand the change of fracture parame-
ters including both energy release rate and phase angle, during
crack propagation, i.e., increase of crack length. Fig. 5 plots the
energy release rate as a function of crack length, for the baseline
case. The strain energy release rate for different temperature ex-
cursions can be readily obtained from the fact that energy release
rate is proportional to . As shown in Fig. 5, the strain en-
ergy release rate G increases with increasing crack length.
Fig. 6 shows that phase angle de-
creases with crack length, indicating an increasing contribution

ZHAI et al.: INVESTIGATION AND MINIMIZATION OF UNDERFILL DELAMINATION IN FLIP CHIP PACKAGES 89
Fig. 4. Crack opening after loading.
Fig. 5. Energy release rate versus crack length.
Fig. 6. Phase angle versus crack length.
from mode I. As the crack mode shifts from mode II to mode I,
interfacial fracture toughness decreases as seen from trends in
Fig. 1. Therefore, according to the failure criterion for delam-
ination growth, i.e., , the delamination may grow
unstably because of decreased toughness , and increased
crack driving force versus crack length.
was found to be significantly smaller than or .
Hence, its contribution is negligible.
The effects of underfill properties on fracture parameters are
shown in Figs. 7 and 8. As shown in Fig. 7, energy release rate
increases with underfill modulus, which indicates that stiffer un-
derfill encapsulation will generate a larger crack driving force
and accelerate crack propagation once the crack is initiated.
Fig. 7. Effects of underfill properties on energy release rate.
(a)
(b)
Fig. 8. (a) No delamination at package with moderate fillet. (b) Underfill
delamination at package with low fillet.
However, this result does not necessarily imply that more com-
pliant underfill material would reduce the risk of overall flip
chip package reliability. Excessively compliant underfill fails
to support stress, loading the solder bumps to a greater degree,
which may lead to solder bump cracking prior to underfill de-
lamination. An appropriate choice of underfill modulus should
consider reliability associated with various failure mechanisms
including underfill delamination and solder bump (under bump
metallization) cracking.
The effect of underfill CTE on the energy release rate, as
shown in Fig. 7, clearly demonstrates that, in addition to a global
CTE mismatch between silicon die and organic substrate, the

90 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 1, MARCH 2004
(a)
(b)
Fig. 9. (a) Effect of fillet height on energy release rate. (b) Effect of fillet size
on phase angle.
local CTE mismatch among silicon die, underfill, and solder
bumps also play an important role in determining fracture
behavior for underfill delamination. For example, energy release
rate increases by nearly 20% if underfill CTE varies from
26 ppm/ C to 36 ppm/ C. It is shown that a lower CTE value,
closer to that of solder bumps, produces a smaller energy
release rate. The result suggests that underfill delamination can
decrease by reducing underfill CTE to match solder CTE.
Cross-section pictures [Fig. 8(a) and (b)] from failure anal-
ysis of post-temperature cycling parts, under 0 C to 100 C,
show that fillet height has an impact on underfill delamination.
While a nominal fillet height does not suffer a visible delamina-
tion/crack after 500 cycles [Fig. 8(a)], the part with smaller fillet
causes delamination between die and underfill [Fig. 8(b)]. This
indicates that fillet configuration influences the delamination of
die/underfill interface.
Different fillet sizes arise from variation of underfill volume
and process control during dispensing. As seen in Fig. 9(a) and
(b), it is noteworthy that both high and low fillet, i.e., over en-
capsulated and under encapsulated fillet, produce a larger en-
ergy release rate. This indicates that fillet size needs to be prop-
erly controlled during underfill dispense. There exists an op-
timal range of fillet size to minimize energy release rate and de-
sign rules must be derived from specific package configuration
and dimensions.
The die overhang, i.e., the distance between outmost solder
bump and die edge, is an important factor in the package de-
sign. Since overhang is directly associated with the usable area
for I/O footprint, it is desirable to have a short overhang to max-
imize useable area. Fig. 10(a) shows that energy release rate al-
most remains constant with decreasing overhang while phase
angle [Fig. 10(b)] shifts from mode II to mode I, i.e., shear mode
(a)
(b)
Fig. 10. (a) Effects of die overhang on energy release rate. (b) Effects of die
overhang on phase angle.
to open mode. It is noted that interfacial fracture toughness is
usually smaller for the opening mode than for the shear mode.
Therefore, it is not beneficial that the mode mixity shift be domi-
nated by the open mode. This indicates that overhang needs to be
maintained within a certain critical range to avoid crack growth.
The comparison study of fillet height and overhang size is
based on the assumption that initial crack length is 0.1 mm, and
the general trend presented is valid for other choices of crack
length, as discussed in Section IV.
VI. CONCLUSION
It has been demonstrated that it is possible to optimize de-
sign factors to reduce the risk of underfill delamination. The
design factors studied in this paper involve material properties
including elastic modulus and CTE, underfill fillet size and die
overhang. We find that underfill delamination for this partic-
ular flip chip configuration exhibits instability as the energy re-
lease rate increases with crack length. It is clear that increasing
underfill modulus and CTE will increase energy release rate.
Fillet optimization is proven to be an effective way to prevent
underfill delamination. Moderate fillet height is demonstrated
to generate the least energy release rate. Lower fillet (under en-
capsulation) has the highest probability of causing underfill de-
lamination because it results in higher energy release rate and
small phase angle. From fracture analysis, we also found that an
excessively small die overhang will shift the crack mode from
mode II dominated to mode I dominated, reducing the interface
fracture toughness substantially. As a consequence, die over-
hang needs to be controlled to be above a certain critical value,
which will depend on the configuration analyzed.

ZHAI et al.: INVESTIGATION AND MINIMIZATION OF UNDERFILL DELAMINATION IN FLIP CHIP PACKAGES 91
APPENDIX A
The enriched element displacements , , and take the form
[7], [8]
(A1)
(A2)
(A3)
In (A1)–(A3) and represent the unknown nodal
displacements and are the conventional element shape func-
tions in terms of the element’s local coordinates. and
represent the mode I, II, and III stress intensity factors
varying along the crack front defined by the interpolation func-
tions . The contributions from these stress intensity fac-
tors are then assembled into the global stiffness matrix in the
same manner as for regular elements. The function is a “ze-
roing function”that provides inter-element compatibility be-
tween the enriched crack tip elements and the elements that sur-
round the enriched elements.
ACKNOWLEDGMENT
The auhtors would like to thank Dr. H. Nied and X. Hu of
Lehigh University for many helpful discussions on Frac3D.
They would also like to acknowledge contributions from
D. Natekar when he was at AMD.
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Charlie Jun Zhai received the Ph.D. degree in me-
chanical engineering with a focus on solid mechanics
from the Georgia Institute of Technology, Atlanta, in
2000.
He worked in the Personal Communicational
Sector, Motorola, Inc., from 2000 to 2001, where
he conducted research on advanced packaging and
assembly technology development for telecommu-
nication products. Since 2001, he has been with
Advanced Micro Devices, Inc., Sunnyvale, CA, in
the reliability modeling group. His research interests
are in FEA modeling, fracture mechanics, IC back-end reliability, and advanced
packaging. He has more than 20 publications.
Sidharth received the Ph.D. degree in mechanical
engineering with a focus on electronic packaging and
reliability from the University of Maryland, College
Park, in 1995.
Since 1995, he has been with Advanced Micro
Devices, Inc. (AMD), Sunnyvale, CA, as a Senior
Member of the Technical Staff in the Reliability
Modeling Group. He has served as Co-Chair of
the IRPS Packaging and Assembly Committee for
the past several years. His research interests are
in electronic packaging, numerical modeling, and
product quality and reliability.
Richard C. Blish II received the B.S. degree in
physics and the Ph.D. degree in materials sci-
ence from the California Institute of Technology,
Pasadena, in 1963 and 1967, respectively.
He was with Bell Laboratories from 1967 to 1969
correlating electrical properties of diode arrays to
crystalline damage detected by X-ray topography.
From 1969 to 1980, he was with Signetics, working
on XRF, SEM, microprobe, metallography, chro-
matography, and plasma etching. From 1980 to
1994, he was with Intel in a variety of management
roles in package reliability. From 1995 to the present, he has been with
Advanced Micro Devices, Inc. (AMD), Sunnyvale, CA, currently as an AMD
Fellow in Reliability Modeling. He has 36 patents and 31 publications.
Dr. Blish has won awards for paper quality at IRPS and ECTC. He is a past
General Chair and Chairman of the Board of IRPS, chaired the SEMATECH
RTAB for 2000, and was appointed to the Program Committee for IEDM in
2003.
Raj N. Master joined AMD in 1996. At AMD, Raj
is Senior AMD Fellow. Senior Fellow is the highest
technical position at AMD. There are only 6 Senior
Fellows. He was responsible to successfully transfer
the IBM C4/BGA technologies to AMD and set up
high volume manufacturing in Penang which has to
date produced more then 100 million flip chip as-
semblies. He led the Organic packaging development
and manufacturing which is now in high volume pro-
duction. He provides technical guidance for equip-
ment and processes for C4/BGA manufacturing lines
in Penang and Singapore. He also provides technical expertise and guidance
to product lines, Failure analysis, reliability and quality organizations within
AMD. He manages advanced packaging group involved in developing strategic
enabling technologies in the area of materials, process, thermal and electrical
performance. He is also manager of the Lead Free program of AMD. Raj joined
AMD after spending 21 years at IBM. He was Senior Technical Staff member
at IBM prior to joining AMD. He was technically responsible for packaging de-
velopment and manufacturing as related to C4, Ball Grid Array, Column Grid
Array, Board Level Reliability and Multi Layer Ceramic Substrate. Raj has 32
U.S. patents issued to him and has published over 60 technical papers.