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Real-Time FPGA Implementation of Digital Video
Watermarking Techniques using Co-Design
Approach: Comparative Study
Noureddine AISSAOUI
´
Ecole Militaire Polytechnique
Laboratoire Syst`
emes
´
Electroniques et Num´
eriques
Alger, Alg´
erie 16111
aissaouifn@gmail.com
Redouane KAIBOU ID
´
Ecole Militaire Polytechnique
Laboratoire Syst`
emes
´
Electroniques et Num´
eriques
Alger, Alg´
erie 16111
kaibouredouane@gmail.com
Mohamed Salah AZZAZ ID
´
Ecole Militaire Polytechnique
Laboratoire Syst`
emes
´
Electroniques et Num´
eriques
Alger, Alg´
erie 16111
ms.azzaz@gmail.com
Abstract—This paper presents a Genesys-2 FPGA implemen-
tation of three video watermarking techniques in both spatial and
frequency domains followed by a comparative analysis. The video
acquisition is realized using OV7670 camera used for real-time
watermarking with each technique both in visible and invisible
schemes with Video Graphics Adapter (VGA) display validations.
The techniques implemented are based on Least Significant bit
(LSB), additive spatial and additive frequency watermarking.
All implementations have been realized in Software/Hardware
(SW/HW) co-design using Vivado-HLS tool achieving low area,
high speed of up to 130 MHz and low power consumption
that did not exceed 827 mw all along with good watermarking
performances of imperceptibility with fairly good robustness for
most of the geometric and image processing attacks.
Keywords—Watermarking, FPGA, DWT, Vivado, Image Auten-
tichation.
I. INTRODUCTION
At present, the excessive use of multimedia has made the
tasks of protecting information more difficult, in particular,
to ensure confidentiality and guarantee the authenticity of the
information [1]. Hence, more focus has been put on securing
the content of digital media such as video conferencing, mili-
tary surveillance, pay-per-view TV (PPV), multimedia systems
of industry and broadcast monitoring to name a few [2].
Watermarking and Encryption are being implemented both in
separate and combined algorithms to achieve this goal. The
integration of these algorithms is made possible as more plat-
form alternatives are being released in an accelerated pace. This
evolution of the hardware is accompanied by an outstanding
development of methods with a tendency of going for higher-
level languages that combine the advantages of both hardware
and software implementations [3].
As raw video signal is composed of several frames, real-time
watermarking becomes a hard task to realize in addition to
the increasing computational burden. In this context, several
methods are being investigated to meet this requirement and
others both in spatial and transform domains. Among which
transparency, resistance, security, and capacity are the main
parameters that define a given watermarking scheme efficiency
[4]. However, implementation complexity is an additional
parameter acting in the opposite direction that needs to be
carefully considered. This latter is made more tangible in
live video broadcasting applications where latency effect can
influence the quality of transmission [5].
Embedding a watermark as being the core principle of wa-
termarking can fall into two categories in terms of human
perception visible such as TV channel logo or invisible such
as fingerprint or signature [6]. Bearing in mind that both
techniques are implemented in VLSI configurations that fit
in multiple purposes, more than one application can be con-
cretized in a single platform that can integrate ideally an
encryption scheme to increase the watermarking security [7].
II. RELATED PREVIOUS WORKS
Recently, several digital watermarking systems have been
implemented on FPGA hardware platforms, where a num-
ber of researchers adopt a co-design approach with different
techniques in spatial and frequency domains. Bhaisare et al.
[8] presented an FPGA hardware implementation of a digi-
tal watermarking system. The implementation uses invisible
and semi-fragile watermarks into compressed video streams
in real-time in the discrete cosine transform (DCT) domain
on Xilinx Spartan3. The results showed that the proposed
algorithm has a very good hidden invisibility, good security and
robustness for a lot of hidden attacks. Tamilvabnan et al. [9]
proposed Discrete Wavelet Transform (DWT) to authenticate
the multimedia image and it can convert the image from
spatial domain to frequency domain. This system has been
developed on Xilinx Spartan3 FPGA device. The proposed
algorithm gave good reults in terms of imperceptibility and
security. Das et al. [10] implemented a Reversible Contrast Map
algorithm (RCM) using OV7670 camera through Zedboard
FPGA. The gray scaled video watermarking has achieved high
performances in a pipeline structure reaching a speed of 150
MHz and a latency of 876.626 ns with a throughput 62.328
Mbps. Shivdeep et al. [11] proposed FPGA implementation
of Reversible Image Watermarking (RIW) with Difference
Expansion (DE) algorithm using HLS implementation. The
design achieved good performances in terms of area ressources
consumption compared to existing RIW based architectures.
The rest of the paper is organized as follows. Section 3 presents
the proposed work that consists of three different watermark-
ing techniques. Section 4 presents their FPGA synthesis and
implementation results. Section 5 evaluates the implemented
techniques in terms of imperceptibility, robustness and com-
plexity. The paper is concluded in Section 6.
978-1-6654-8042-0/22$31.00 ©2022 IEEE
III. PROPOSED WORK
The sequence of the elaborated work as shown in the
overall diagram is illustrated in Figure (1). It consists of FPGA
implementation of three digital watermarking systems applied
on real-time video input, namely LSB spatial watermarking,
additive spatial watermarking and additive frequency water-
marking.
Fig. 1: Elaborated Work Sequence.
A. Video Acquisition
The input video has been acquired from a low-cost camera
type OV7670 using Genesys-2 Pmod connections in VHDL.
The camera module is an image capturing device which is
designed for use in embedded systems. It supplies a real-time
video of a 640 ×480 frames resolution. Figure 2 illustrates the
used camera.
Fig. 2: OV7670 used Camera.
B. Watermarking Techniques
The proposed watermarking techniques with the algorithm
of each one are described as follows:
1) LSB Spatial Watermarking: The process of watermark
embedding/extraction in the LSB spatial domain consists of
embedding a black and white watermark into the video pixels
frames blue component LSB in using a reversible XOR op-
eration. Extraction uses the same algoritm in reverse order as
illustrated in Figure (3)
2) Additive Spatial Watermarking: The embedding phase
in this scheme consists of embedding RGB components of the
watermark in the corresponding RGB components of the video
frames using a visibility factor α. The algorithm is illustrated
in Figure (4)(a).
(a) Embedding
(b) Extraction
Fig. 3: LSB Spatial Watermarking Process.
(a) Embedding
(b) Extraction
Fig. 4: Additive Spatial Watermarking Process.
3) Additive Frequency Watermarking: The scheme of this
process performs the watermark embedding in the frequency
domain. After applying the DWT to the watermark and the
video frames, the embedding process is performed in the Low-
Low (LL) subframe, then the IDWT is applied to reconstruct
the watermarked video. It consists of applying the reverse
procedure of the embedding process as shown in Figure (5).
(a) Embedding
(b) Extraction
Fig. 5: Frequency Watermarking Process.
IV. FPGA SYNTHESIS AND IMPLEMENTATION
The FPGA Implementation results of the three techniques
have been synthesised using Vivado and validated using 640 ×
480 Video Graphics Adapter (VGA) display. The video acqui-
sition has been conducted using OV7670 camera input. Visual
results are shown in Figure 6.
(a) (b)
(c) (d)
(e) (f) (g)
Fig. 6: Watermarking Implementaion Visual Results: (a-b) LSB
(c-d) Spatial (e-g) Frequency.
The synthesis results after optimization of the three water-
marking techniques are summarized in terms of resources used,
maximum operating frequencies and power consumption in
Tables (I), (II) and (III). For additive frequency watermarking,
DWT/IDWT IP-Cores has been synthesized and simulated
under the Vivado-XSim simulator. After verification and opti-
mization of the design, the generated RTL-IP will be included
in the catalog of IPs of the Vivado library. These IP-Cores
are integrated within the hardware project of the watermarking
system. The simulation results are shown in Figure (7) for the
two IP-Cores of DWT/IDWT. The generated IP-Cores are use
in the additive frequency watermarking system. The DWT and
IDWT IP-Cores modules are illustrated in Figure 8.
TABLE I: LSB Spatial Watermarking Implementation Results.
Ressources Utilisation Available Utilisation (%)
LUTs 663 203800 0.32
Registers 279 407600 0.08
FF 552 407600 0.24
Slice 324 150950 0.21
BRAM 176 445 39.55
IOB 47 500 9.40
IBUFDS 1 480 0.21
BUFGCRTL 6 32 18.75
MMCM 2 10 20.00
Maximum Frequency 130.68 MHz
Total On-Chip Power 0.311W
Efficiency [Fmax/Sclice] 0.40
TABLE II: Additive Spatial Watermarking Implmementation
Results.
Resources Utilisation Available Usage (%)
LUTs 1205 203800 0.59
Registers 337 407600 0.70
FF 968 407600 2.03
Slice 623 150950 0.41
BRAM 352 445 79.10
IOB 45 500 9.00
IBUFDS 1 480 0.20
BUFGCRTL 6 32 18.75
MMCM 2 10 20.00
Maximum Frequency 129.86 MHz
Total On-Chip Power 0.423W
Efficiency [Fmax/Slice] 0.20
TABLE III: Additive Frequency Watermarking Implementation
Results.
Ressource Utilisation Available Utilisation (%)
LUTs 16538 203800 8.11
Registers 25 407600 0.006
FF 1861 407600 0.46
Slice 754 150950 0.50
BRAM 402 445 90.34
IOB 65 500 13.00
IBUFDS 1 480 0.20
BUFGCRTL 6 32 18.75
MMCM 2 10 20.00
Maximum Frequency 123.36 MHz
Total On-Chip Power 0.827W
Efficiency [Fmax/Slice] 0.16
Fig. 7: DWT/IDWT IP-Cores Vivado-XSim Simulation Results.
(a) DWT (b) IDWT
Fig. 8: DWT/IDWT IP-Cores Modules.
RTL Architecture of the additive Frequency Watermarking
is presented in Figure 9. The decomposition of the video frames
and the watermark are ensured using customized DWT IP-Core
integrated in the design.
Fig. 9: Additive Frequency Watermarking RTL Architecture.
V. P ERFORMANCES EVALUATION
The performance evaluation results of the proposed wa-
termarking system are conducted in terms of imperceptibility,
robustness and ressources concumption.
A. Imperceptibility Assessment
Imperceptibility assessment has been conducted by studying
visibility factor influence and histograms comparisong between
original and watermarked video as the following:
1) Visibility Factor Influence: According to the results
obtained, shown in Figure (10), we notice a fairly significant
degradation in the watermark visibility for higher values of α.
(a) α=0.05 (b) α=0.15 (c) α=0.5(d) α=0.8.
Fig. 10: Visibility Factor Influence on the Watermarked Video.
Table (IV) presents the results of objective evaluation of the
watermarking system in the DWT domain for some values
of the visibility factor α, several imperceptibility metrics have
been performed in order to better characterize the robustness
of these proposed watermarking systems.
Highest PSNR values for smaller values of the visibility factor
as presented in Figure 11.
2) Histogram: According to Figure (12), we notice that the
watermark embedding does not influence in a significant way
the distribution of the watermarked video histograms.
TABLE IV: Proposed System Imperceptibility Evaluation.
Metrics\αα=0.01 α=0.05 α=0.1 α=0.5 α=0.9
PSNR(dB) 50.4680 45.4886 39.4680 25.4866 20.3830
NCC 0.7198 0.8127 0.9354 0.9996 0.9998
SSIM 0.9981 0.9180 0.8715 0.8515 0.8411
0 0.2 0.4 0.6 0.8 1
9LVLELOLW\)DFWRU
20
25
30
35
40
45
50
55
PSNR(dB)
(a) PSNR vs Visibility Factor.
0 0.2 0.4 0.6 0.8 1
9LVLELOLW\FactRr
0.7
0.75
0.8
0.85
0.9
0.95
1
NCC
SSIM
(b) NCC and SSIM vs Visibility Factor.
Fig. 11: Proposed Watermarking System Imperceptibility Eval-
uation.
B. Robustness Assessment
Robustness tests have been conducted against rotation,
compression, median filter and Gaussian noise. Results have
been as shown in Figure 13.
Four attacks types have been applied on the watermarked
video in order to assess the robustness of the watermarking im-
plmenentation namely Rotation, Compression, Gaussian Noise
and Median Filter. Table (V) presents the robustness evaluation
results of the additive frequency watermarking system for
maximum reached values of 2◦angle, 20% quality factor, 0.1
(a) Original video frame
(b) Watermarked video frame
Fig. 12: Watermarking Histogram Distribution
(a) 2◦Rotation (b) Compression (c) Median Filter (d) Gaussian Filter
(e) 2◦Rotation (f) Compression (g) Median Filter (h) Gaussian Filter
Fig. 13: Proposed System Robustness Visual Evaluation.
and 0.05 densities for the used attacks respectively beyond
which robustness is lost.
TABLE V: Proposed System Robustness Objective Evaluation.
Metric No Attack Rotation Compression Gaussian Noise Median Filter
PSNR(dB) 50.4680 3.9856 2.4141 10.9691 5.1875
SSIM 0.9981 0.0821 0.0221 0.2336 0.1796
From the results of Table (V), we find that the proposed
DWT-based additive watermarking system design approach is
not resistant to geometric and compression attacks. On the
other hand, the latter presents a strong robustness against image
processing attacks such as the median filter and the Gaussian
noise.
C. Resources consumption
The three techniques LSB spatial watermarking, additive
spatial watermarking and additive frequency watermarking in-
terms of resources usage are contrasted in Figure (14).
It is noted that the DWT additive watermarking consumes
the most resources of the FPGA platform Genesys-2 compared
to the two other watermarking systems because of the DWT
IP-Core implementation.
Table (VI) presents a summary of the maximum power and
frequency consumption for the three watermarking techniques:
!
"
Fig. 14: Video Watermarking Techniques Resources Consump-
tion Comparison.
TABLE VI: Implemented Watermarking Techniques Compari-
son.
LSB
Spatial
Additive
Spatial
Additive
DWT
Maximum Frequency (MHz) 130.68 129.86 123.36
Power Consumed (W) 0.311 0.423 0.827
D. Comparison with Similar works
TABLE VII: Proposed System Comparison with Similar Works.
Proposed
Work [10] [12] [13]
Used
Technique DWT Spatial DCT DCT/DWT
Design Approach C/VHDL VHDL VHDL VHDL
FPGA Plateform Genesys-2 Zynq-7000 Xilinx
XC5VLX330T -
Frequency 123.36MHz 150MHz 113.61MHZ 98.96MHz
Robustness -Median Filter
-Gaussian Noise --Rotation
-Compression
-Rotation
-Gaussian Filter
-Gaussian Noise
It can be concluded that the proposed work making using
af a HW/SW co-design approach has achieved comparable
results to the purely hardware implemented approaches with
more flexibility in algorithm coding. This can be considered as
valuable asset in favor of the HW/SW co-design approach and
validates its adoption real-time applications.
VI. CONCLUSION
In this work, a real-time OV7670 camera video watermark-
ing has been implemented on the FPGA platform Genesys-2
of three techniques namely LSB spatial watermarking, additive
spatial watermarking and additive frequency watermarking.
The design approach adopted has been a (SW/HW) co-design
approach in VHDL and C++ under the high-level synthesis
tool HLS-Xilinx, which allowed to design the IP-cores. The
proposed architectures are then validated using VGA displays.
The synthesis and implementation results of the proposed sys-
tem in terms of resource consumption, Timing, and power con-
sumption show that the proposed architectures present a good
compromise between performance and power consumption.
The subjective and objective evaluations of the implementations
show that watermarking in the transformed domain is more
resistant to certain attacks. And finally, a comparative analysis
between the three techniques and with similar works have been
achieved making them adaptable to several future applications.
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