A 2-PPM CMOS modulator for IR-UWB signals

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A 2-PPM CMOS Modulator for IR-UWB Signals
Adrian Popa
Fixed & Mobile Operations East
Telekom Romania Communications S.A.
Iasi, Romania
adrian_m.popa@telekom.ro
N.D. Alexandru, Radu Gabriel Bozomitu
Department of Telecommunications
Gheorghe Asachi Technical University of Iasi
Iasi, Romania
nalex@etti.tuiasi.ro, bozomitu@etti.tuiasi.ro
Abstract—This paper presents an implementation of a binary
pulse-position modulator (2-PPM) for impulse-radio ultra-
wideband (IR-UWB) systems, capable of producing an
appropriate signal to drive the final output stage of an ultra
narrow pulse generator. Compared to the usual circuits based on
voltage-controlled delay lines, this novel scheme uses digital
signal processing of the clock and data signals with a direct
implementation in CMOS technology, which makes possible to
construct also the UWB pulse generator. Simulations show that
the signal obtained as pulse sequences that are delayed using
phase modulation can be used to drive an UWB generator that
outputs pulses satisfying the requirements regarding the
regulated output spectrum.
Keywords—IR-UWB; pulse position modulation; 2-PPM;
modulation; CMOS integrates circuits; inverter; logical gates
I. I
NTRODUCTION
The IR-UWB communications is gaining interest in the
recent years in areas such as sensor networks, wireless personal
area networks (WPAN), wireless body area networks (WBAN)
[1]. A specific feature of these technologies is the pulse
transmission using low-complexity devices with very low
power consumption. When used in medicine, WBAN can
provide high-quality location-independent medical monitoring
with increased flexibility, mobility and communicability at low
costs [2, 3].
A type of modulation commonly used for these
transmissions is 2-PPM. The bit information is conveyed by
transmitting pulses with a particular time offset within the
allocated time interval. The modulator implementation must
take into account the very high operating frequencies, and also
the specific asynchronous operation of the next stage, the UWB
pulse generator. The literature reports proposed schemes of
UWB modulators using delay lines and threshold detectors
based on linear voltage ramps obtained by charging a capacitor
from a constant current source.
In the sequel it is proposed the use of a logical CMOS
structure for combining the clock signal, its inverted replica
and data signal to produce output pulses at the beginning or at
the mid-position of the bit frame. The proposed circuit operates
for a wide interval of transmission rates. Simulations show that
up to 500 Mbps transmission rates, which corresponds to a bit
frame duration of 2 ns, the time positioning of UWB pulses
respects the requirements related to synchronization and non-
coherent demodulation at receiver site [4,5].
II. IR-UWB
S
IGNAL
W
ITH
2-PPM
M
ODULATION
The IR-UWB signal is composed of very small duration
pulses having a waveform of a certain shape that determines
the signal spectrum to fit within the regulated transmit spectral
mask [4]. Binary phase modulation involve transmission of a
pulse associated to a bit frame within a particular time "chip" at
the beginning or at its middle, depending on the value of the
transmitted bit. The transmitted 2-PPM UWB signal is
expressed as [6]:
.)2/TbjTt(w)t(s
bjb
j
−−=
¦
∞
−∞=
(1)
The signal is composed of a string of waveforms w(t),
having [0, Tb/2] support interval such that w(t) and w(t-Tb/2)
should be time-orthogonal. The waveform w(t) is generated in
the bit time interval, at the time instant jǜTb or Tb/2 seconds
later, as a function of the transmitted binary information bj
ɽ{0,1} [6].
Fig. 1 illustrates the waveform of the transmitted signal for
a "01101" bit sequence.
Fig. 1. IR-UWB signal with 2-PPM modulation.
III. 2-PPM
M
ODULATORS
A delicate issue regarding the practical realization of the
UWB transmitter is the pulse generator, which requires the use
of special circuits, most operating in asynchronous mode, such
as monostable circuits triggered by the rising edge of the input
signal. The modulation of the UWB signal can be done
afterwards [7], the modulator working with analog signals,
makes the selection between signals containing the UWB pulse
with certain positioning either at the beginning or at the middle
of the bit frame, as illustrated in Fig. 2.
978-1-4673-8197-0/16/$31.00 ©2016 IEEE 353

Fig. 2. Analogue 2-PPM modulation of generated UWB pulses
However, the more efficient generation of 2 PPM UWB
pulses is done placing a modulator circuit before a single
generator, that drives it with pulses wide enough and having a
waveform that is not regulated.
A proposed solution uses a circuit that generates a linear
voltage ramp based on charging a capacitor with a constant
current, followed by a threshold comparator [8, 9].
According to the value of data bits a specific charging
current of the capacitor is selected and therefore a time offset to
activate the comparator output that generates a rising voltage
edge, as illustrated in Fig. 3. As a disadvantage, the circuit
needs a reset signal at the beginning of the frame, in order to
quickly discharge the capacitor and to reset the output of the
comparator, waiting for the next triggered pulse.
Fig. 3. 2-PPM modulator with voltage ramp and comparator.[6]
In the sequel a simpler method of obtaining excitation
pulses at the beginning of the time frame or at its middle is
proposed. This is based on the shape of the clock signal,
consisting of two portions of logical values different in the first
and second half period, and rising and falling edges.
A first idea is the use of an XOR gate having as input the
clock and data signals, as illustrated in Fig. 4. The analysis of
the obtained pulses that excite the UWB generator and emitted
signal are shown in Fig. 5.
Fig. 4. Possible 2-PPM modulator with logical XOR gate.
Fig. 5. 2-PPM NRZ input signal and output UWB generated pulses.
The XOR gate determines the intervals when the data and
clock signals do not have the same logical value. For the data
bit "0", the gate output generates a pulse "1" on the first half of
the frame, when the clock signal is "1". For the data bit "1",
the gate becomes active in the second half of the frame, when
the clock signal is "0". Thus, one obtains an output logic level
"1" that is positioned in time as a PPM modulation.
However, the scheme does not function properly in the case
of a signal with consecutives logical levels “1" and “0", when
no rising edges are present to trigger the UWB pulse generator.
The modulated signal is of NRZ (Non-Return-To-Zero) type,
inadequate to drive the pulse generator. Thus, when simulating
a "10" bit string, the "high" levels of the bit "1" and the bit next
"0" are consecutive. The generator can generate an ultra-
narrow pulse only on the rising edge of the first excitation
pulse, as shown in Fig. 5.
IV. A
N
OVEL
2-PPM
M
ODULATOR
C
IRCUIT
This deficiency can be eliminated if the modulator will
provide an excitation signal to the UWB generator composed
of pulses of a shorter duration than a half-frame. An interesting
circuit to generate short pulses has been studied. This consists
of a NAND gate driven by a rising edge signal and its delayed
replica generated by an invertor [10].
In the following it is proposed a modulator scheme using
such special circuits to obtain pulses of ultra narrow width.
Both the clock and inverted clock signals are “narrowed” by
such circuits, as shown in Fig. 6.
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Fig. 6. CMOS modulator with logical gates for IR-UWB
By passing the clock signal and its inverted replica through
two circuits that narrow the pulses, the circuit above will
generate output pulses that are positioned as 2-PPM
modulation at the beginning or at middle of the frame, but of
much shorter duration.
In this way, any of the excitation pulses will start from the
"0"state, and will present a rising edge for triggering the UWB
generator, as illustrated in Fig. 7 and Fig. 8.
Fig. 7. Correct generation of UWB PPM pulse modulation.
Fig. 8. Pulse waveforms positioning at generator input and output
For data speeds of 100-500 Mbps, the duration of the basic
frame becomes very small, of the order of ns. In this case, the
propagation of signals through CMOS gates is not negligible.
The signal path with inverted clock shows a further delay
due to inverter propagation delay, which can be reduced to 60
ps. For a lag of half-frame this delay is eliminated by
introducing a compensatory delay in the non-inverted clock
signal path. The delay is achieved by inserting a capacitor “C
compensation delay” between the NAND gate and the
subsequent inverter. The inverter in the data signal path does
not influence the pulse positioning, its delay being less than the
propagation delay of the clock signal through the NAND gate.
The delayed clock signal generates a pulse at modulator
output. The simulation results show that the excitation pulse for
bit "0" occurs at t = 0.231 ns, while for the bit "1" at t = 3.230
ns, respectively. The frame duration is 2 ns and the rising edge
for bit “1” appears at the middle of the second frame, i.e. 3 ns
later. So, the same offset relative to the clock signal is
obtained.
V. P
RACTICAL
I
MPLEMENTATION
The modulator is realized in the same 0.18 μm CMOS
structure as the UWB pulse generator based on the third
derivative of Gaussian pulse [11].
For design and simulation of circuits the Agilent ADS
software has been used. The results of Monte Carlo analysis
when varying the values of components with prescribed
tolerance is presented in Fig. 9. The graphic of waveform
signal output of the modulator acting as input to UWB
generator, and the histogram of PPM delay time prove that
modulated pulses with correct and little variation of positioning
are obtained.
The modulator is built with inverters and NAND gates. The
inverter outputs contained in the circuits used for “narrowing”
the pulses are connected with capacitors that allow the
generation of pulses with a duration less than a half-frame, but
still wide enough to be processed correctly by following logic
gates.
355

Fig. 9. Monte-Carlo simulation results: a) Modulated pulses trials for “0” and
“1"bits; b) Histogram of PPM delay
Simulations with a large number of data bits prove that the
average value of the supply current into the modulator
subcircuit is only 0.5 mA. This determines a very low power
consumption of 0.9 mW for a supply voltage of 1.8 V.
The modulator performance is summarized in Table 1.
TABLE I. 2-PPM
S
YSTEM
S
IMULATION
P
ARAMETERS
Parameters Values
T
p
- Pulse duration 0.6 ns
Pulse shape 3-rd Gaussian derivative
T
f
- Frame Time 2÷100 ns
PPM delay T
f
/2 (1÷50 ns)
PPM delay error ±30 ps
Bandwidth 3.1 – 5.1 GHz
f
clock
- clock frequency 10÷500 MHz
Data rate 10-500 Mbps
Technology 0.18 μm TSMC
Supply voltage 1.8 V
Power consumption
(modulator) 0.9 mW
VI. C
ONCLUSIONS
IR-UWB systems implementation is aimed at getting 'on-
chip' "all digital" devices that are easily achieved with low
power consumption and low costs. The 2-PPM modulation
scheme is attractive because of the simple structure of the
transmitter and receiver. Regarding transmitter implementation
the trend is to integrate in the same technology various circuits
in the transmission chain.
The proposed modulator circuit with CMOS gates scheme
uses circuit configurations to obtain narrow pulses with respect
to frame duration and with delays that are appropriate to 2-
PPM modulation. The simulations results show that the
modulated data signal are suitable to drive an UWB pulse
generator. Also, the time positioning of the generated pulses
meets the requirements of synchronization and correct
detections at the receiver.
The goal is to achieve on the same chip in a simple way and
in the same CMOS technology different stages of the UWB
transmitter, the circuit remaining the same for different pulse
durations, thus covering a wide range of data transmission
rates. The modulator circuit for UWB systems is functional up
to 500 Mbps rates for a basic frame of 2 ns. The PPM offset of
1 ns is achieved with an accuracy of ±30 ps.
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