Pietro Monsurrò

Sapienza University of Rome | la sapienza · Department of Information Engineering, Electronics and Telecommunications

The design and the characterization of a non-linear target to test an intermodulation radar was performed using the AWR design environment Version 22 by Cadence software. Two experimental setups for intermodulation measurements were realized in order to characterize connectorized or antenna-equipped devices. Both setups were modeled using the VSS s...

An adaptive biasing circuit suitable for very low-voltage design of class-AB symmetrical transconductance operational amplifiers (OTAs) is presented. A non-linear current mirror is exploited to enhance the maximum tail current as a function of the input voltage, achieving a super class-AB behavior. Robustness to process and voltage supply variation...

In the last years several ultra-low voltage (ULV) operational transconductance amplifiers (OTAs) with supply voltages below 0.5V have been proposed in the literature. To achieve high gain, multi-stage amplifiers are frequently exploited, in spite of the complexity of design and compensation approaches, whereas cascode and regulated-cascode OTA topo...

Nonlinear calibration allows enhancing the performance of analog and radiofrequency circuits by digitally correcting nonlinearities. Often, calibration is performed in the complex baseband domain, and Volterra models are used. These models have hundreds of coefficients, and easily become computationally unfeasible. This is worse in complex Volterra...

In this paper, an evolution of the Sallen-Key biquad architecture is presented, suitable for applications at very high frequency. The pole of the buffer amplifier is exploited as one of the poles of the biquad, therefore overcoming the constraints it poses on the maximum resonance frequency that can be achieved. This allows designing low-pass filte...

This paper presents a 0.3 V rail-to-rail three stage OTA. Due to the topology of the input stage, to the three gain stages and to subthreshold operation, the proposed OTA exhibits high dc gain in spite of the bulk-driven input. In addition, thanks to the adoption of two fully differential stages and the usage of an additional local common-mode feed...

This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias curr...

This paper presents a novel topology of ultra‐low voltage (ULV) operational transconductance amplifier (OTA), which exploits several design techniques to achieve high efficiency, symmetrical slew rate, good linearity, and robustness in spite of ultra‐low voltage operation. Simulations in a commercial 130‐nm CMOS technology with 0.3‐V supply voltage...

Volterra models allow modeling nonlinear dynamical systems, even though they require the estimation of a large number of parameters and have, consequently, potentially large computational costs. The pruning of Volterra models is thus of fundamental importance to reduce the computational costs of nonlinear calibration, and improve stability and spee...

The use of capacitive sensors has advantages in different industrial applications due to their low cost and low-temperature dependence. In this sense, the current-mode approach by means of second-generation current conveyors (CCIIs) allows for improvements in key features, such as sensitivity and resolution. In this paper, a novel architecture of C...

In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tr...

In this work a novel bulk-driven (BD) ultra-low-voltage (ULV) class-AB operational transconductance amplifier (OTA) which exploits local common mode feedback (LCMFB) strategies to enhance performance and robustness against process, voltage and temperature (PVT) variations has been proposed. The amplifier exploits body-to-gate (B2G) interface to inc...

Analysis, design, and characterization of an E-band Variable Gain Amplifier (VGA) in SiGe BiCMOS commercial technology is presented. VGA topologies are compared in terms of their capability to contribute to receiver linearity and dynamic range. The proposed VGA is based on a Gilbert multiplier cell exploiting current cancellation to enhance control...

In this paper a novel linear transconductor topology is proposed, where class-AB behavior based on adaptive biasing is exploited to improve the linear range. The adaptive biasing circuit is based on the Winner-Take-All topology already used for class-AB OTAs, and optimized to improve the linearity, and the proposed transconductor features a gain co...

A novel architecture and design approach which make it possible to boost the bandwidth and slewrate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, ba...

High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasing filters in the multi-GHz range. Asynchronous Time-Interleaved (ATI) digitizers also need low-pass filters before digitization, and additional requirements on their design are set by this specific application. In integrated solutions, inductor-less fi...

In this paper we present a novel Operational Transconductance Amplifier (OTA) topology based on a dual path body-driven input stage, exploiting body-driven current mirror active load and targeting ultra-low-power (ULP), ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node a...

A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a...

In this work, we present a low-power 2nd order band-pass filter for neural recording applications. The central frequency of the passband is set to 375Hz and the quality factor to 5 to properly process the neural signals related to the onset of epileptic seizure, and to strongly attenuate all the out of band biological signals and electrical disturb...

This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed-forward stage to obtain double pole-zero cancellation, and ideally single-pole behavior, in a three-stage Miller amplifier. The approach allows designing a three-stage operational transconductance amplifier (OTA) with one dominant pole...

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all...

A 4th‐order Butterworth class‐AB current‐mode low‐pass filter is proposed, based on second‐generation Current Conveyors (CCII). Class‐AB operation allows high‐power efficiency and driving large loads with small quiescent currents. The CCII topology uses the class‐AB output buffer with error amplifiers: this topology is known to be sensitive to mism...

An innovative low‐voltage low‐power complementary metal‐oxide‐semiconductor (CMOS) gain boosting approach is presented. It exploits complementary gate‐driven gain boosting and adopts forward body bias, resulting in the minimum possible supply requirement of one threshold plus two saturation voltages, without requiring any additional current branch....

Two architectures of 4-channel mixing-filtering-processing (MFP) digitizers are presented and compared. Both architectures use four analogue-to-digital converters (ADCs), but differ in terms of layout, and are named parallel and hierarchical, respectively. The hierarchical architecture is entirely novel, while the parallel one is at present only en...

A novel class AB operational transconductance amplifier (OTA) topology is proposed, based on a class AB flipped voltage follower. The OTA has class AB behavior, with current boosting both for the load and the compensation capacitors. It has a high gain of (gmr0)4, obtained using a two‐stage structure with cascoded stages, and is a two‐stage Miller‐...

High‐frequency (around 10 GHz) filters are necessary for many applications, in anti‐aliasing filters for high‐speed data converters or optical communications. Modern SiGe technology allows implementing radio‐frequency circuits up to about 100 GHz. At the lower frequencies around 10 GHz, the size of passive components is a concern, and inductorless...

Two alternative architectures of 4-channel mixing-filtering-processing (MFP) digitizers are presented. Both architectures use four analogue-to-digital converters (ADCs), but differ in terms of layout, and are named parallel and hierarchical. Unlike conventional time-interleaved digitizers, which require ADCs characterized by relaxed sampling rate b...

A 2-channel digitizer based on a mixing-filtering-processing (MFP) strategy capable of granting ultra-high bandwidth and sampling rate is presented. The digitizer requires suitable digital signal processing resources, which consist of several dedicated integrated circuits (ICs), to produce a digital representation of the input signal. Processing is...

A class-AB OTA (operational transconductance amplifier) topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications. High efficiency is achieved by reusing transistors both for class-AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply v...

The most recent digitizers available on the market can grant real-time bandwidth up to 70 GHz and beyond. Such a performance is achieved by transforming the signal at the analog front-end in order to produce two or more instances characterized by reduced bandwidth; the different instances are acquired by means of less demanding ADCs and combined to...

The low power instrumentation amplifier (IA) presented in this paper has been designed to be the front-end of an integrated neural recording system, in which common-mode rejection ratio (CMRR), input referred noise and power consumption are critical requirements. The proposed IA topology exploits a differential-difference amplifier (DDA) whose diff...

Power analysis attacks (PAAs), a class of side-channel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a register-transfer level (RTL) countermeasure to increase the security of cryptographic...

An improvement of a standard fully differential class-AB symmetrical OTA topology is proposed in this paper to enhance the common-mode behavior. Common-mode behavior could be critical in fully differential class-AB OTAs, where the total current is not fixed and differential to common-mode conversion could therefore be present. A signal proportional...

We present a low voltage low power architecture for an integrated current conveyor (CCII) topology, designed to decrease the stand-by power dissipation without affecting the CCII transient performance. In the proposed circuit, implemented in a standard AMS 0.35um CMOS technology, an extra current flows into the circuit only when an input voltage va...

This paper presents a fully differential class-AB current mirror OTA that improves the common-mode behavior of a topology that presents very good differential-mode performance but poor common-mode rejection ratio (CMRR). The proposed solution requires a low-current auxiliary circuit driven by the input signal, to compensate the effect of the common...

New linear models to calibrate 4-channel time-interleaved ADCs are proposed and investigated. The ideal 4-periodic correction filters which cancel distortions are computed as a function of the error filters, which model the analog transfer function of each channel, including the sampling time. These correction filters are then approximated as a lin...

An analytic design-oriented model of phase and frequency modulated microwave optical links has been developed. The models are suitable for design of broadband high dynamic range optical links for antenna remoting and optical beamforming, where noise and linearity of the subsystems are a concern Digital filter design techniques have been applied to...

We investigate AM/PM distortion models and compare them with baseband (BB) Volterra models. We show that the AM/PM model can be considered a special case of memoryless baseband Volterra models, and that adding memory can improve modeling accuracy by allowing the simulation of more complex nonlinearities. We report models of an LNA, a downconversion...

A Volterra model is used to calibrate a pipeline ADC simulated in Cadence Virtuoso using the STMicroelectronics CMOS 45 nm process. The ADC was designed to work at 50 MSps, but it is simulated at up to 125 MSps, proving that calibration using a Volterra model can significantly increase sampling frequency. Equivalent number of bits (ENOB) improves b...

Digital IF receivers face a trade-off between the required selectivity of the frequency response and the value of the IF frequency: higher IF frequencies make it easier to reject the image frequency of the mixer, but increase the required Q values in the anti-aliasing filter. However, high-Q filters are hard to implement in IC technologies. The con...

A novel class-AB Flipped Voltage Follower is proposed, suitable for low-voltage low-power CMOS implementation in advanced technology nodes. Simulations have been performed using STMicroelectronics models for the 45nm technology. The Flipped Voltage Follower allows low output impedance and high linearity by means of a feedback loop. However, like th...

In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub- 50nm CMOS integrated circuits on the internally processed data. Spice simulations of static power have been carried out to show that the coefficient of variation of nanometer logic gates is increasing with the scaling of CMOS technology...

An analytic design-oriented model of microwave optical links has been developed. The core of the model is the non-linear and noise model of a Mach-Zehnder LiNbO

A new calibration technique for time-interleaved analog-to-digital converters is proposed, based on Hermitianity-preserving complex Taylor approximations of the frequency response of the correction filters. Calibration is interpreted as approximating these filters with linear combinations of base filters obtained by the proposed Taylor expansion. K...

We propose a novel recursive least squares (RLS) algorithm that exploits the Frisch-Waugh-Lovell theorem to reduce digital complexity and improve convergence speed and algorithmic stability in fixed-point arithmetic. We tested the new algorithm in the digital background calibration section of a four-channel time-interleaved analog-to-digital conver...

Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier nonlinearity, and incomplete settling. It is possibl...

Bandwidth mismatch is one of the mechanisms that reduce linearity in time-interleaved analog-to-digital converters (TI-ADCs). Models of bandwidth mismatch have been already proposed in the literature: this brief extends them to subsampling signals, validates them against circuit-level simulations, and investigates their effect on linearity in subsa...

The last twenty years of financial innovation have produced an impressive amount of new instruments and institutions which have greatly improved the efficiency of national and international financial markets. However, the ongoing economic crisis shows that many of these innovations did not take adequately into account problems like liquidity and cr...

In this paper we extend the figures of merit for class AB symmetrical OTAs to the fully differential case and compare topologies from the literature. This analysis shows that the power consumption of the CMFB can have a significant role in determining the efficiency of the OTA, but on the other hand a CMFB is needed both to set the desired output c...

SUMMARYA design procedure for high-order continuous-time intermediate-frequency band-pass filters based on the cascade of low-Q biquadratic cells is presented. The approach is well suited for integrated-circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivit...

An analytic design-oriented model of microwave optical link has been developed. The core of the model is the nonlinear and noise model of a Mach-Zehnder LiNbO3 interferometer. Different linearized microwave links, based on the use of an auxiliary modulator, have been designed by using the proposed model: significant improvement of the 3rd-order int...

In this paper we present a methodology to calibrate and correct frequency-dependent errors in phased-array antennas with large signal bandwidth and large size. If the receivers are not narrow-band, the hypotheses of constant gain and group delay are not valid. If the frequency responses of the receivers are affected by mismatches, this will also im...

The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors. The proposed approach comprises a capacitance to current converter providing current-summing and current-differencing capability. It also exploits an autotuning feedback loop to control the common-mode current,...

This paper investigates the implementation of radar algorithms on Graphics Processing Units (GPUs). The focus is on electronically scanned search radars. GPUs enable to develop high performance digital processing systems with limited development time. It is possible to employ a single commercial board (an NVIDIA GeForce 680 GTX in our case) to perf...

A novel architecture for optical beamforming is presented, and its implementation as an integrated multi-chip system is discussed. Modeling and design methodology of the key components of the system, i.e. the linearized electro-optic external modulator and the array of tunable true delay lines, is detailed. Measurements on a linearized modulator ar...

We analyze the effects of relative mismatches in transconductances and in capacitances onto the magnitude of the Gm-C biquad filter section. It is confirmed that deviation from the ideal magnitude increases with Q and with mismatches, being those associated with transcondunctances the relevant ones. The obtained data can be used at an early design...

We propose an algorithm for the digital background calibration of time-interleaved analog-to-digital converters (ADCs), which is capable of accurately calibrating errors due to offset, gain, and timing mismatches, as well as nonlinearities due to errors in the channel ADCs. Calibration is performed in the background without interrupting data conver...

A novel technique for the digital background calibration of time-interleaved analog-to-digital converters is proposed. The technique corrects at the same time for both errors due to gain, offset and timing mismatches among the time-interleaved channels and errors due to nonlinearities in the channels, for instance due to capacitor mismatches in swi...

With the progressive reduction of MOS transistors minimum dimension and their associated supply voltages, the body terminal—considered in the past as an exclusive source of unwanted second order effects—has been advantageously exploited by digital designers and is also becoming an attractive opportunity for the implementation of high-performance an...

An architecture for MDAC stages with low sensitivity to finite opamp gain is proposed, that allows designing high- precision pipeline ADCs in deep submicron technologies. The standard MDAC architecture is modified by inserting a voltage follower in the feedback path, and zero gain error is achieved if a relationship between the gain of the main opa...

In this paper we present a low-power low-voltage class- AB amplifier with rail-to-rail output swing capable of operating from 0.5V to 1.0V of supply voltage, and two Sample & Hold (SHA) circuits based on this amplifier. The bias current and the bandwidth of the amplifier depend on the voltage supply, so that for low-power operation a low supply vol...

In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class- AB FVF buffers previously prese...

In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common- mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the prop...

This paper presents a design procedure for high-order continuous time low-pass filters based on the cascade of biquadratic cells. The proposed approach is amenable for integration, as it takes into account the maximum capacitance spread imposed by the available technology, and also allows a tradeoff between noise and maximum linear range to be met,...

In this paper we propose a variable-gain transimpedance amplifier suitable for low-power applications. Its noise, bandwidth and input impedance performance are similar to a more conventional regulated-cascode common-gate transimpedance with resistive load, with the same power consumption and gain performance. The proposed amplifier has, however, va...

In this paper, a design flow for the design of calibrated pipeline analog-to-digital converters (ADCs), and a framework for their behavioral modeling is presented. The model includes also second order effects such as nonlinearities and linear and nonlinear memory errors, thus allowing fast and accurate simulations of the ADC behavior. In this way,...

Solutions for the design of low-voltage sample-and-hold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4- V_PP differe...

A CMOS differential amplifier cell for minimum supply requirements is presented. The solution uses transistors in strong inversion and an original biasing scheme that exploits the bulk terminals of the transistor pair to accurately set the quiescent current and provide common-mode control. As a result, we avoid the use of the tail current source ad...

The body-driven variant of the gain-boosting technique is here exploited to design a CMOS transconductance amplifier with minimum supply below 1 V. When compared with the conventional gain-boosting technique, the proposed body-driven approach reduces the minimum supply requirement by two thresholds in a rail-to-rail amplifier exploiting two complem...

This paper presents a unity-gain amplifier architecture, which, unlike already known solutions, provides a theoretically zero gain error without requiring an infinitely large loop gain. The architecture is based on two amplifiers nested in a feedback configuration, which allows a straightforward complementary metal-oxide-semiconductor (CMOS) implem...

In this paper we present a gain enhancement technique for very low-voltage deep sub-micron amplifiers based on the use of a CCH-based negative impedance converter. Relaxed specifications on the current conveyor allow an easy implementation of this technique in a sub-1 V environment, where common topologies such as the cascode and the differential p...

A modification of the background digital calibration procedure for A/D converters by Li and Moon is proposed, based on a method to improve the speed of convergence and the accuracy of the calibration. The procedure exploits a colored random sequence in the calibration algorithm, and can be applied both for narrowband input signals and for baseband...

A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-mum process and powered with 2.5 V and 1 mA, show that total harmon...

A minimum-supply rail-to-rail differential stage architecture is presented. It exhibits easy cascading features and unlike previous similar solutions does not critically affect CMRR. Starting from this block, a fully-differential two-stage amplifier is designed using 0.7-V supply in a 130-nm CMOS technology. Simulations show a 47-dB dc differential...

A low-voltage CMOS amplifier exploiting a new body-driven gain boosting technique is described. Compared to the standard gain boosting approach, the proposed one reduces the minimum supply by one threshold voltage in the single structure, and by two thresholds in an amplifier exploiting two complementary versions. Simulations using a 130-nm process...

For very high frequency applications feedback is not a suitable technique to be employed. In order to achieve high gain and large bandwidth, several open-loop stages are cascaded. In this paper we show that it is possible to improve the bandwidth of a cascaded amplifier, given constraints on input resistance, load capacitance and total bias current...