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Introduction
Publications
Publications (88)
This work proposes an execution model for massively parallel systems aiming at ensuring the communications overlap by the computations. This model is named SCAC: Synchronous Communication Asynchronous Computation. This weakly-coupled model separates the execution of communication phases from those of computation in order to facilitate their overlap...
Nowadays, recent intensive signal processing applications are evolving and are characterized by the diversity of algorithms (filtering, correlation, etc.) and their numerous parameters. Having a flexible and pro-grammable system that adapts to changing and various characteristics of these applications reduces the design cost. In this context, we pr...
Tunisian Workshop on Embedded Systems Design (TWESD’2014)
The performance of massively parallel processing system depends mostly on the control configuration that is inherently part of the system. In particular, centralized control configuration is rigid and limits system scalability, and distributed control configuration is difficult to control in processing elements (PEs) interaction. Maintaining a flex...
Complexity in the digital systems integration rises from the heterogeneity of the components integrated in a chip. The simulation or code generation of such systems require to validate methodologies, platforms and technologies to support integration, verication and programming, of complex systems composed of heterogeneous virtual components. Severa...
The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), where the processing stage and that of setting up the communication mechanism need several clock periods. Subnetting is the strat...
Due to the growing computation rates of intensive signal processing applications, using Multiprocessor System on Chip (MPSoC) becomes an incontrovertible solution to meet the functional requirements. Today, Electronic System Level (ESL) design is considered a vital premise to overcome the design complexity intrinsic in the heterogeneity of these de...
Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. Massively parallel embedded systems specifically deal with the optimized usage of such hardware resources to efficiently execute their funct...
Model-Driven Engineering (MDE) based approaches have been proposed as a solution to cope with the inefficiency of current design methods. In this context, this paper presents an MDE-based framework for rapid SIMD (Single Instruction Mul- tiple Data) parametric parallel SoC (System-on-Chip) prototyp- ing to deal with the ever-growing complexity of s...
Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communic...
This chapter presents a High Level Synthesis (HLS) flow dedicated to intensive signal processing applications. Model Driven Engineering (MDE) is the skeleton of this flow. The benefits of extending this software technology to hardware design are used to solve major difficulties encountered by usual HLS flows. Both users and designers of the flow ta...
Significant advances in the field of configurable computing have enabled parallel processing within a single Field- Programmable Gate Array (FPGA) chip. This paper presents the implementation of a flexible and programmable Single Instruc- tion Multiple Data (SIMD) processing system on FPGA that can be adapted to the application. Its implementation...
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device. These parallel systems require a cost-effective yet high-performance interconnection scheme to provide the needed communications between processors. The massively parall...
The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communica- tion networks are considered as one of the challenges facing researchers. This work describes the FPGA implementation of two reconfigurable and flexible communication networks integrated into mppSoC. An mppSoC system...
Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communic...
Single instruction multiple data processors are increasingly used in embedded systems for multimedia applications because of their area and energy-efficiency. Neighboring communications between the processing elements are a key issue in SIMD processors. They are present in most data parallel applications. However, the lack of flexibility in major p...
This paper demonstrates that the Model Driven Engineering approach is reliable for the development of codesign environments dedicated to embedded systems. From a UML model of a data parallel application, the Gaspard environment is able to generate an hardware accelerator which executes the modeled application. All the potential parallelism of a giv...
As the size, hardware complexity, and programming diversity of parallel systems continue to evolve, the range of alternatives for implementing a task on these systems grows. Choosing a parallel algorithm and implementation becomes an important decision, and the choice has a significant impact on the execution time of the application. This paper foc...
Abstract To efficiently use the tremendous,amount,of hard- ware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC), new design methodologies and tools are needed to reduce the development,complexity of such systems. In this paper, we present an efficient MPSoC design environment, Gaspard2. It uses the new standard MARTE (...
This report presents the benefits of using the Model Driven Engineering (MDE) methodology to solve major difficulties encountered by usual high level synthesis (HLS) flows. These advantages are highlighted in a design space exploration environment we propose. MDE is the skeleton of our HLS flow dedicated to intensive signal processing to demonstrat...
Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. High performance embedded systems specifically deal with the optimized usage of such hardware resources to efficiently execute their functio...
In this paper, we first present an efficient Multi-Processor Systems-on-Chip design methodology based on Model-Driven Engineering. Later, a deployment profile is introduced to allow IP reuse and to carry multilevel implementation details. With this methodology, simulations at different levels are automatically generated, reducing the cost of target...
This paper introduces a new flow able to lit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. The flow is based on iterative refactoring and transformations of the application. From the resulting application, a VHDL code is generated. This code is finally used to simulate or synthesize the a...
MppSoC is a SIMD architecture composed of a grid of pro- cessors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution of the famous massively parallel systems pro- posed at the end of the eighties. We claim that today such a machine may be integrated in a single chip. On one side, new d...
Abstract— With the,advent,of multi-processor,Systems-onChip (MpSoC), the need for modeling the distribution of a parallel application onto a parallel hardware,architecture is increasing. The recent standard,profile for the modeling,and analysis of realtime and embedded systems (MARTE) provides,a notation,for the modeling,of regular,distributions. T...
With the increase of amount of transistors which can be contained on a chip and the constant expectation for more sophisticated applications, the design of Systems-on-Chip (SoC) is more and more complex. In this paper, we present the use of model transformations in the context of SoC co-design. Both the hardware part and the software part of a SoC...
The ModEasy project seeks to develop techniques and software tools to aid in the development of reliable microprocessor based electronic (embedded) systems using advanced development and verification systems. The tools are evaluated in domains such as the automotive sector for reactive cruise control and anti-collision radar. While current developm...
This document describes the current UML profile of Gaspard2. This profile extends the UML semantics to allow the user to describe a SoC (System-on-Chip) in three steps: the application (behavior of the Soc), the hardware architecture, and the association of the application to the hardware architecture. The application is represented following a dat...
Anti-collision radars help prevent car accidents by detecting obstacles in front of vehicles equipped with such systems. This task traditionally relies on a correlator, which searches for similarities between an emitted and a received wave. Other modules can then use the information produced by the correlator to compute the distance and the relativ...
The ModEasy project seeks to develop techniques and software tools to aid in the development of reliable microprocessor based electronic (embedded) systems using advanced development and verification systems. The tools are to be evaluated in practical domains such as the automotive sector for reactive cruise control and anti-collision radar. We cho...
Abstract The ARTiS system,is a real-time extension,of the GNU/Linux scheduler,dedicated,to SMP (Symmetric Multi-Processors) systems. It allows to mix,High Per- formance,Computing,and,Real-Time. ARTiS exploits the SMP architecture,to guarantee,the preemption,of a processor,when,the system,has to schedule,a real-time task. The implementation,is avail...
MppSoC is a SIMD architecture composed of a grid of extended MIPS R3000 processors, called Processing Ele- ments (PEs). This embedded system gives interesting per- formances in several modern applications based on parallel algorithms. Communication is clearly a key issue in such a system. In fact, regular communication between the PEs are assumed b...
Recent research have demonstrate interests in a codesign framework that allows description refinement at different abstraction level. We have proposed such a framework that allows SoC resources allocation for regular and repetitive tasks found in intensive multimedia applications. Nevertheless, the framework does not directly target reconfigurable...
The MARTE RFP (Modeling and Analysis of Real-Time and Embedded systems) was issued by the OMG in February 2005. This request
for proposals solicits submissions for a UML profile that adds capabilities for modeling Real Time and Embedded Systems (RTES),
and for analyzing schedulability and performance properties of UML specifications. One of the par...
The ARTiS system, a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems is proposed. ARTiS exploits the SMP architecture to guarantee the preemption of a processor when the system has to schedule a real-time task.
The basic idea of ARTiS is to assign a selected set of processors to real-time operatio...
SoC co-design requires to master a lot of different abstraction levels, different simulation techniques, different synthesis tools. Due to the evolution of the technologies, the best one is the one to come. Evolution of an embedded system both hardware and software, is not simple. The business logic has to be kept and the technical aspect has to be...
SystemC is a quasi open source event driven HDL (hardware description language) reference simulator which was introduced in September 1999 from the OSCI. At first, it meant to be a replacement for VHDL, and, although SystemC can be use for RTL modeling, it is now envisioned by the community as a high level system simulator. SystemC inherits all the...
The ARTiS system,is a real-time extension,of the GNU/Linux scheduler,dedi- cated to SMP (Symmetric Multi-Processors) systems. It allows to mix High Performance Computing,and real-time. ARTiS exploits the SMP architecture to guarantee,the preemp- tion of a processor when,the system,has to schedule,a real-time task. The implementation is available as...
The Model-Driven architecture is an initiative by the Object Management Group (OMG) to define an approach to software development based on modeling and automated mapping of models to implementations. The basic MDA pattern involves the definition of a platform-independent model (PIM) and its automated mapping to one or more platform-specific models...
The MARTE RFP (Modeling and Analysis of Real-Time and Embedded systems) was voted by OMG in February 2005. This request for proposals solicits submissions for a UML profile that adds capabilities for modeling Real Time and Embedded Systems (RTES), and for analyzing schedulability and performance properties of UML specifications. One of the particul...
ARTiS is a real-time extension of GNU/Linux dedicated to SMP systems (Symmetric Multi-Processors). ARTiS divides the CPUs of an SMP system into two sets: real-time CPUs and non real-time CPUs. Real- time CPUs execute preemptible code only, thus tasks running on these processors perform predictably. If a task wants to enter into a non-preemptible se...
We propose the ARTiS system, a real-time extension of GNU/Linux dedicated to SMP (Sym-metric Multi-Processors) systems. ARTiS exploits the SMP architecture to guarantee the pos-sible preemption of a processor when the system has to schedule a real-time task. The basic idea of ARTiS is to assign a selected set of processors to real-time operations....
ARTiS is a project that aims at enhancing the Linux kernel with better real-time properties. It allows to retain the flexibility and ease of development of a normal application for the real-time applications while keeping the whole power of SMP (Symmetric Multi-Processors) systems for their execution. Based on the introduction of an asymmetry betwe...
High-throughput real-time systems require non-standard and costly hardware and software solutions. Modern workstation can represent a credible alternative to de- velop real-time intensive signal processing applications. Furthermore, the programming model of Kahn Process Networks (KPN) corresponds completely to this kind of applica- tions and ts per...
Taking into account the hardware architecture specificities is a crucial step in the development of an efficient application. This is particularly the case for embedded systems where constraints are strong (real-time) and resources limited (computing, power). This approach is called co-design, and it is found more or less explicitly in ADLs. Much w...
The development of embedded applications is very difficult. Several different languages are usually used to specify different parts of the application or of the hardware. Dealing with so many languages can be daunting. A separation of the preoccupations: application, hardware architecture, association between them and the simulation or execution te...
Complexity in the digital systems integration rises from the heterogeneity of the components integrated in a chip. The aim of the Sophocles project is to validate methodologies, platforms and technologies to support integration, verification and programming, over a distributed environment, of complex systems composed of heterogeneous virtual compon...
Real-time intensive signal processing applications have been traditionally deployed on various custom platforms. Meanwhile, the enterprise computing market had spurred the advent of inexpensive and powerful systems based on widely available processors. Today, SMP systems associating a potentially large number of recent processors are deemed to cope...
In this paper, we present GASPARD (Graphical Array Specification for Parallel and Distributed computing), our visual programming environment devoted to the development of parallel applications. Task and data parallelism paradigms of parallel computing are mixed in GASPARD to achieve a simple programming interface. We use the printed circuit metapho...
Array-OL, developed by Thomson Marconi Sonar, is a programming language dedicated to signal processing. An Array-OL program specifies the dependencies between array elements produced and consumed by tasks. In particular, temporal dependencies may be specified by referencing elements that belong to an infinite dimension of an array.
A basic compilat...
Gaspard is a visual programming environment devoted to the development and control of scientific parallel applications. par The two paradigms of parallel programming (task and data parallelism) are mixed in Gaspard: a hierarchy of task graphs operates on array flows. These two levels are mixed in a common metaphor. An application is designed as a p...
Matrix manipulation programs are easily developed using a visual language. For signal processing, a graph of tasks operates on arrays. Each task iterates the same code on different patterns tilling these arrays. In this case visual specifications of dependencies between the pattern elements are enough to define an application. From the ARRAY-OL lan...
The Gaspard (Graphical Array Specification for PARallel and Distributed computing) project is a visual specification environment for data-parallelism. We describe here the specification model used in Gaspard. This model inherits from the Array-OL one. We then define an SQL inspired approach to intensive data treatment that proposes a language to de...
Programming irregular and dynamic data-parallel algorithms must consider the effect of data distribution. The implementation of a load balancing algorithm is quite a difficult task for the programmer. However, a load balancing strategy may be developed independently of the application. The integration of such a strategy into the data-parallel algor...
. Most data-parallel languages use arrays to support parallelism. This regular data structure allows a natural development of regular parallel algorithms. The implementation of irregular algorithms requires a programming effort to project the irregular data structures onto regular structures. We first propose in this paper a classification of exist...
Signal processing applications are bound by severe constraints:
efficiency an reliability. To obey these constraints two main approaches
exist: the synchronous approach and the asynchronous one. But, in
practice, each style tends to be weak where the other is strong. Work
presented in this paper is part of a project that aims at combining the
respe...
The basic features of our work in progress that aims at combining
the respective advantages of the synchronous and synchronous approach
for signal and real-time image processing are illustrated by the way of
an example. This example is based on the implementation of the
high-level code of a distributed MPEG-like real-time image coder
A new synchronous-asynchronous method for complex signal and real-time processing applications is introduced in this paper. Indeed, the synchronous approach corresponds to an ideal formal context for reasoning about complex timing relations which naturally arise between program's signals. From a synchronous specification of complex real-time and si...
We present in this paper a new approach to the problem of programming complex real-time applications on distributed heterogeneous architectures. Assuming that the synchronous and asynchronous models have both significant advantages, we propose to merge them in a single framework. Indeed, the synchronous model provides the properest formal context t...
Data-parallel languages support a single instruction flow; the parallelism is expressed at the instruction level. Actually, data-parallel languages have chosen arrays to support the parallelism. This regular data structure allows a natural development of regular parallel algorithms. The implementation of irregular algorithms necessitates a programm...
In this paper, we present several methods for load balancing data in a SIMD computer. There are two types of approach; either global or local. With an easy example, we showed that dynamic load balancing for SIMD data-parallel computers can really improve the performance of the system and is as efficient as in the MIMD case. We plan to work on the c...
The HELP project proposes a model of data-parallel programming allowing a programmer to develop an algorithm the nearest of his thought. Usually, for many parts of a data-parallel program, the manipulations of data could be modelized as geometrical migrations in side a cartesian reference space.We define the language C-HELP in the frame of explicit...
Massively parallel architectures perform treatments on large sets of data. For this purpose, modern supercomputers have thousands processor elements. But the problem size we can solve with this kind of machines is often limited by the PE-memory available. For instance, the MasPar MP-1 has 1K to 16K processor elements, with 16 Kbytes to 64 Kbytes of...
In the framework of data parallel programming, data mapping and physical mapping characterize existing languages. Our model HELP (Hyper-Espace et Langage Paralle`le) introduces the hyper-space notion. The programmer handles data parallel objects using two programming levels. At the macroscopic level, geometrical operators provide explicit com...
In this paper we describe the data parallel programming environment "HelpDraw" which,through some interactive and graphical manipulations, allows to express (or translate) the userdata parallel thought in a data parallel code without compelling him to learn a particular language.HelpDraw also provides the dual part of the code generation: the code...
Fortran is the main language used on supercomputer today. Indeed, all supercomputers compilers have extensions, providing language features for explicit vector handling, to Fortran 77. These extensions are different on each machine and their functions are limited. Even with the next standard Fortran 8x, vector syntax is incomplete. EVA is an explic...
High performance computers are centered around the concept of vector processing. The first super-computer generation is single processor oriented. The last trends introduce parallel processing concepts in this field (e.g. Cray 2). In this context, we propose to associate a specialized processor in vector addressing to vector processors. This one ta...
Applications that require a combination of high-performance computing capabilities and real-time behavior, although pervasive (simulation, medicine, training, multimedia communications), often rely on specific hardware and software components that make them high performance but expensive, and quite difficult to develop, validate and moreover upgrad...
In this paper we present a distributed simulation environment for System-on-Chip (SoC) design. Our approach enables automatic generation of, geographically distributed, SystemC simulation models for IP-based SoC design and eases communication between heterogeneous parts of the simulation. The SystemC simulation model follows a client/server archite...
The ModEasy project seeks to develop techniques and software tools to aid in the development of reliable microprocessor based electronic (embedded) systems using advanced development and verification systems. The tools are evaluated in domains such as the automotive sector for reactive cruise control and anti-collision radar. While current developm...
Le système ARTiS est une extension temps-réel de GNU/Linux dédiée aux architectures multiprocesseurs symétriques (SMP). ARTiS exploite la caractéristique SMP de l'architecture pour garantir la possible préemption d'un processeur quand le système doit ordonnancer une tâche temps-réel. Le principe d'ARTiS est d'identifier un ensemble de processeurs d...
The augmentation of number of gates on chip makes SOC design more dicult. So we have to work on SOC design tools to make designer work easier and manage all the available gates. We propose an embedded Linux co-simulation with hardware simulation at a high level of abstrac- tion (TLM) to verify the system very early in the design flow. This will all...
Th. : Inform. : Lille 1 : 1992 ; 863.
